[people/ms/u-boot.git] / board / freescale / p1010rdb / tlb.c

/*
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
			MAS3_SX|MAS3_SW|MAS3_SR, 0,
			0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
			MAS3_SX|MAS3_SW|MAS3_SR, 0,
			0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
			MAS3_SX|MAS3_SW|MAS3_SR, 0,
			0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
			MAS3_SX|MAS3_SW|MAS3_SR, 0,
			0, 0, BOOKE_PAGESZ_4K, 0),

	/* TLB 1 */
	/* *I*** - Covers boot page */
	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 0, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_SPL_NAND_BOOT
	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 10, BOOKE_PAGESZ_4K, 1),
#endif

	/* *I*G* - CCSRBAR */
	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, 1, BOOKE_PAGESZ_1M, 1),

#ifndef CONFIG_SPL_BUILD
	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
			0, 2, BOOKE_PAGESZ_16M, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
			CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
			0, 3, BOOKE_PAGESZ_16M, 1),

#ifdef CONFIG_PCI
	/* *I*G* - PCI */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, 4, BOOKE_PAGESZ_1G, 1),

	/* *I*G* - PCI I/O */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, 5, BOOKE_PAGESZ_256K, 1),
#endif
#endif

	/* *I*G - Board CPLD  */
	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, 6, BOOKE_PAGESZ_256K, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, 7, BOOKE_PAGESZ_1M, 1),

#if defined(CONFIG_SYS_RAMBOOT) || \
	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
			0, 8, BOOKE_PAGESZ_1G, 1),
#endif

#ifdef CONFIG_SYS_INIT_L2_ADDR
	/* *I*G - L2SRAM */
	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
		      0, 11, BOOKE_PAGESZ_256K, 1)
#endif
};

int num_tlb_entries = ARRAY_SIZE(tlb_table);
Commit	Line	Data
49249e13 PA	1	/*
	2	* Copyright 2010-2011 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
49249e13 PA	5	*/
	6
	7	#include <common.h>
	8	#include <asm/mmu.h>
	9
	10	struct fsl_e_tlb_entry tlb_table[] = {
	11	/* TLB 0 - for temp stack in cache */
	12	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
	13	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	14	0, 0, BOOKE_PAGESZ_4K, 0),
	15	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
	16	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
	17	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	18	0, 0, BOOKE_PAGESZ_4K, 0),
	19	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
	20	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
	21	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	22	0, 0, BOOKE_PAGESZ_4K, 0),
	23	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
	24	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
	25	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	26	0, 0, BOOKE_PAGESZ_4K, 0),
	27
	28	/* TLB 1 */
	29	/* I** - Covers boot page */
f64bd7c0 PK	30	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
	31	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	32	0, 0, BOOKE_PAGESZ_4K, 1),
fbe76ae4	33	#ifdef CONFIG_SPL_NAND_BOOT
0fa934d2 PK	34	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
0fa934d2 PK	35	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
f64bd7c0 PK	36	0, 10, BOOKE_PAGESZ_4K, 1),
f64bd7c0 PK	37	#endif
49249e13 PA	38
	39	/* IG* - CCSRBAR */
	40	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
	41	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	42	0, 1, BOOKE_PAGESZ_1M, 1),
	43
0fa934d2	44	#ifndef CONFIG_SPL_BUILD
49249e13 PA	45	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
	46	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
	47	0, 2, BOOKE_PAGESZ_16M, 1),
	48
	49	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
	50	CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
	51	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
	52	0, 3, BOOKE_PAGESZ_16M, 1),
49249e13	53
505c293f	54	#ifdef CONFIG_PCI
49249e13 PA	55	/* IG* - PCI */
	56	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
	57	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	58	0, 4, BOOKE_PAGESZ_1G, 1),
	59
	60	/* IG* - PCI I/O */
	61	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
	62	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	63	0, 5, BOOKE_PAGESZ_256K, 1),
	64	#endif
	65	#endif
	66
49249e13 PA	67	/* IG - Board CPLD */
	68	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
	69	MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	70	0, 6, BOOKE_PAGESZ_256K, 1),
	71
	72	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
	73	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	74	0, 7, BOOKE_PAGESZ_1M, 1),
49249e13	75
c9e1f588 YZ	76	#if defined(CONFIG_SYS_RAMBOOT) \|\| \
c9e1f588 YZ	77	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
49249e13	78	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
316f0d0f	79	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_M,
c9e1f588 YZ	80	0, 8, BOOKE_PAGESZ_1G, 1),
	81	#endif
	82
	83	#ifdef CONFIG_SYS_INIT_L2_ADDR
	84	/* IG - L2SRAM */
	85	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
	86	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_G,
	87	0, 11, BOOKE_PAGESZ_256K, 1)
49249e13 PA	88	#endif
	89	};
	90
	91	int num_tlb_entries = ARRAY_SIZE(tlb_table);