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7c8eea59 YZ |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
bf902566 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
7c8eea59 YZ |
5 | */ |
6 | ||
7 | #include <common.h> | |
24b852a7 | 8 | #include <console.h> |
7c8eea59 YZ |
9 | #include <ns16550.h> |
10 | #include <malloc.h> | |
11 | #include <mmc.h> | |
12 | #include <nand.h> | |
13 | #include <i2c.h> | |
14 | #include "../common/ngpixis.h" | |
15 | #include <fsl_esdhc.h> | |
382ce7e9 | 16 | #include <spi_flash.h> |
ea022a37 | 17 | #include "../common/spl.h" |
7c8eea59 YZ |
18 | |
19 | DECLARE_GLOBAL_DATA_PTR; | |
20 | ||
21 | static const u32 sysclk_tbl[] = { | |
22 | 66666000, 7499900, 83332500, 8999900, | |
23 | 99999000, 11111000, 12499800, 13333200 | |
24 | }; | |
25 | ||
e3866163 | 26 | phys_size_t get_effective_memsize(void) |
7c8eea59 YZ |
27 | { |
28 | return CONFIG_SYS_L2_SIZE; | |
29 | } | |
30 | ||
31 | void board_init_f(ulong bootflag) | |
32 | { | |
33 | int px_spd; | |
34 | u32 plat_ratio, sys_clk, bus_clk; | |
35 | ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; | |
36 | ||
37 | console_init_f(); | |
38 | ||
39 | /* Set pmuxcr to allow both i2c1 and i2c2 */ | |
40 | setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); | |
41 | setbits_be32(&gur->pmuxcr, | |
42 | in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); | |
43 | ||
382ce7e9 YZ |
44 | #ifdef CONFIG_SPL_SPI_BOOT |
45 | /* Enable the SPI */ | |
46 | clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); | |
47 | #endif | |
48 | ||
7c8eea59 YZ |
49 | /* Read back the register to synchronize the write. */ |
50 | in_be32(&gur->pmuxcr); | |
51 | ||
52 | /* initialize selected port with appropriate baud rate */ | |
53 | px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); | |
54 | sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; | |
55 | plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; | |
56 | bus_clk = sys_clk * plat_ratio / 2; | |
57 | ||
58 | NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, | |
59 | bus_clk / 16 / CONFIG_BAUDRATE); | |
60 | #ifdef CONFIG_SPL_MMC_BOOT | |
61 | puts("\nSD boot...\n"); | |
382ce7e9 YZ |
62 | #elif defined(CONFIG_SPL_SPI_BOOT) |
63 | puts("\nSPI Flash boot...\n"); | |
7c8eea59 YZ |
64 | #endif |
65 | ||
66 | /* copy code to RAM and jump to it - this should not return */ | |
67 | /* NOTE - code has to be copied out of NAND buffer before | |
68 | * other blocks can be read. | |
69 | */ | |
70 | relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); | |
71 | } | |
72 | ||
73 | void board_init_r(gd_t *gd, ulong dest_addr) | |
74 | { | |
75 | /* Pointer is writable since we allocated a register for it */ | |
76 | gd = (gd_t *)CONFIG_SPL_GD_ADDR; | |
77 | bd_t *bd; | |
78 | ||
79 | memset(gd, 0, sizeof(gd_t)); | |
80 | bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); | |
81 | memset(bd, 0, sizeof(bd_t)); | |
82 | gd->bd = bd; | |
83 | bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; | |
84 | bd->bi_memsize = CONFIG_SYS_L2_SIZE; | |
85 | ||
cbcbf71b | 86 | arch_cpu_init(); |
7c8eea59 YZ |
87 | get_clocks(); |
88 | mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, | |
89 | CONFIG_SPL_RELOC_MALLOC_SIZE); | |
ed4708aa | 90 | gd->flags |= GD_FLG_FULL_MALLOC_INIT; |
5d97fe2a | 91 | #ifndef CONFIG_SPL_NAND_BOOT |
7c8eea59 | 92 | env_init(); |
5d97fe2a | 93 | #endif |
7c8eea59 YZ |
94 | #ifdef CONFIG_SPL_MMC_BOOT |
95 | mmc_initialize(bd); | |
96 | #endif | |
97 | /* relocate environment function pointers etc. */ | |
5d97fe2a YZ |
98 | #ifdef CONFIG_SPL_NAND_BOOT |
99 | nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, | |
100 | (uchar *)CONFIG_ENV_ADDR); | |
101 | ||
102 | gd->env_addr = (ulong)(CONFIG_ENV_ADDR); | |
103 | gd->env_valid = 1; | |
104 | #else | |
7c8eea59 | 105 | env_relocate(); |
5d97fe2a | 106 | #endif |
7c8eea59 | 107 | |
81b867aa YZ |
108 | #ifdef CONFIG_SYS_I2C |
109 | i2c_init_all(); | |
110 | #else | |
111 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
112 | #endif | |
7c8eea59 YZ |
113 | |
114 | gd->ram_size = initdram(0); | |
5d97fe2a YZ |
115 | #ifdef CONFIG_SPL_NAND_BOOT |
116 | puts("Tertiary program loader running in sram..."); | |
117 | #else | |
7c8eea59 | 118 | puts("Second program loader running in sram...\n"); |
5d97fe2a | 119 | #endif |
7c8eea59 YZ |
120 | |
121 | #ifdef CONFIG_SPL_MMC_BOOT | |
122 | mmc_boot(); | |
382ce7e9 | 123 | #elif defined(CONFIG_SPL_SPI_BOOT) |
ea022a37 | 124 | fsl_spi_boot(); |
5d97fe2a YZ |
125 | #elif defined(CONFIG_SPL_NAND_BOOT) |
126 | nand_boot(); | |
7c8eea59 YZ |
127 | #endif |
128 | } |