[people/ms/u-boot.git] / board / freescale / p1022ds / tlb.c

/*
 * Copyright 2010 Freescale Semiconductor, Inc.
 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
 *          Timur Tabi <timur@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 0, BOOKE_PAGESZ_4K, 0),

	/* TLB 1 */
	/* *I*** - Covers boot page */
	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
		      0, 0, BOOKE_PAGESZ_4K, 1),

	/* *I*G* - CCSRBAR */
	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 1, BOOKE_PAGESZ_1M, 1),

#ifndef CONFIG_SPL_BUILD
	/* W**G* - Flash/promjet, localbus */
	/* This will be changed to *I*G* after relocation to RAM. */
	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
		      0, 2, BOOKE_PAGESZ_256M, 1),

	/* *I*G* - PCI */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 3, BOOKE_PAGESZ_1G, 1),

	/* *I*G* - PCI */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 4, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 5, BOOKE_PAGESZ_256M, 1),

	/* *I*G* - PCI I/O */
	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 6, BOOKE_PAGESZ_256K, 1),
#endif

	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 7, BOOKE_PAGESZ_4K, 1),

#if defined(CONFIG_SYS_RAMBOOT) || \
	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
	/* **** - eSDHC/eSPI/NAND boot */
	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
		      0, 8, BOOKE_PAGESZ_1G, 1),
	/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
		      0, 9, BOOKE_PAGESZ_1G, 1),
#endif

#ifdef CONFIG_SYS_NAND_BASE
	/* *I*G - NAND */
	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 10, BOOKE_PAGESZ_16K, 1),
#endif

#ifdef CONFIG_SYS_INIT_L2_ADDR
	/* *I*G - L2SRAM */
	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
		      0, 11, BOOKE_PAGESZ_256K, 1)
#endif
};

int num_tlb_entries = ARRAY_SIZE(tlb_table);
Commit	Line	Data
c59e1b4d TT	1	/*
	2	* Copyright 2010 Freescale Semiconductor, Inc.
	3	* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
	4	* Timur Tabi <timur@freescale.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
c59e1b4d TT	7	*/
	8
	9	#include <common.h>
	10	#include <asm/mmu.h>
	11
	12	struct fsl_e_tlb_entry tlb_table[] = {
	13	/* TLB 0 - for temp stack in cache */
	14	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
	15	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	16	0, 0, BOOKE_PAGESZ_4K, 0),
	17	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
	18	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
	19	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	20	0, 0, BOOKE_PAGESZ_4K, 0),
	21	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
	22	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
	23	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	24	0, 0, BOOKE_PAGESZ_4K, 0),
	25	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
	26	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
	27	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	28	0, 0, BOOKE_PAGESZ_4K, 0),
	29
	30	/* TLB 1 */
	31	/* I** - Covers boot page */
	32	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
	33	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I,
	34	0, 0, BOOKE_PAGESZ_4K, 1),
	35
	36	/* IG* - CCSRBAR */
	37	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
	38	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	39	0, 1, BOOKE_PAGESZ_1M, 1),
	40
f45210d6	41	#ifndef CONFIG_SPL_BUILD
c59e1b4d TT	42	/* W*G - Flash/promjet, localbus */
	43	/* This will be changed to IG* after relocation to RAM. */
	44	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
	45	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
	46	0, 2, BOOKE_PAGESZ_256M, 1),
	47
	48	/* IG* - PCI */
	49	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
	50	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	51	0, 3, BOOKE_PAGESZ_1G, 1),
	52
	53	/* IG* - PCI */
	54	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
	55	CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
	56	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	57	0, 4, BOOKE_PAGESZ_256M, 1),
	58
	59	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
	60	CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
	61	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	62	0, 5, BOOKE_PAGESZ_256M, 1),
	63
	64	/* IG* - PCI I/O */
	65	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
	66	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	67	0, 6, BOOKE_PAGESZ_256K, 1),
f45210d6	68	#endif
c59e1b4d TT	69
	70	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
	71	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	72	0, 7, BOOKE_PAGESZ_4K, 1),
af253608	73
7c8eea59 YZ	74	#if defined(CONFIG_SYS_RAMBOOT) \|\| \
7c8eea59 YZ	75	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
f45210d6	76	/* **** - eSDHC/eSPI/NAND boot */
af253608	77	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
316f0d0f	78	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_M,
7c8eea59	79	0, 8, BOOKE_PAGESZ_1G, 1),
f45210d6	80	/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
af253608	81	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
7c8eea59	82	CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
316f0d0f	83	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_M,
7c8eea59	84	0, 9, BOOKE_PAGESZ_1G, 1),
af253608	85	#endif
f45210d6 MM	86
	87	#ifdef CONFIG_SYS_NAND_BASE
	88	/* IG - NAND */
	89	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
7c8eea59 YZ	90	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
7c8eea59 YZ	91	0, 10, BOOKE_PAGESZ_16K, 1),
f45210d6 MM	92	#endif
f45210d6 MM	93
7c8eea59 YZ	94	#ifdef CONFIG_SYS_INIT_L2_ADDR
	95	/* IG - L2SRAM */
	96	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
	97	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_G,
	98	0, 11, BOOKE_PAGESZ_256K, 1)
	99	#endif
c59e1b4d TT	100	};
	101
	102	int num_tlb_entries = ARRAY_SIZE(tlb_table);