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Commit | Line | Data |
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3f7f6b85 RZ |
1 | /* |
2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
3f7f6b85 RZ |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/mmu.h> | |
9 | ||
10 | struct fsl_e_tlb_entry tlb_table[] = { | |
11 | /* TLB 0 - for temp stack in cache */ | |
12 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, | |
13 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
14 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
15 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
16 | CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, | |
17 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
18 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
19 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
20 | CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, | |
21 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
22 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
23 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
24 | CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, | |
25 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
26 | 0, 0, BOOKE_PAGESZ_4K, 0), | |
27 | ||
28 | /* TLB 1 */ | |
29 | /* *I*** - Covers boot page */ | |
30 | SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, | |
31 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, | |
32 | 0, 0, BOOKE_PAGESZ_4K, 1), | |
33 | ||
34 | /* *I*G* - CCSRBAR */ | |
35 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, | |
36 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
37 | 0, 1, BOOKE_PAGESZ_4M, 1), | |
38 | ||
39 | #ifndef CONFIG_NAND_SPL | |
40 | /* *W*G* - BCSR and NOR flash on local bus*/ | |
41 | /* This will be changed to *I*G* after relocation to RAM. */ | |
42 | SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, | |
43 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, | |
44 | 0, 2, BOOKE_PAGESZ_256M, 1), | |
45 | ||
46 | /* *I*G* - PCI */ | |
47 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, | |
48 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
49 | 0, 3, BOOKE_PAGESZ_1G, 1), | |
50 | ||
51 | /* *I*G* - PCI */ | |
52 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, | |
53 | CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, | |
54 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
55 | 0, 4, BOOKE_PAGESZ_256M, 1), | |
56 | ||
57 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, | |
58 | CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, | |
59 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
60 | 0, 5, BOOKE_PAGESZ_256M, 1), | |
61 | ||
62 | /* *I*G* - PCI I/O */ | |
63 | SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, | |
64 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
65 | 0, 6, BOOKE_PAGESZ_256K, 1), | |
66 | ||
67 | /* Bman/Qman */ | |
68 | SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, | |
69 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
70 | 0, 7, BOOKE_PAGESZ_1M, 1), | |
71 | SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, | |
72 | CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, | |
73 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
74 | 0, 8, BOOKE_PAGESZ_1M, 1), | |
75 | SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, | |
76 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, | |
77 | 0, 9, BOOKE_PAGESZ_1M, 1), | |
78 | SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, | |
79 | CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, | |
80 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
81 | 0, 10, BOOKE_PAGESZ_1M, 1), | |
82 | #endif | |
83 | ||
84 | /* *I*G - NAND */ | |
85 | SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, | |
86 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
87 | 0, 11, BOOKE_PAGESZ_1M, 1), | |
88 | ||
89 | #ifdef CONFIG_SYS_RAMBOOT | |
90 | SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, | |
91 | CONFIG_SYS_DDR_SDRAM_BASE, | |
92 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
93 | 0, 12, BOOKE_PAGESZ_1G, 1), | |
94 | ||
95 | SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, | |
96 | CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, | |
97 | MAS3_SX|MAS3_SW|MAS3_SR, 0, | |
98 | 0, 13, BOOKE_PAGESZ_1G, 1), | |
99 | #endif | |
100 | }; | |
101 | ||
102 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |