[people/ms/u-boot.git] / board / freescale / p1_p2_rdb / p1_p2_rdb.c

/*
 * Copyright 2009-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <vsc7385.h>
#include <netdev.h>
#include <rtc.h>
#include <i2c.h>
#include <hwconfig.h>

DECLARE_GLOBAL_DATA_PTR;

#define VSC7385_RST_SET		0x00080000
#define SLIC_RST_SET		0x00040000
#define SGMII_PHY_RST_SET	0x00020000
#define PCIE_RST_SET		0x00010000
#define RGMII_PHY_RST_SET	0x02000000

#define USB_RST_CLR		0x04000000
#define USB2_PORT_OUT_EN        0x01000000

#define GPIO_DIR		0x060f0000

#define BOARD_PERI_RST_SET	VSC7385_RST_SET | SLIC_RST_SET | \
				SGMII_PHY_RST_SET | PCIE_RST_SET | \
				RGMII_PHY_RST_SET

#define SYSCLK_MASK	0x00200000
#define BOARDREV_MASK	0x10100000
#define BOARDREV_C	0x00100000
#define BOARDREV_D	0x00000000

#define SYSCLK_66	66666666
#define SYSCLK_100	100000000

unsigned long get_board_sys_clk(ulong dummy)
{
	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	u32 val_gpdat, sysclk_gpio;

	val_gpdat = in_be32(&pgpio->gpdat);
	sysclk_gpio = val_gpdat & SYSCLK_MASK;

	if(sysclk_gpio == 0)
		return SYSCLK_66;
	else
		return SYSCLK_100;

	return 0;
}

#ifdef CONFIG_MMC
int board_early_init_f (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	setbits_be32(&gur->pmuxcr,
			(MPC85xx_PMUXCR_SDHC_CD |
			 MPC85xx_PMUXCR_SDHC_WP));
	return 0;
}
#endif

int checkboard (void)
{
	u32 val_gpdat, board_rev_gpio;
	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	char board_rev = 0;
	struct cpu_type *cpu;

	val_gpdat = in_be32(&pgpio->gpdat);
	board_rev_gpio = val_gpdat & BOARDREV_MASK;
	if (board_rev_gpio == BOARDREV_C)
		board_rev = 'C';
	else if (board_rev_gpio == BOARDREV_D)
		board_rev = 'D';
	else
		panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);

	cpu = gd->arch.cpu;
	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);

	setbits_be32(&pgpio->gpdir, GPIO_DIR);

/*
 * Bringing the following peripherals out of reset via GPIOs
 * 0 = reset and 1 = out of reset
 * GPIO12 - Reset to Ethernet Switch
 * GPIO13 - Reset to SLIC/SLAC devices
 * GPIO14 - Reset to SGMII_PHY_N
 * GPIO15 - Reset to PCIe slots
 * GPIO6  - Reset to RGMII PHY
 * GPIO5  - Reset to USB3300 devices 1 = reset and 0 = out of reset
 */
	clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);

	return 0;
}

int misc_init_r(void)
{
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
	ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR;

	setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
	setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
#endif
	return 0;
}

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	unsigned int orig_bus = i2c_get_bus_num();
	u8 i2c_data;

	i2c_set_bus_num(1);
	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
		1, &i2c_data, sizeof(i2c_data)) == 0) {
		if (i2c_data & 0x2)
			puts("NOR Flash Bank : Secondary\n");
		else
			puts("NOR Flash Bank : Primary\n");

		if (i2c_data & 0x1) {
			setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
			puts("SD/MMC : 8-bit Mode\n");
			puts("eSPI : Disabled\n");
		} else {
			puts("SD/MMC : 4-bit Mode\n");
			puts("eSPI : Enabled\n");
		}
	} else {
		puts("Failed reading I2C Chip 0x18 on bus 1\n");
	}
	i2c_set_bus_num(orig_bus);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 2;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel, BOOKE_PAGESZ_16M, 1);
	rtc_reset();
	return 0;
}


#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[4];
	int num = 0;
	char *tmp;
	unsigned int vscfw_addr;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (is_serdes_configured(SGMII_TSEC3)) {
		puts("eTSEC3 is in sgmii mode.\n");
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif
	if (!num) {
		printf("No TSECs initialized\n");
		return 0;
	}
#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */
	if ((tmp = getenv ("vscfw_addr")) != NULL) {
		vscfw_addr = simple_strtoul (tmp, NULL, 16);
		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
		if (vsc7385_upload_firmware((void *) vscfw_addr,
					CONFIG_VSC7385_IMAGE_SIZE))
			puts("Failure uploading VSC7385 microcode.\n");
	} else
		puts("No address specified for VSC7385 microcode.\n");
#endif

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;
	fsl_pq_mdio_init(bis, &mdio_info);

	tsec_eth_init(bis, tsec_info, num);

	return pci_eth_init(bis);
}
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_pci_board_setup(void *blob);

int ft_board_setup(void *blob, bd_t *bd)
{
	const char *soc_usb_compat = "fsl-usb2-dr";
	int err, usb1_off, usb2_off;
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

#if defined(CONFIG_PCI)
	ft_pci_board_setup(blob);
#endif /* #if defined(CONFIG_PCI) */

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#if defined(CONFIG_HAS_FSL_DR_USB)
	fdt_fixup_dr_usb(blob, bd);
#endif

#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
	/* Delete eLBC node as it is muxed with USB2 controller */
	if (hwconfig("usb2")) {
		const char *soc_elbc_compat = "fsl,p1020-elbc";
		int off = fdt_node_offset_by_compatible(blob, -1,
			soc_elbc_compat);
		if (off < 0) {
			printf("WARNING: could not find compatible node %s\n",
			       soc_elbc_compat);
			return off;
		}
		err = fdt_del_node(blob, off);
		if (err < 0) {
			printf("WARNING: could not remove %s\n",
			       soc_elbc_compat);
			return err;
		}
		return 0;
	}
#endif
	/* Delete USB2 node as it is muxed with eLBC */
	usb1_off = fdt_node_offset_by_compatible(blob, -1,
		soc_usb_compat);
	if (usb1_off < 0) {
		printf("WARNING: could not find compatible node %s\n",
		       soc_usb_compat);
		return usb1_off;
	}
	usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
			soc_usb_compat);
	if (usb2_off < 0) {
		printf("WARNING: could not find compatible node %s\n",
		       soc_usb_compat);
		return usb2_off;
	}
	err = fdt_del_node(blob, usb2_off);
	if (err < 0) {
		printf("WARNING: could not remove %s\n", soc_usb_compat);
		return err;
	}

	return 0;
}

#endif
Commit	Line	Data
728ece34	1	/*
b7070904	2	* Copyright 2009-2011 Freescale Semiconductor, Inc.
728ece34	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
728ece34 PA	5	*/
	6
	7	#include <common.h>
	8	#include <command.h>
	9	#include <asm/processor.h>
	10	#include <asm/mmu.h>
	11	#include <asm/cache.h>
	12	#include <asm/immap_85xx.h>
058d7dc7	13	#include <asm/fsl_serdes.h>
728ece34 PA	14	#include <asm/io.h>
	15	#include <miiphy.h>
	16	#include <libfdt.h>
	17	#include <fdt_support.h>
063c1263	18	#include <fsl_mdio.h>
728ece34 PA	19	#include <tsec.h>
	20	#include <vsc7385.h>
	21	#include <netdev.h>
39c2a6eb	22	#include <rtc.h>
cac29f25	23	#include <i2c.h>
86dda504	24	#include <hwconfig.h>
728ece34 PA	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
	28	#define VSC7385_RST_SET 0x00080000
	29	#define SLIC_RST_SET 0x00040000
	30	#define SGMII_PHY_RST_SET 0x00020000
	31	#define PCIE_RST_SET 0x00010000
	32	#define RGMII_PHY_RST_SET 0x02000000
	33
	34	#define USB_RST_CLR 0x04000000
2bad42a0	35	#define USB2_PORT_OUT_EN 0x01000000
728ece34 PA	36
	37	#define GPIO_DIR 0x060f0000
	38
	39	#define BOARD_PERI_RST_SET VSC7385_RST_SET \| SLIC_RST_SET \| \
	40	SGMII_PHY_RST_SET \| PCIE_RST_SET \| \
	41	RGMII_PHY_RST_SET
	42
	43	#define SYSCLK_MASK 0x00200000
	44	#define BOARDREV_MASK 0x10100000
728ece34	45	#define BOARDREV_C 0x00100000
75997dc5	46	#define BOARDREV_D 0x00000000
728ece34 PA	47
728ece34 PA	48	#define SYSCLK_66 66666666
728ece34 PA	49	#define SYSCLK_100 100000000
	50
	51	unsigned long get_board_sys_clk(ulong dummy)
	52	{
	53	volatile ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
3313b20b	54	u32 val_gpdat, sysclk_gpio;
728ece34	55
75997dc5	56	val_gpdat = in_be32(&pgpio->gpdat);
728ece34	57	sysclk_gpio = val_gpdat & SYSCLK_MASK;
3313b20b PA	58
	59	if(sysclk_gpio == 0)
	60	return SYSCLK_66;
	61	else
	62	return SYSCLK_100;
	63
728ece34 PA	64	return 0;
	65	}
	66
	67	#ifdef CONFIG_MMC
	68	int board_early_init_f (void)
	69	{
	70	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	71
	72	setbits_be32(&gur->pmuxcr,
	73	(MPC85xx_PMUXCR_SDHC_CD \|
	74	MPC85xx_PMUXCR_SDHC_WP));
	75	return 0;
	76	}
	77	#endif
	78
	79	int checkboard (void)
	80	{
	81	u32 val_gpdat, board_rev_gpio;
	82	volatile ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	83	char board_rev = 0;
	84	struct cpu_type *cpu;
	85
75997dc5	86	val_gpdat = in_be32(&pgpio->gpdat);
728ece34 PA	87	board_rev_gpio = val_gpdat & BOARDREV_MASK;
	88	if (board_rev_gpio == BOARDREV_C)
	89	board_rev = 'C';
75997dc5 PA	90	else if (board_rev_gpio == BOARDREV_D)
75997dc5 PA	91	board_rev = 'D';
728ece34 PA	92	else
	93	panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
	94
67ac13b1	95	cpu = gd->arch.cpu;
728ece34	96	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
5d065c3e	97
728ece34 PA	98	setbits_be32(&pgpio->gpdir, GPIO_DIR);
	99
	100	/*
	101	* Bringing the following peripherals out of reset via GPIOs
	102	* 0 = reset and 1 = out of reset
	103	* GPIO12 - Reset to Ethernet Switch
	104	* GPIO13 - Reset to SLIC/SLAC devices
	105	* GPIO14 - Reset to SGMII_PHY_N
	106	* GPIO15 - Reset to PCIe slots
	107	* GPIO6 - Reset to RGMII PHY
	108	* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
	109	*/
	110	clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
	111
	112	return 0;
	113	}
	114
2bad42a0 RM	115	int misc_init_r(void)
	116	{
	117	#if defined(CONFIG_SDCARD) \|\| defined(CONFIG_SPIFLASH)
	118	ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	119	ccsr_gpio_t gpio = (void )CONFIG_SYS_MPC85xx_GPIO_ADDR;
	120
	121	setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
	122	setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
	123	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
	124	#endif
	125	return 0;
	126	}
	127
728ece34 PA	128	int board_early_init_r(void)
	129	{
	130	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9d045682	131	int flash_esel = find_tlb_idx((void *)flashbase, 1);
cac29f25 PJ	132	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	133	unsigned int orig_bus = i2c_get_bus_num();
	134	u8 i2c_data;
	135
	136	i2c_set_bus_num(1);
	137	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
	138	1, &i2c_data, sizeof(i2c_data)) == 0) {
	139	if (i2c_data & 0x2)
	140	puts("NOR Flash Bank : Secondary\n");
	141	else
	142	puts("NOR Flash Bank : Primary\n");
	143
	144	if (i2c_data & 0x1) {
	145	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
	146	puts("SD/MMC : 8-bit Mode\n");
	147	puts("eSPI : Disabled\n");
	148	} else {
	149	puts("SD/MMC : 4-bit Mode\n");
	150	puts("eSPI : Enabled\n");
	151	}
	152	} else {
	153	puts("Failed reading I2C Chip 0x18 on bus 1\n");
	154	}
	155	i2c_set_bus_num(orig_bus);
728ece34 PA	156
	157	/*
	158	* Remap Boot flash region to caching-inhibited
	159	* so that flash can be erased properly.
	160	*/
	161
	162	/* Flush d-cache and invalidate i-cache of any FLASH data */
	163	flush_dcache();
	164	invalidate_icache();
	165
9d045682 YS	166	if (flash_esel == -1) {
	167	/* very unlikely unless something is messed up */
	168	puts("Error: Could not find TLB for FLASH BASE\n");
	169	flash_esel = 2; /* give our best effort to continue */
	170	} else {
	171	/* invalidate existing TLB entry for flash */
	172	disable_tlb(flash_esel);
	173	}
728ece34 PA	174
	175	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	176	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	177	0, flash_esel, BOOKE_PAGESZ_16M, 1);
39c2a6eb	178	rtc_reset();
728ece34 PA	179	return 0;
	180	}
	181
	182
	183	#ifdef CONFIG_TSEC_ENET
	184	int board_eth_init(bd_t *bis)
	185	{
063c1263	186	struct fsl_pq_mdio_info mdio_info;
728ece34	187	struct tsec_info_struct tsec_info[4];
728ece34 PA	188	int num = 0;
	189	char *tmp;
	190	unsigned int vscfw_addr;
	191
	192	#ifdef CONFIG_TSEC1
	193	SET_STD_TSEC_INFO(tsec_info[num], 1);
	194	num++;
	195	#endif
	196	#ifdef CONFIG_TSEC2
	197	SET_STD_TSEC_INFO(tsec_info[num], 2);
	198	num++;
	199	#endif
	200	#ifdef CONFIG_TSEC3
	201	SET_STD_TSEC_INFO(tsec_info[num], 3);
058d7dc7 KG	202	if (is_serdes_configured(SGMII_TSEC3)) {
058d7dc7 KG	203	puts("eTSEC3 is in sgmii mode.\n");
728ece34	204	tsec_info[num].flags \|= TSEC_SGMII;
058d7dc7	205	}
728ece34 PA	206	num++;
	207	#endif
	208	if (!num) {
	209	printf("No TSECs initialized\n");
	210	return 0;
	211	}
	212	#ifdef CONFIG_VSC7385_ENET
	213	/* If a VSC7385 microcode image is present, then upload it. */
	214	if ((tmp = getenv ("vscfw_addr")) != NULL) {
	215	vscfw_addr = simple_strtoul (tmp, NULL, 16);
	216	printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
	217	if (vsc7385_upload_firmware((void *) vscfw_addr,
	218	CONFIG_VSC7385_IMAGE_SIZE))
	219	puts("Failure uploading VSC7385 microcode.\n");
	220	} else
	221	puts("No address specified for VSC7385 microcode.\n");
	222	#endif
	223
063c1263 AF	224	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	225	mdio_info.name = DEFAULT_MII_NAME;
	226	fsl_pq_mdio_init(bis, &mdio_info);
	227
728ece34 PA	228	tsec_eth_init(bis, tsec_info, num);
	229
	230	return pci_eth_init(bis);
	231	}
	232	#endif
	233
	234	#if defined(CONFIG_OF_BOARD_SETUP)
1749c3da KG	235	extern void ft_pci_board_setup(void *blob);
1749c3da KG	236
e895a4b0	237	int ft_board_setup(void blob, bd_t bd)
728ece34	238	{
86dda504 RM	239	const char *soc_usb_compat = "fsl-usb2-dr";
86dda504 RM	240	int err, usb1_off, usb2_off;
728ece34 PA	241	phys_addr_t base;
	242	phys_size_t size;
	243
	244	ft_cpu_setup(blob, bd);
	245
	246	base = getenv_bootm_low();
	247	size = getenv_bootm_size();
	248
b7070904	249	#if defined(CONFIG_PCI)
1749c3da	250	ft_pci_board_setup(blob);
b7070904	251	#endif /* #if defined(CONFIG_PCI) */
1749c3da	252
728ece34	253	fdt_fixup_memory(blob, (u64)base, (u64)size);
86dda504	254
a311db69	255	#if defined(CONFIG_HAS_FSL_DR_USB)
86dda504	256	fdt_fixup_dr_usb(blob, bd);
a311db69	257	#endif
86dda504 RM	258
	259	#if defined(CONFIG_SDCARD) \|\| defined(CONFIG_SPIFLASH)
	260	/* Delete eLBC node as it is muxed with USB2 controller */
	261	if (hwconfig("usb2")) {
	262	const char *soc_elbc_compat = "fsl,p1020-elbc";
	263	int off = fdt_node_offset_by_compatible(blob, -1,
	264	soc_elbc_compat);
	265	if (off < 0) {
e895a4b0 SG	266	printf("WARNING: could not find compatible node %s\n",
	267	soc_elbc_compat);
	268	return off;
86dda504 RM	269	}
	270	err = fdt_del_node(blob, off);
	271	if (err < 0) {
e895a4b0 SG	272	printf("WARNING: could not remove %s\n",
	273	soc_elbc_compat);
	274	return err;
86dda504	275	}
e895a4b0	276	return 0;
86dda504 RM	277	}
	278	#endif
	279	/* Delete USB2 node as it is muxed with eLBC */
	280	usb1_off = fdt_node_offset_by_compatible(blob, -1,
	281	soc_usb_compat);
	282	if (usb1_off < 0) {
e895a4b0 SG	283	printf("WARNING: could not find compatible node %s\n",
	284	soc_usb_compat);
	285	return usb1_off;
86dda504 RM	286	}
	287	usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
	288	soc_usb_compat);
	289	if (usb2_off < 0) {
e895a4b0 SG	290	printf("WARNING: could not find compatible node %s\n",
	291	soc_usb_compat);
	292	return usb2_off;
86dda504 RM	293	}
86dda504 RM	294	err = fdt_del_node(blob, usb2_off);
e895a4b0 SG	295	if (err < 0) {
	296	printf("WARNING: could not remove %s\n", soc_usb_compat);
	297	return err;
	298	}
	299
	300	return 0;
728ece34	301	}
e895a4b0	302
728ece34	303	#endif