[people/ms/u-boot.git] / board / freescale / p1_p2_rdb_pc / p1_p2_rdb_pc.c

/*
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <hwconfig.h>
#include <pci.h>
#include <i2c.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <asm/mp.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <vsc7385.h>
#include <ioports.h>
#include <asm/fsl_serdes.h>
#include <netdev.h>

#ifdef CONFIG_QE

#define GPIO_GETH_SW_PORT	1
#define GPIO_GETH_SW_PIN	29
#define GPIO_GETH_SW_DATA	(1 << (31 - GPIO_GETH_SW_PIN))

#define GPIO_SLIC_PORT		1
#define GPIO_SLIC_PIN		30
#define GPIO_SLIC_DATA		(1 << (31 - GPIO_SLIC_PIN))

#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
#define GPIO_DDR_RST_PORT	1
#define GPIO_DDR_RST_PIN	8
#define GPIO_DDR_RST_DATA	(1 << (31 - GPIO_DDR_RST_PIN))

#define GPIO_2BIT_MASK		(0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
#endif

#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
#define PCA_IOPORT_I2C_ADDR		0x23
#define PCA_IOPORT_OUTPUT_CMD		0x2
#define PCA_IOPORT_CFG_CMD		0x6
#define PCA_IOPORT_QE_PIN_ENABLE	0xf8
#define PCA_IOPORT_QE_TDM_ENABLE	0xf6
#endif

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* GPIO */
	{1,   1, 2, 0, 0}, /* GPIO7/PB1   - LOAD_DEFAULT_N */
#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
	{1,   8, 1, 1, 0}, /* GPIO10/PB8  - DDR_RST */
#endif
	{0,  15, 1, 0, 0}, /* GPIO11/A15  - WDI */
	{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0},	/* RST_GETH_SW_N */
	{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0},	/* RST_SLIC_N */

#ifdef CONFIG_P1025RDB
	/* QE_MUX_MDC */
	{1,  19, 1, 0, 1}, /* QE_MUX_MDC               */

	/* QE_MUX_MDIO */
	{1,  20, 3, 0, 1}, /* QE_MUX_MDIO              */

	/* UCC_1_MII */
	{0, 23, 2, 0, 2}, /* CLK12 */
	{0, 24, 2, 0, 1}, /* CLK9 */
	{0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0      */
	{0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1      */
	{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2      */
	{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
	{0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0      */
	{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1      */
	{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
	{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
	{0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
	{0, 13, 1, 0, 2}, /* ENET1_TX_ER               */
	{0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B    */
	{0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B    */
	{0, 17, 2, 0, 2}, /* ENET1_CRS    */
	{0, 16, 2, 0, 2}, /* ENET1_COL    */

	/* UCC_5_RMII */
	{1, 11, 2, 0, 1}, /* CLK13 */
	{1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0      */
	{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1      */
	{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0      */
	{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1      */
	{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B    */
	{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B    */
	{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B    */
#endif

	{0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
};
#endif

struct cpld_data {
	u8 cpld_rev_major;
	u8 pcba_rev;
	u8 wd_cfg;
	u8 rst_bps_sw;
	u8 load_default_n;
	u8 rst_bps_wd;
	u8 bypass_enable;
	u8 bps_led;
	u8 status_led;                  /* offset: 0x8 */
	u8 fxo_led;                     /* offset: 0x9 */
	u8 fxs_led;                     /* offset: 0xa */
	u8 rev4[2];
	u8 system_rst;                  /* offset: 0xd */
	u8 bps_out;
	u8 rev5[3];
	u8 cpld_rev_minor;
};

#define CPLD_WD_CFG	0x03
#define CPLD_RST_BSW	0x00
#define CPLD_RST_BWD	0x00
#define CPLD_BYPASS_EN	0x03
#define CPLD_STATUS_LED	0x01
#define CPLD_FXO_LED	0x01
#define CPLD_FXS_LED	0x0F
#define CPLD_SYS_RST	0x00

void board_cpld_init(void)
{
	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);

	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
	out_8(&cpld_data->status_led, CPLD_STATUS_LED);
	out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
	out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
	out_8(&cpld_data->system_rst, CPLD_SYS_RST);
}

void board_gpio_init(void)
{
#ifdef CONFIG_QE
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);

#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
	/* reset DDR3 */
	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
	udelay(1000);
	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
	udelay(1000);
	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
	/* disable CE_PB8 */
	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
#endif
	/* Enable VSC7385 switch */
	setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);

	/* Enable SLIC */
	setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
#else

	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);

	/*
	 * GPIO10 DDR Reset, open drain
	 * GPIO7  LOAD_DEFAULT_N          Input
	 * GPIO11  WDI (watchdog input)
	 * GPIO12  Ethernet Switch Reset
	 * GPIO13  SLIC Reset
	 */

	setbits_be32(&pgpio->gpdir, 0x02130000);
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
	/* init DDR3 reset signal */
	setbits_be32(&pgpio->gpdir, 0x00200000);
	setbits_be32(&pgpio->gpodr, 0x00200000);
	clrbits_be32(&pgpio->gpdat, 0x00200000);
	udelay(1000);
	setbits_be32(&pgpio->gpdat, 0x00200000);
	udelay(1000);
	clrbits_be32(&pgpio->gpdir, 0x00200000);
#endif

#ifdef CONFIG_VSC7385_ENET
	/* reset VSC7385 Switch */
	setbits_be32(&pgpio->gpdir, 0x00080000);
	setbits_be32(&pgpio->gpdat, 0x00080000);
#endif

#ifdef CONFIG_SLIC
	/* reset SLIC */
	setbits_be32(&pgpio->gpdir, 0x00040000);
	setbits_be32(&pgpio->gpdat, 0x00040000);
#endif
#endif
}

int board_early_init_f(void)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	setbits_be32(&gur->pmuxcr,
			(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
	clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);

	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);

	board_gpio_init();
	board_cpld_init();

	return 0;
}

int checkboard(void)
{
	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u8 in, out, io_config, val;

	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
		in_8(&cpld_data->cpld_rev_major) & 0x0F,
		in_8(&cpld_data->cpld_rev_minor) & 0x0F,
		in_8(&cpld_data->pcba_rev) & 0x0F);

	/* Initialize i2c early for rom_loc and flash bank information */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
	    i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
		printf("Error reading i2c boot information!\n");
		return 0; /* Don't want to hang() on this error */
	}

	val = (in & io_config) | (out & (~io_config));

	puts("rom_loc: ");
	if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
		puts("sd");
#ifdef __SW_BOOT_SPI
	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
		puts("spi");
#endif
#ifdef __SW_BOOT_NAND
	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
		puts("nand");
#endif
#ifdef __SW_BOOT_PCIE
	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
		puts("pcie");
#endif
	} else {
		if (val & 0x2)
			puts("nor lower bank");
		else
			puts("nor upper bank");
	}
	puts("\n");

	if (val & 0x1) {
		setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
		puts("SD/MMC : 8-bit Mode\n");
		puts("eSPI : Disabled\n");
	} else {
		puts("SD/MMC : 4-bit Mode\n");
		puts("eSPI : Enabled\n");
	}

	return 0;
}

#ifdef CONFIG_PCI
void pci_init_board(void)
{
	fsl_pcie_init_board(0);
}
#endif

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
		0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
	return 0;
}

int board_eth_init(bd_t *bis)
{
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[4];
	ccsr_gur_t *gur __attribute__((unused)) =
		(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int num = 0;
#ifdef CONFIG_VSC7385_ENET
	char *tmp;
	unsigned int vscfw_addr;
#endif

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	if (is_serdes_configured(SGMII_TSEC2)) {
		printf("eTSEC2 is in sgmii mode.\n");
		tsec_info[num].flags |= TSEC_SGMII;
	}
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");
		return 0;
	}

#ifdef CONFIG_VSC7385_ENET
	/* If a VSC7385 microcode image is present, then upload it. */
	if ((tmp = getenv("vscfw_addr")) != NULL) {
		vscfw_addr = simple_strtoul(tmp, NULL, 16);
		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
		if (vsc7385_upload_firmware((void *) vscfw_addr,
					CONFIG_VSC7385_IMAGE_SIZE))
			puts("Failure uploading VSC7385 microcode.\n");
	} else
		puts("No address specified for VSC7385 microcode.\n");
#endif

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;

	fsl_pq_mdio_init(bis, &mdio_info);

	tsec_eth_init(bis, tsec_info, num);

#if defined(CONFIG_UEC_ETH)
	/*  QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);

	uec_standard_init(bis);
#endif

	return pci_eth_init(bis);
}

#if defined(CONFIG_QE) && \
	(defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB))
static void fdt_board_fixup_qe_pins(void *blob)
{
	unsigned int oldbus;
	u8 val8;
	int node;
	fsl_lbc_t *lbc = LBC_BASE_ADDR;

	if (hwconfig("qe")) {
		/* For QE and eLBC pins multiplexing,
		 * there is a PCA9555 device on P1025RDB.
		 * It control the multiplex pins' functions,
		 * and setting the PCA9555 can switch the
		 * function between QE and eLBC.
		 */
		oldbus = i2c_get_bus_num();
		i2c_set_bus_num(0);
		if (hwconfig("tdm"))
			val8 = PCA_IOPORT_QE_TDM_ENABLE;
		else
			val8 = PCA_IOPORT_QE_PIN_ENABLE;
		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
				1, &val8, 1);
		i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
				1, &val8, 1);
		i2c_set_bus_num(oldbus);
		/* if run QE TDM, Set ABSWP to implement
		 * conversion of addresses in the eLBC.
		 */
		if (hwconfig("tdm")) {
			set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
			set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
			setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
		}
	} else {
		node = fdt_path_offset(blob, "/qe");
		if (node >= 0)
			fdt_del_node(blob, node);
	}

	return;
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;
	const char *soc_usb_compat = "fsl-usb2-dr";
	int err, usb1_off, usb2_off;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

	FT_FSL_PCI_SETUP;

#ifdef CONFIG_QE
	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
			sizeof("okay"), 0);
#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
	fdt_board_fixup_qe_pins(blob);
#endif
#endif

#if defined(CONFIG_HAS_FSL_DR_USB)
	fdt_fixup_dr_usb(blob, bd);
#endif

#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
	/* Delete eLBC node as it is muxed with USB2 controller */
	if (hwconfig("usb2")) {
		const char *soc_elbc_compat = "fsl,p1020-elbc";
		int off = fdt_node_offset_by_compatible(blob, -1,
				soc_elbc_compat);
		if (off < 0) {
			printf("WARNING: could not find compatible node %s: %s.\n",
			       soc_elbc_compat,
			       fdt_strerror(off));
				return;
		}
		err = fdt_del_node(blob, off);
		if (err < 0) {
			printf("WARNING: could not remove %s: %s.\n",
			       soc_elbc_compat, fdt_strerror(err));
		}
		return;
	}
#endif

/* Delete USB2 node as it is muxed with eLBC */
	usb1_off = fdt_node_offset_by_compatible(blob, -1,
		soc_usb_compat);
	if (usb1_off < 0) {
		printf("WARNING: could not find compatible node %s: %s.\n",
		       soc_usb_compat,
		       fdt_strerror(usb1_off));
		return;
	}
	usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
			soc_usb_compat);
	if (usb2_off < 0) {
		printf("WARNING: could not find compatible node %s: %s.\n",
		       soc_usb_compat,
		       fdt_strerror(usb2_off));
		return;
	}
	err = fdt_del_node(blob, usb2_off);
	if (err < 0) {
		printf("WARNING: could not remove %s: %s.\n",
		       soc_usb_compat, fdt_strerror(err));
	}

}
#endif
Commit	Line	Data
14aa71e6 LY	1	/*
	2	* Copyright 2010-2011 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
	25	#include <hwconfig.h>
	26	#include <pci.h>
	27	#include <i2c.h>
	28	#include <asm/processor.h>
	29	#include <asm/mmu.h>
	30	#include <asm/cache.h>
	31	#include <asm/immap_85xx.h>
	32	#include <asm/fsl_pci.h>
	33	#include <asm/fsl_ddr_sdram.h>
	34	#include <asm/io.h>
	35	#include <asm/fsl_law.h>
	36	#include <asm/fsl_lbc.h>
	37	#include <asm/mp.h>
	38	#include <miiphy.h>
	39	#include <libfdt.h>
	40	#include <fdt_support.h>
	41	#include <fsl_mdio.h>
	42	#include <tsec.h>
	43	#include <vsc7385.h>
	44	#include <ioports.h>
	45	#include <asm/fsl_serdes.h>
	46	#include <netdev.h>
	47
	48	#ifdef CONFIG_QE
	49
	50	#define GPIO_GETH_SW_PORT 1
	51	#define GPIO_GETH_SW_PIN 29
	52	#define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
	53
	54	#define GPIO_SLIC_PORT 1
	55	#define GPIO_SLIC_PIN 30
	56	#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
	57
545c12cf XJ	58	#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
	59	#define GPIO_DDR_RST_PORT 1
	60	#define GPIO_DDR_RST_PIN 8
	61	#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
	62
	63	#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
	64	#endif
14aa71e6 LY	65
	66	#if defined(CONFIG_P1025RDB) \|\| defined(CONFIG_P1021RDB)
	67	#define PCA_IOPORT_I2C_ADDR 0x23
	68	#define PCA_IOPORT_OUTPUT_CMD 0x2
	69	#define PCA_IOPORT_CFG_CMD 0x6
	70	#define PCA_IOPORT_QE_PIN_ENABLE 0xf8
	71	#define PCA_IOPORT_QE_TDM_ENABLE 0xf6
	72	#endif
	73
	74	const qe_iop_conf_t qe_iop_conf_tab[] = {
	75	/* GPIO */
	76	{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
545c12cf	77	#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
14aa71e6 LY	78	{1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
	79	#endif
	80	{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
	81	{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
	82	{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
	83
	84	#ifdef CONFIG_P1025RDB
	85	/* QE_MUX_MDC */
	86	{1, 19, 1, 0, 1}, /* QE_MUX_MDC */
	87
	88	/* QE_MUX_MDIO */
	89	{1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
	90
	91	/* UCC_1_MII */
	92	{0, 23, 2, 0, 2}, /* CLK12 */
	93	{0, 24, 2, 0, 1}, /* CLK9 */
	94	{0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
	95	{0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
	96	{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
	97	{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
	98	{0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
	99	{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
	100	{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
	101	{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
	102	{0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
	103	{0, 13, 1, 0, 2}, /* ENET1_TX_ER */
	104	{0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
	105	{0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
	106	{0, 17, 2, 0, 2}, /* ENET1_CRS */
	107	{0, 16, 2, 0, 2}, /* ENET1_COL */
	108
	109	/* UCC_5_RMII */
	110	{1, 11, 2, 0, 1}, /* CLK13 */
	111	{1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
	112	{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
	113	{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
	114	{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
	115	{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
	116	{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
	117	{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
	118	#endif
	119
	120	{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
	121	};
	122	#endif
	123
	124	struct cpld_data {
	125	u8 cpld_rev_major;
	126	u8 pcba_rev;
	127	u8 wd_cfg;
	128	u8 rst_bps_sw;
	129	u8 load_default_n;
	130	u8 rst_bps_wd;
	131	u8 bypass_enable;
	132	u8 bps_led;
	133	u8 status_led; /* offset: 0x8 */
	134	u8 fxo_led; /* offset: 0x9 */
	135	u8 fxs_led; /* offset: 0xa */
	136	u8 rev4[2];
	137	u8 system_rst; /* offset: 0xd */
	138	u8 bps_out;
	139	u8 rev5[3];
	140	u8 cpld_rev_minor;
	141	};
142
143	#define CPLD_WD_CFG 0x03
144	#define CPLD_RST_BSW 0x00
145	#define CPLD_RST_BWD 0x00
146	#define CPLD_BYPASS_EN 0x03
147	#define CPLD_STATUS_LED 0x01
148	#define CPLD_FXO_LED 0x01
149	#define CPLD_FXS_LED 0x0F
150	#define CPLD_SYS_RST 0x00
151
152	void board_cpld_init(void)
153	{
154	struct cpld_data cpld_data = (void )(CONFIG_SYS_CPLD_BASE);
155
156	out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
157	out_8(&cpld_data->status_led, CPLD_STATUS_LED);
158	out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
159	out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
160	out_8(&cpld_data->system_rst, CPLD_SYS_RST);
161	}
162
163	void board_gpio_init(void)
164	{
165	#ifdef CONFIG_QE
166	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
167	par_io_t par_io = (par_io_t ) &(gur->qe_par_io);
168
545c12cf XJ	169	#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
	170	/* reset DDR3 */
	171	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
	172	udelay(1000);
	173	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
	174	udelay(1000);
	175	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
	176	/* disable CE_PB8 */
	177	clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
	178	#endif
14aa71e6 LY	179	/* Enable VSC7385 switch */
	180	setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
	181
	182	/* Enable SLIC */
	183	setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
	184	#else
	185
	186	ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
	187
	188	/*
	189	* GPIO10 DDR Reset, open drain
	190	* GPIO7 LOAD_DEFAULT_N Input
	191	* GPIO11 WDI (watchdog input)
	192	* GPIO12 Ethernet Switch Reset
	193	* GPIO13 SLIC Reset
	194	*/
	195
	196	setbits_be32(&pgpio->gpdir, 0x02130000);
94a45bb1	197	#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
14aa71e6 LY	198	/* init DDR3 reset signal */
	199	setbits_be32(&pgpio->gpdir, 0x00200000);
	200	setbits_be32(&pgpio->gpodr, 0x00200000);
	201	clrbits_be32(&pgpio->gpdat, 0x00200000);
	202	udelay(1000);
	203	setbits_be32(&pgpio->gpdat, 0x00200000);
	204	udelay(1000);
	205	clrbits_be32(&pgpio->gpdir, 0x00200000);
	206	#endif
	207
	208	#ifdef CONFIG_VSC7385_ENET
	209	/* reset VSC7385 Switch */
	210	setbits_be32(&pgpio->gpdir, 0x00080000);
	211	setbits_be32(&pgpio->gpdat, 0x00080000);
	212	#endif
	213
	214	#ifdef CONFIG_SLIC
	215	/* reset SLIC */
	216	setbits_be32(&pgpio->gpdir, 0x00040000);
	217	setbits_be32(&pgpio->gpdat, 0x00040000);
	218	#endif
	219	#endif
	220	}
	221
	222	int board_early_init_f(void)
	223	{
	224	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	225
	226	setbits_be32(&gur->pmuxcr,
	227	(MPC85xx_PMUXCR_SDHC_CD \| MPC85xx_PMUXCR_SDHC_WP));
	228	clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
	229
	230	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
	231	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
	232
	233	board_gpio_init();
	234	board_cpld_init();
	235
	236	return 0;
	237	}
	238
	239	int checkboard(void)
	240	{
	241	struct cpld_data cpld_data = (void )(CONFIG_SYS_CPLD_BASE);
	242	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	243	u8 in, out, io_config, val;
	244
5d065c3e	245	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
14aa71e6 LY	246	in_8(&cpld_data->cpld_rev_major) & 0x0F,
	247	in_8(&cpld_data->cpld_rev_minor) & 0x0F,
	248	in_8(&cpld_data->pcba_rev) & 0x0F);
	249
	250	/* Initialize i2c early for rom_loc and flash bank information */
	251	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	252
	253	if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 \|\|
	254	i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 \|\|
	255	i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
	256	printf("Error reading i2c boot information!\n");
	257	return 0; /* Don't want to hang() on this error */
	258	}
	259
	260	val = (in & io_config) \| (out & (~io_config));
	261
	262	puts("rom_loc: ");
	263	if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
	264	puts("sd");
	265	#ifdef __SW_BOOT_SPI
	266	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
	267	puts("spi");
	268	#endif
	269	#ifdef __SW_BOOT_NAND
	270	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
	271	puts("nand");
	272	#endif
	273	#ifdef __SW_BOOT_PCIE
	274	} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
	275	puts("pcie");
	276	#endif
	277	} else {
	278	if (val & 0x2)
	279	puts("nor lower bank");
	280	else
	281	puts("nor upper bank");
	282	}
	283	puts("\n");
	284
	285	if (val & 0x1) {
	286	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
	287	puts("SD/MMC : 8-bit Mode\n");
	288	puts("eSPI : Disabled\n");
	289	} else {
	290	puts("SD/MMC : 4-bit Mode\n");
	291	puts("eSPI : Enabled\n");
	292	}
	293
	294	return 0;
	295	}
	296
	297	#ifdef CONFIG_PCI
	298	void pci_init_board(void)
	299	{
	300	fsl_pcie_init_board(0);
	301	}
	302	#endif
	303
	304	int board_early_init_r(void)
	305	{
	306	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	307	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
	308
	309	/*
310	* Remap Boot flash region to caching-inhibited
311	* so that flash can be erased properly.
312	*/
313
314	/* Flush d-cache and invalidate i-cache of any FLASH data */
315	flush_dcache();
316	invalidate_icache();
317
318	/* invalidate existing TLB entry for flash */
319	disable_tlb(flash_esel);
320
321	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
322	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,/* perms, wimge */
323	0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
324	return 0;
325	}
326
327	int board_eth_init(bd_t *bis)
328	{
329	struct fsl_pq_mdio_info mdio_info;
330	struct tsec_info_struct tsec_info[4];
331	ccsr_gur_t *gur __attribute__((unused)) =
332	(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
333	int num = 0;
334	#ifdef CONFIG_VSC7385_ENET
335	char *tmp;
336	unsigned int vscfw_addr;
337	#endif
338
339	#ifdef CONFIG_TSEC1
340	SET_STD_TSEC_INFO(tsec_info[num], 1);
341	num++;
342	#endif
343	#ifdef CONFIG_TSEC2
344	SET_STD_TSEC_INFO(tsec_info[num], 2);
345	if (is_serdes_configured(SGMII_TSEC2)) {
346	printf("eTSEC2 is in sgmii mode.\n");
347	tsec_info[num].flags \|= TSEC_SGMII;
348	}
349	num++;
350	#endif
351	#ifdef CONFIG_TSEC3
352	SET_STD_TSEC_INFO(tsec_info[num], 3);
353	num++;
354	#endif
355
356	if (!num) {
357	printf("No TSECs initialized\n");
358	return 0;
359	}
360
361	#ifdef CONFIG_VSC7385_ENET
362	/* If a VSC7385 microcode image is present, then upload it. */
363	if ((tmp = getenv("vscfw_addr")) != NULL) {
364	vscfw_addr = simple_strtoul(tmp, NULL, 16);
365	printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
366	if (vsc7385_upload_firmware((void *) vscfw_addr,
367	CONFIG_VSC7385_IMAGE_SIZE))
368	puts("Failure uploading VSC7385 microcode.\n");
369	} else
370	puts("No address specified for VSC7385 microcode.\n");
371	#endif
372
373	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
374	mdio_info.name = DEFAULT_MII_NAME;
375
376	fsl_pq_mdio_init(bis, &mdio_info);
377
378	tsec_eth_init(bis, tsec_info, num);
379
380	#if defined(CONFIG_UEC_ETH)
381	/* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
382	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
383	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
384
385	uec_standard_init(bis);
386	#endif
387
388	return pci_eth_init(bis);
389	}
390
391	#if defined(CONFIG_QE) && \
392	(defined(CONFIG_P1025RDB) \|\| defined(CONFIG_P1021RDB))
393	static void fdt_board_fixup_qe_pins(void *blob)
394	{
395	unsigned int oldbus;
396	u8 val8;
397	int node;
398	fsl_lbc_t *lbc = LBC_BASE_ADDR;
399
400	if (hwconfig("qe")) {
401	/* For QE and eLBC pins multiplexing,
402	* there is a PCA9555 device on P1025RDB.
403	* It control the multiplex pins' functions,
404	* and setting the PCA9555 can switch the
405	* function between QE and eLBC.
406	*/
407	oldbus = i2c_get_bus_num();
408	i2c_set_bus_num(0);
409	if (hwconfig("tdm"))
410	val8 = PCA_IOPORT_QE_TDM_ENABLE;
411	else
412	val8 = PCA_IOPORT_QE_PIN_ENABLE;
413	i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
414	1, &val8, 1);
415	i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
416	1, &val8, 1);
417	i2c_set_bus_num(oldbus);
418	/* if run QE TDM, Set ABSWP to implement
419	* conversion of addresses in the eLBC.
420	*/
421	if (hwconfig("tdm")) {
422	set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
423	set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
424	setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
425	}
426	} else {
427	node = fdt_path_offset(blob, "/qe");
428	if (node >= 0)
429	fdt_del_node(blob, node);
430	}
431
432	return;
433	}
434	#endif
435
436	#ifdef CONFIG_OF_BOARD_SETUP
437	void ft_board_setup(void blob, bd_t bd)
438	{
439	phys_addr_t base;
440	phys_size_t size;
7d83b79c ZF	441	const char *soc_usb_compat = "fsl-usb2-dr";
7d83b79c ZF	442	int err, usb1_off, usb2_off;
14aa71e6 LY	443
	444	ft_cpu_setup(blob, bd);
	445
	446	base = getenv_bootm_low();
	447	size = getenv_bootm_size();
	448
	449	fdt_fixup_memory(blob, (u64)base, (u64)size);
	450
	451	FT_FSL_PCI_SETUP;
	452
	453	#ifdef CONFIG_QE
	454	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
	455	sizeof("okay"), 0);
	456	#if defined(CONFIG_P1025RDB) \|\| defined(CONFIG_P1021RDB)
	457	fdt_board_fixup_qe_pins(blob);
	458	#endif
	459	#endif
a311db69 RM	460
a311db69 RM	461	#if defined(CONFIG_HAS_FSL_DR_USB)
14aa71e6	462	fdt_fixup_dr_usb(blob, bd);
a311db69	463	#endif
7d83b79c ZF	464
	465	#if defined(CONFIG_SDCARD) \|\| defined(CONFIG_SPIFLASH)
	466	/* Delete eLBC node as it is muxed with USB2 controller */
	467	if (hwconfig("usb2")) {
	468	const char *soc_elbc_compat = "fsl,p1020-elbc";
	469	int off = fdt_node_offset_by_compatible(blob, -1,
	470	soc_elbc_compat);
	471	if (off < 0) {
	472	printf("WARNING: could not find compatible node %s: %s.\n",
	473	soc_elbc_compat,
	474	fdt_strerror(off));
	475	return;
	476	}
	477	err = fdt_del_node(blob, off);
	478	if (err < 0) {
	479	printf("WARNING: could not remove %s: %s.\n",
	480	soc_elbc_compat, fdt_strerror(err));
	481	}
	482	return;
	483	}
	484	#endif
	485
	486	/* Delete USB2 node as it is muxed with eLBC */
	487	usb1_off = fdt_node_offset_by_compatible(blob, -1,
	488	soc_usb_compat);
	489	if (usb1_off < 0) {
	490	printf("WARNING: could not find compatible node %s: %s.\n",
	491	soc_usb_compat,
	492	fdt_strerror(usb1_off));
	493	return;
	494	}
	495	usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
	496	soc_usb_compat);
	497	if (usb2_off < 0) {
	498	printf("WARNING: could not find compatible node %s: %s.\n",
	499	soc_usb_compat,
	500	fdt_strerror(usb2_off));
	501	return;
	502	}
	503	err = fdt_del_node(blob, usb2_off);
	504	if (err < 0) {
	505	printf("WARNING: could not remove %s: %s.\n",
	506	soc_usb_compat, fdt_strerror(err));
	507	}
	508
14aa71e6 LY	509	}
14aa71e6 LY	510	#endif