[people/ms/u-boot.git] / board / freescale / p2020ds / p2020ds.c

/*
 * Copyright 2007-2009 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>
#include <asm/fsl_law.h>
#include <asm/mp.h>
#include <netdev.h>

#include "../common/pixis.h"
#include "../common/sgmii_riser.h"

DECLARE_GLOBAL_DATA_PTR;

phys_size_t fixed_sdram(void);

int checkboard(void)
{
	u8 sw7;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	puts("Board: P2020DS ");
#ifdef CONFIG_PHYS_64BIT
	puts("(36-bit addrmap) ");
#endif

	printf("Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	sw7 = in_8(pixis_base + PIXIS_SW(7));
	switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
		case 0:
		case 1:
			printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
			break;
		case 2:
		case 3:
			puts ("Promjet\n");
			break;
	}

	return 0;
}

phys_size_t initdram(int board_type)
{
	phys_size_t dram_size = 0;

	puts("Initializing....");

#ifdef CONFIG_SPD_EEPROM
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram();

	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
			 dram_size,
			 LAW_TRGT_IF_DDR) < 0) {
		printf("ERROR setting Local Access Windows for DDR\n");
		return 0;
	};
#endif
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

	puts("    DDR: ");
	return dram_size;
}

#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */

phys_size_t fixed_sdram(void)
{
	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
	uint d_init;

	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
	ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
	ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
	ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
	ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
	ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;

	if (!strcmp("performance", getenv("perf_mode"))) {
		/* Performance Mode Values */

		ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
		ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
		ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;

		asm("sync;isync");

		udelay(500);

		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
	} else {
		/* Stable Mode Values */

		ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
		ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
		ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;

		/* ECC will be assumed in stable mode */
		ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
		ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
		ddr->err_sbe = CONFIG_SYS_DDR_SBE;

		asm("sync;isync");

		udelay(500);

		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
	}

#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
		udelay(1000);
	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}

#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif

#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif

int first_free_busno = 0;

#ifdef CONFIG_PCI
void pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

	volatile ccsr_fsl_pci_t *pci;
	struct pci_controller *hose;
	int pcie_ep, pcie_configured;
	struct pci_region *r;
/*		u32 temp32; */

	debug("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
			devdisr, io_sel, host_agent);

	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
		printf("    eTSEC2 is in sgmii mode.\n");
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		printf("    eTSEC3 is in sgmii mode.\n");

#ifdef CONFIG_PCIE2
	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
	hose = &pcie2_hose;
	pcie_ep = (host_agent == 2) || (host_agent == 4) ||
		  (host_agent == 6) || (host_agent == 0);
	pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
	r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
		printf("\n    PCIE2 connected to ULI as %s (base addr %x)",
				pcie_ep ? "End Point" : "Root Complex",
				(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug(" with errors.  Clearing.  Now 0x%08x",
				pci->pme_msg_det);
		}
		printf("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
				CONFIG_SYS_PCIE2_MEM_BUS,
				CONFIG_SYS_PCIE2_MEM_PHYS,
				CONFIG_SYS_PCIE2_MEM_SIZE,
				PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
				CONFIG_SYS_PCIE2_IO_BUS,
				CONFIG_SYS_PCIE2_IO_PHYS,
				CONFIG_SYS_PCIE2_IO_SIZE,
				PCI_REGION_IO);

		hose->region_count = r - hose->regions;
		hose->first_busno = first_free_busno;
		pci_setup_indirect(hose, (int)&pci->cfg_addr,
				  (int)&pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno = hose->last_busno+1;
		printf("    PCIE2 on bus %02x - %02x\n",
			hose->first_busno, hose->last_busno);

		/*
		 * The workaround doesn't work on p2020 because the location
		 * we try and read isn't valid on p2020, fix this later
		 */
#if 0
		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 * Device 1d has the first on-board memory BAR.
		 */

		pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
				PCI_BASE_ADDRESS_1, &temp32);
		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
			void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
							temp32, 4, 0);
			debug(" uli1575 read to %p\n", p);
			in_be32(p);
		}
#endif
	} else {
		printf("    PCIE2: disabled\n");
	}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
#endif

#ifdef CONFIG_PCIE3
	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
	hose = &pcie3_hose;
	pcie_ep = (host_agent == 0) || (host_agent == 3) ||
		(host_agent == 5) || (host_agent == 6);
	pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
	r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
		printf("\n    PCIE3 connected to Slot 1 as %s (base addr %x)",
				pcie_ep ? "End Point" : "Root Complex",
				(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug(" with errors.  Clearing.  Now 0x%08x",
				pci->pme_msg_det);
		}
		printf("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
				CONFIG_SYS_PCIE3_MEM_BUS,
				CONFIG_SYS_PCIE3_MEM_PHYS,
				CONFIG_SYS_PCIE3_MEM_SIZE,
				PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
				CONFIG_SYS_PCIE3_IO_BUS,
				CONFIG_SYS_PCIE3_IO_PHYS,
				CONFIG_SYS_PCIE3_IO_SIZE,
				PCI_REGION_IO);

		hose->region_count = r - hose->regions;
		hose->first_busno = first_free_busno;
		pci_setup_indirect(hose, (int)&pci->cfg_addr,
				  (int)&pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno = hose->last_busno+1;
		printf("    PCIE3 on bus %02x - %02x\n",
				hose->first_busno, hose->last_busno);

	} else {
		printf("    PCIE3: disabled\n");
	}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
#endif

#ifdef CONFIG_PCIE1
	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	hose = &pcie1_hose;
	pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
	pcie_configured  = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
	r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
		printf("\n    PCIE1 connected to Slot 2 as %s (base addr %x)",
				pcie_ep ? "End Point" : "Root Complex",
				(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug(" with errors.  Clearing.  Now 0x%08x",
				pci->pme_msg_det);
		}
		printf("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
				CONFIG_SYS_PCIE1_MEM_BUS,
				CONFIG_SYS_PCIE1_MEM_PHYS,
				CONFIG_SYS_PCIE1_MEM_SIZE,
				PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
				CONFIG_SYS_PCIE1_IO_BUS,
				CONFIG_SYS_PCIE1_IO_PHYS,
				CONFIG_SYS_PCIE1_IO_SIZE,
				PCI_REGION_IO);

		hose->region_count = r - hose->regions;
		hose->first_busno = first_free_busno;

		pci_setup_indirect(hose, (int)&pci->cfg_addr,
				  (int)&pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno = hose->last_busno+1;
		printf("    PCIE1 on bus %02x - %02x\n",
			hose->first_busno, hose->last_busno);

	} else {
		printf("    PCIE1: disabled\n");
	}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif
}
#endif

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	const u8 flash_esel = 2;

	/*
	 * Remap Boot flash + PROMJET region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash + promjet */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel, BOOKE_PAGESZ_256M, 1);

	return 0;
}

#ifdef CONFIG_GET_CLK_FROM_ICS307
/* decode S[0-2] to Output Divider (OD) */
static unsigned char ics307_S_to_OD[] = {
	10, 2, 8, 4, 5, 7, 3, 6
};

/* Calculate frequency being generated by ICS307-02 clock chip based upon
 * the control bytes being programmed into it. */
/* XXX: This function should probably go into a common library */
static unsigned long
ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
{
	const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
	unsigned long RDW = cw2 & 0x7F;
	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
	unsigned long freq;

	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */

	/* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
	 *
	 * R6:R0 = Reference Divider Word (RDW)
	 * V8:V0 = VCO Divider Word (VDW)
	 * S2:S0 = Output Divider Select (OD)
	 * F1:F0 = Function of CLK2 Output
	 * TTL = duty cycle
	 * C1:C0 = internal load capacitance for cyrstal
	 */

	/* Adding 1 to get a "nicely" rounded number, but this needs
	 * more tweaking to get a "properly" rounded number. */

	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));

	debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
			freq);
	return freq;
}

unsigned long get_board_sys_clk(ulong dummy)
{
	return gd->bus_clk;
}

unsigned long get_board_ddr_clk(ulong dummy)
{
	return gd->mem_clk;
}

unsigned long
calculate_board_sys_clk(ulong dummy)
{
	ulong val;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	val = ics307_clk_freq(
	    in_8(pixis_base + PIXIS_VSYSCLK0),
	    in_8(pixis_base + PIXIS_VSYSCLK1),
	    in_8(pixis_base + PIXIS_VSYSCLK2));
	debug("sysclk val = %lu\n", val);
	return val;
}

unsigned long
calculate_board_ddr_clk(ulong dummy)
{
	ulong val;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	val = ics307_clk_freq(
	    in_8(pixis_base + PIXIS_VDDRCLK0),
	    in_8(pixis_base + PIXIS_VDDRCLK1),
	    in_8(pixis_base + PIXIS_VDDRCLK2));
	debug("ddrclk val = %lu\n", val);
	return val;
}
#else
unsigned long get_board_sys_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	i = in_8(pixis_base + PIXIS_SPD);
	i &= 0x07;

	switch (i) {
		case 0:
			val = 33333333;
			break;
		case 1:
			val = 40000000;
			break;
		case 2:
			val = 50000000;
			break;
		case 3:
			val = 66666666;
			break;
		case 4:
			val = 83333333;
			break;
		case 5:
			val = 100000000;
			break;
		case 6:
			val = 133333333;
			break;
		case 7:
			val = 166666666;
			break;
	}

	return val;
}

unsigned long get_board_ddr_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	i = in_8(pixis_base + PIXIS_SPD);
	i &= 0x38;
	i >>= 3;

	switch (i) {
		case 0:
			val = 33333333;
			break;
		case 1:
			val = 40000000;
			break;
		case 2:
			val = 50000000;
			break;
		case 3:
			val = 66666666;
			break;
		case 4:
			val = 83333333;
			break;
		case 5:
			val = 100000000;
			break;
		case 6:
			val = 133333333;
			break;
		case 7:
			val = 166666666;
			break;
	}
	return val;
}
#endif

#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
	struct tsec_info_struct tsec_info[4];
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif
#ifdef CONFIG_TSEC3
	SET_STD_TSEC_INFO(tsec_info[num], 3);
	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
		tsec_info[num].flags |= TSEC_SGMII;
	num++;
#endif

	if (!num) {
		printf("No TSECs initialized\n");

		return 0;
	}

#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_init(tsec_info, num);
#endif

	tsec_eth_init(bis, tsec_info, num);

	return pci_eth_init(bis);
}
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#ifdef CONFIG_PCIE3
	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE2
	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
#ifdef CONFIG_FSL_SGMII_RISER
	fsl_sgmii_riser_fdt_fixup(blob);
#endif
}
#endif

#ifdef CONFIG_MP
void board_lmb_reserve(struct lmb *lmb)
{
	cpu_mp_lmb_reserve(lmb);
}
#endif
Commit	Line	Data
feb7838f SS	1	/*
	2	* Copyright 2007-2009 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <command.h>
	25	#include <pci.h>
	26	#include <asm/processor.h>
	27	#include <asm/mmu.h>
	28	#include <asm/cache.h>
	29	#include <asm/immap_85xx.h>
	30	#include <asm/fsl_pci.h>
	31	#include <asm/fsl_ddr_sdram.h>
	32	#include <asm/io.h>
	33	#include <miiphy.h>
	34	#include <libfdt.h>
	35	#include <fdt_support.h>
	36	#include <tsec.h>
	37	#include <asm/fsl_law.h>
	38	#include <asm/mp.h>
29c35182	39	#include <netdev.h>
feb7838f SS	40
	41	#include "../common/pixis.h"
	42	#include "../common/sgmii_riser.h"
	43
	44	DECLARE_GLOBAL_DATA_PTR;
	45
	46	phys_size_t fixed_sdram(void);
	47
	48	int checkboard(void)
	49	{
6bb5b412 KG	50	u8 sw7;
	51	u8 pixis_base = (u8 )PIXIS_BASE;
	52
feb7838f SS	53	puts("Board: P2020DS ");
	54	#ifdef CONFIG_PHYS_64BIT
	55	puts("(36-bit addrmap) ");
	56	#endif
6bb5b412	57
feb7838f	58	printf("Sys ID: 0x%02x, "
6bb5b412 KG	59	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
	60	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
	61	in_8(pixis_base + PIXIS_PVER));
	62
	63	sw7 = in_8(pixis_base + PIXIS_SW(7));
	64	switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
	65	case 0:
	66	case 1:
	67	printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
	68	break;
	69	case 2:
	70	case 3:
	71	puts ("Promjet\n");
	72	break;
	73	}
	74
feb7838f SS	75	return 0;
	76	}
	77
	78	phys_size_t initdram(int board_type)
	79	{
	80	phys_size_t dram_size = 0;
	81
	82	puts("Initializing....");
	83
	84	#ifdef CONFIG_SPD_EEPROM
	85	dram_size = fsl_ddr_sdram();
	86	#else
	87	dram_size = fixed_sdram();
	88
	89	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
	90	dram_size,
	91	LAW_TRGT_IF_DDR) < 0) {
	92	printf("ERROR setting Local Access Windows for DDR\n");
	93	return 0;
	94	};
	95	#endif
	96	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	97	dram_size *= 0x100000;
	98
	99	puts(" DDR: ");
	100	return dram_size;
	101	}
	102
	103	#if !defined(CONFIG_SPD_EEPROM)
	104	/*
	105	* Fixed sdram init -- doesn't use serial presence detect.
	106	*/
	107
	108	phys_size_t fixed_sdram(void)
	109	{
	110	volatile ccsr_ddr_t ddr = (ccsr_ddr_t )CONFIG_SYS_MPC85xx_DDR_ADDR;
	111	uint d_init;
	112
	113	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	114	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
	115	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	116	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
	117	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
	118	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
	119	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	120	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
	121	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
	122	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
	123	ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
	124	ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
	125	ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
	126	ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
	127	ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
	128
	129	if (!strcmp("performance", getenv("perf_mode"))) {
	130	/* Performance Mode Values */
	131
	132	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
	133	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
	134	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
	135	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
	136	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
	137
	138	asm("sync;isync");
139
140	udelay(500);
141
142	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
143	} else {
144	/* Stable Mode Values */
145
146	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
147	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
148	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
149	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
150	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
151
152	/* ECC will be assumed in stable mode */
153	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
154	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
155	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
156
157	asm("sync;isync");
158
159	udelay(500);
160
161	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
162	}
163
164	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
165	d_init = 1;
166	debug("DDR - 1st controller: memory initializing\n");
167	/*
168	* Poll until memory is initialized.
169	* 512 Meg at 400 might hit this 200 times or so.
170	*/
171	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
172	udelay(1000);
173	debug("DDR: memory initialized\n\n");
174	asm("sync; isync");
175	udelay(500);
176	#endif
177
178	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
179	}
180
181	#endif
182
183	#ifdef CONFIG_PCIE1
184	static struct pci_controller pcie1_hose;
185	#endif
186
187	#ifdef CONFIG_PCIE2
188	static struct pci_controller pcie2_hose;
189	#endif
190
191	#ifdef CONFIG_PCIE3
192	static struct pci_controller pcie3_hose;
193	#endif
194
195	int first_free_busno = 0;
196
197	#ifdef CONFIG_PCI
198	void pci_init_board(void)
199	{
200	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
201	uint devdisr = gur->devdisr;
202	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
203	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
204
205	volatile ccsr_fsl_pci_t *pci;
206	struct pci_controller *hose;
207	int pcie_ep, pcie_configured;
208	struct pci_region *r;
209	/* u32 temp32; */
210
211	debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
212	devdisr, io_sel, host_agent);
213
214	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
215	printf(" eTSEC2 is in sgmii mode.\n");
216	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
217	printf(" eTSEC3 is in sgmii mode.\n");
218
219	#ifdef CONFIG_PCIE2
220	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
221	hose = &pcie2_hose;
222	pcie_ep = (host_agent == 2) \|\| (host_agent == 4) \|\|
223	(host_agent == 6) \|\| (host_agent == 0);
224	pcie_configured = (io_sel == 0x2) \|\| (io_sel == 0xe);
225	r = hose->regions;
226
227	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
228	printf("\n PCIE2 connected to ULI as %s (base addr %x)",
229	pcie_ep ? "End Point" : "Root Complex",
230	(uint)pci);
231	if (pci->pme_msg_det) {
232	pci->pme_msg_det = 0xffffffff;
233	debug(" with errors. Clearing. Now 0x%08x",
234	pci->pme_msg_det);
235	}
236	printf("\n");
237
238	/* inbound */
239	r += fsl_pci_setup_inbound_windows(r);
240
241	/* outbound memory */
242	pci_set_region(r++,
243	CONFIG_SYS_PCIE2_MEM_BUS,
244	CONFIG_SYS_PCIE2_MEM_PHYS,
245	CONFIG_SYS_PCIE2_MEM_SIZE,
246	PCI_REGION_MEM);
247
248	/* outbound io */
249	pci_set_region(r++,
250	CONFIG_SYS_PCIE2_IO_BUS,
251	CONFIG_SYS_PCIE2_IO_PHYS,
252	CONFIG_SYS_PCIE2_IO_SIZE,
253	PCI_REGION_IO);
254
255	hose->region_count = r - hose->regions;
256	hose->first_busno = first_free_busno;
257	pci_setup_indirect(hose, (int)&pci->cfg_addr,
258	(int)&pci->cfg_data);
259
260	fsl_pci_init(hose);
261	first_free_busno = hose->last_busno+1;
262	printf(" PCIE2 on bus %02x - %02x\n",
263	hose->first_busno, hose->last_busno);
264
265	/*
266	* The workaround doesn't work on p2020 because the location
267	* we try and read isn't valid on p2020, fix this later
268	*/
269	#if 0
270	/*
271	* Activate ULI1575 legacy chip by performing a fake
272	* memory access. Needed to make ULI RTC work.
273	* Device 1d has the first on-board memory BAR.
274	*/
275
276	pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
277	PCI_BASE_ADDRESS_1, &temp32);
278	if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
279	void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
280	temp32, 4, 0);
281	debug(" uli1575 read to %p\n", p);
282	in_be32(p);
283	}
284	#endif
285	} else {
286	printf(" PCIE2: disabled\n");
287	}
288	#else
289	gur->devdisr \|= MPC85xx_DEVDISR_PCIE2; /* disable */
290	#endif
291
292	#ifdef CONFIG_PCIE3
293	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
294	hose = &pcie3_hose;
295	pcie_ep = (host_agent == 0) \|\| (host_agent == 3) \|\|
296	(host_agent == 5) \|\| (host_agent == 6);
297	pcie_configured = (io_sel == 0x2) \|\| (io_sel == 0x4);
298	r = hose->regions;
299
300	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
301	printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)",
302	pcie_ep ? "End Point" : "Root Complex",
303	(uint)pci);
304	if (pci->pme_msg_det) {
305	pci->pme_msg_det = 0xffffffff;
306	debug(" with errors. Clearing. Now 0x%08x",
307	pci->pme_msg_det);
308	}
309	printf("\n");
310
311	/* inbound */
312	r += fsl_pci_setup_inbound_windows(r);
313
314	/* outbound memory */
315	pci_set_region(r++,
316	CONFIG_SYS_PCIE3_MEM_BUS,
317	CONFIG_SYS_PCIE3_MEM_PHYS,
318	CONFIG_SYS_PCIE3_MEM_SIZE,
319	PCI_REGION_MEM);
320
321	/* outbound io */
322	pci_set_region(r++,
323	CONFIG_SYS_PCIE3_IO_BUS,
324	CONFIG_SYS_PCIE3_IO_PHYS,
325	CONFIG_SYS_PCIE3_IO_SIZE,
326	PCI_REGION_IO);
327
328	hose->region_count = r - hose->regions;
329	hose->first_busno = first_free_busno;
330	pci_setup_indirect(hose, (int)&pci->cfg_addr,
331	(int)&pci->cfg_data);
332
333	fsl_pci_init(hose);
334
335	first_free_busno = hose->last_busno+1;
336	printf(" PCIE3 on bus %02x - %02x\n",
337	hose->first_busno, hose->last_busno);
338
339	} else {
340	printf(" PCIE3: disabled\n");
341	}
342	#else
343	gur->devdisr \|= MPC85xx_DEVDISR_PCIE3; /* disable */
344	#endif
345
346	#ifdef CONFIG_PCIE1
347	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
348	hose = &pcie1_hose;
349	pcie_ep = (host_agent <= 1) \|\| (host_agent == 4) \|\| (host_agent == 5);
350	pcie_configured = (io_sel & 6) \|\| (io_sel == 0xE) \|\| (io_sel == 0xF);
351	r = hose->regions;
352
353	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
354	printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)",
355	pcie_ep ? "End Point" : "Root Complex",
356	(uint)pci);
357	if (pci->pme_msg_det) {
358	pci->pme_msg_det = 0xffffffff;
359	debug(" with errors. Clearing. Now 0x%08x",
360	pci->pme_msg_det);
361	}
362	printf("\n");
363
364	/* inbound */
365	r += fsl_pci_setup_inbound_windows(r);
366
367	/* outbound memory */
368	pci_set_region(r++,
369	CONFIG_SYS_PCIE1_MEM_BUS,
370	CONFIG_SYS_PCIE1_MEM_PHYS,
371	CONFIG_SYS_PCIE1_MEM_SIZE,
372	PCI_REGION_MEM);
373
374	/* outbound io */
375	pci_set_region(r++,
376	CONFIG_SYS_PCIE1_IO_BUS,
377	CONFIG_SYS_PCIE1_IO_PHYS,
378	CONFIG_SYS_PCIE1_IO_SIZE,
379	PCI_REGION_IO);
380
381	hose->region_count = r - hose->regions;
382	hose->first_busno = first_free_busno;
383
384	pci_setup_indirect(hose, (int)&pci->cfg_addr,
385	(int)&pci->cfg_data);
386
387	fsl_pci_init(hose);
388
389	first_free_busno = hose->last_busno+1;
390	printf(" PCIE1 on bus %02x - %02x\n",
391	hose->first_busno, hose->last_busno);
392
393	} else {
394	printf(" PCIE1: disabled\n");
395	}
396	#else
397	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
398	#endif
399	}
400	#endif
401
402	int board_early_init_r(void)
403	{
404	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
405	const u8 flash_esel = 2;
406
407	/*
408	* Remap Boot flash + PROMJET region to caching-inhibited
409	* so that flash can be erased properly.
410	*/
411
412	/* Flush d-cache and invalidate i-cache of any FLASH data */
413	flush_dcache();
414	invalidate_icache();
415
416	/* invalidate existing TLB entry for flash + promjet */
417	disable_tlb(flash_esel);
418
419	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
420	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
421	0, flash_esel, BOOKE_PAGESZ_256M, 1);
422
423	return 0;
424	}
425
426	#ifdef CONFIG_GET_CLK_FROM_ICS307
427	/* decode S[0-2] to Output Divider (OD) */
428	static unsigned char ics307_S_to_OD[] = {
429	10, 2, 8, 4, 5, 7, 3, 6
430	};
431
432	/* Calculate frequency being generated by ICS307-02 clock chip based upon
433	* the control bytes being programmed into it. */
434	/* XXX: This function should probably go into a common library */
435	static unsigned long
436	ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
437	{
438	const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
439	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
440	unsigned long RDW = cw2 & 0x7F;
441	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
442	unsigned long freq;
443
444	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
445
446	/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
447	* cw1: V8 V7 V6 V5 V4 V3 V2 V1
448	* cw2: V0 R6 R5 R4 R3 R2 R1 R0
449	*
450	* R6:R0 = Reference Divider Word (RDW)
451	* V8:V0 = VCO Divider Word (VDW)
452	* S2:S0 = Output Divider Select (OD)
453	* F1:F0 = Function of CLK2 Output
454	* TTL = duty cycle
455	* C1:C0 = internal load capacitance for cyrstal
456	*/
457
458	/* Adding 1 to get a "nicely" rounded number, but this needs
459	* more tweaking to get a "properly" rounded number. */
460
461	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
462
463	debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
464	freq);
465	return freq;
466	}
467
468	unsigned long get_board_sys_clk(ulong dummy)
469	{
470	return gd->bus_clk;
471	}
472
473	unsigned long get_board_ddr_clk(ulong dummy)
474	{
475	return gd->mem_clk;
476	}
477
478	unsigned long
479	calculate_board_sys_clk(ulong dummy)
480	{
481	ulong val;
048e7efe KG	482	u8 pixis_base = (u8 )PIXIS_BASE;
048e7efe KG	483
feb7838f	484	val = ics307_clk_freq(
048e7efe KG	485	in_8(pixis_base + PIXIS_VSYSCLK0),
	486	in_8(pixis_base + PIXIS_VSYSCLK1),
	487	in_8(pixis_base + PIXIS_VSYSCLK2));
feb7838f SS	488	debug("sysclk val = %lu\n", val);
	489	return val;
	490	}
	491
	492	unsigned long
	493	calculate_board_ddr_clk(ulong dummy)
	494	{
	495	ulong val;
048e7efe KG	496	u8 pixis_base = (u8 )PIXIS_BASE;
048e7efe KG	497
feb7838f	498	val = ics307_clk_freq(
048e7efe KG	499	in_8(pixis_base + PIXIS_VDDRCLK0),
	500	in_8(pixis_base + PIXIS_VDDRCLK1),
	501	in_8(pixis_base + PIXIS_VDDRCLK2));
feb7838f SS	502	debug("ddrclk val = %lu\n", val);
	503	return val;
	504	}
	505	#else
	506	unsigned long get_board_sys_clk(ulong dummy)
	507	{
	508	u8 i;
	509	ulong val = 0;
048e7efe	510	u8 pixis_base = (u8 )PIXIS_BASE;
feb7838f	511
048e7efe	512	i = in_8(pixis_base + PIXIS_SPD);
feb7838f SS	513	i &= 0x07;
	514
	515	switch (i) {
	516	case 0:
	517	val = 33333333;
	518	break;
	519	case 1:
	520	val = 40000000;
	521	break;
	522	case 2:
	523	val = 50000000;
	524	break;
	525	case 3:
	526	val = 66666666;
	527	break;
	528	case 4:
	529	val = 83333333;
	530	break;
	531	case 5:
	532	val = 100000000;
	533	break;
	534	case 6:
	535	val = 133333333;
	536	break;
	537	case 7:
	538	val = 166666666;
	539	break;
	540	}
	541
	542	return val;
	543	}
	544
	545	unsigned long get_board_ddr_clk(ulong dummy)
	546	{
	547	u8 i;
	548	ulong val = 0;
048e7efe	549	u8 pixis_base = (u8 )PIXIS_BASE;
feb7838f	550
048e7efe	551	i = in_8(pixis_base + PIXIS_SPD);
feb7838f SS	552	i &= 0x38;
	553	i >>= 3;
	554
	555	switch (i) {
	556	case 0:
	557	val = 33333333;
	558	break;
	559	case 1:
	560	val = 40000000;
	561	break;
	562	case 2:
	563	val = 50000000;
	564	break;
	565	case 3:
	566	val = 66666666;
	567	break;
	568	case 4:
	569	val = 83333333;
	570	break;
	571	case 5:
	572	val = 100000000;
	573	break;
	574	case 6:
	575	val = 133333333;
	576	break;
	577	case 7:
	578	val = 166666666;
	579	break;
	580	}
	581	return val;
	582	}
	583	#endif
	584
	585	#ifdef CONFIG_TSEC_ENET
	586	int board_eth_init(bd_t *bis)
	587	{
	588	struct tsec_info_struct tsec_info[4];
	589	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	590	int num = 0;
	591
	592	#ifdef CONFIG_TSEC1
	593	SET_STD_TSEC_INFO(tsec_info[num], 1);
	594	num++;
	595	#endif
	596	#ifdef CONFIG_TSEC2
	597	SET_STD_TSEC_INFO(tsec_info[num], 2);
	598	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
	599	tsec_info[num].flags \|= TSEC_SGMII;
	600	num++;
	601	#endif
	602	#ifdef CONFIG_TSEC3
	603	SET_STD_TSEC_INFO(tsec_info[num], 3);
	604	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	605	tsec_info[num].flags \|= TSEC_SGMII;
	606	num++;
	607	#endif
	608
	609	if (!num) {
	610	printf("No TSECs initialized\n");
	611
	612	return 0;
	613	}
	614
	615	#ifdef CONFIG_FSL_SGMII_RISER
616	fsl_sgmii_riser_init(tsec_info, num);
617	#endif
618
619	tsec_eth_init(bis, tsec_info, num);
620
29c35182	621	return pci_eth_init(bis);
feb7838f SS	622	}
	623	#endif
	624
	625	#if defined(CONFIG_OF_BOARD_SETUP)
	626	void ft_board_setup(void blob, bd_t bd)
	627	{
	628	phys_addr_t base;
	629	phys_size_t size;
	630
	631	ft_cpu_setup(blob, bd);
	632
	633	base = getenv_bootm_low();
	634	size = getenv_bootm_size();
	635
	636	fdt_fixup_memory(blob, (u64)base, (u64)size);
	637
	638	#ifdef CONFIG_PCIE3
	639	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
	640	#endif
	641	#ifdef CONFIG_PCIE2
	642	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
	643	#endif
	644	#ifdef CONFIG_PCIE1
	645	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
	646	#endif
	647	#ifdef CONFIG_FSL_SGMII_RISER
	648	fsl_sgmii_riser_fdt_fixup(blob);
	649	#endif
	650	}
	651	#endif
	652
	653	#ifdef CONFIG_MP
	654	void board_lmb_reserve(struct lmb *lmb)
	655	{
	656	cpu_mp_lmb_reserve(lmb);
	657	}
	658	#endif