[people/ms/u-boot.git] / board / freescale / t102xrdb / eth_t102xrdb.c

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include "../common/fman.h"

int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
	int i, interface;
	struct memac_mdio_info dtsec_mdio_info;
	struct memac_mdio_info tgec_mdio_info;
	struct mii_dev *dev;
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 srds_s1;

	srds_s1 = in_be32(&gur->rcwsr[4]) &
					FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;

	dtsec_mdio_info.regs =
		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;

	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;

	/* Register the 1G MDIO bus */
	fm_memac_mdio_init(bis, &dtsec_mdio_info);

	tgec_mdio_info.regs =
		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;

	/* Register the 10G MDIO bus */
	fm_memac_mdio_init(bis, &tgec_mdio_info);

	/* Set the on-board RGMII PHY address */
	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);

	switch (srds_s1) {
#ifdef CONFIG_T1024RDB
	case 0x95:
		/* set the on-board RGMII2  PHY */
		fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);

		/* set 10G XFI with Aquantia AQR105 PHY */
		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
		break;
#endif
	case 0x6a:
	case 0x6b:
	case 0x77:
	case 0x135:
		/* set the on-board 2.5G SGMII AQR105 PHY */
		fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
#ifdef CONFIG_T1023RDB
		/* set the on-board 1G SGMII RTL8211F PHY */
		fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
#endif
		break;
	default:
		printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
		       srds_s1);
		break;
	}

	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
		interface = fm_info_get_enet_if(i);
		switch (interface) {
		case PHY_INTERFACE_MODE_RGMII:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		case PHY_INTERFACE_MODE_SGMII:
#if defined(CONFIG_T1023RDB)
			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
#elif defined(CONFIG_T1024RDB)
			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
#endif
			fm_info_set_mdio(i, dev);
			break;
		case PHY_INTERFACE_MODE_SGMII_2500:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		default:
			break;
		}
	}

	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
		switch (fm_info_get_enet_if(i)) {
		case PHY_INTERFACE_MODE_XGMII:
			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
			fm_info_set_mdio(i, dev);
			break;
		default:
			break;
		}
	}

	cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */

	return pci_eth_init(bis);
}

void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
			      enum fm_port port, int offset)
{
#if defined(CONFIG_T1024RDB)
	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
	     (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
			(port == FM1_DTSEC3)) {
		fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
		fdt_setprop(fdt, offset, "phy-connection-type",
			    "sgmii-2500", 10);
		fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
	}
#endif
}

void fdt_fixup_board_enet(void *fdt)
{
}
Commit	Line	Data
48c6f328 SL	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
e8a7f1c3 SL	4	* Shengzhou Liu <Shengzhou.Liu@freescale.com>
e8a7f1c3 SL	5	*
48c6f328 SL	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10	#include <command.h>
	11	#include <netdev.h>
	12	#include <asm/mmu.h>
	13	#include <asm/processor.h>
	14	#include <asm/immap_85xx.h>
	15	#include <asm/fsl_law.h>
	16	#include <asm/fsl_serdes.h>
	17	#include <asm/fsl_portals.h>
	18	#include <asm/fsl_liodn.h>
	19	#include <malloc.h>
	20	#include <fm_eth.h>
	21	#include <fsl_mdio.h>
	22	#include <miiphy.h>
	23	#include <phy.h>
	24	#include <asm/fsl_dtsec.h>
	25	#include <asm/fsl_serdes.h>
e26416a3	26	#include "../common/fman.h"
48c6f328 SL	27
	28	int board_eth_init(bd_t *bis)
	29	{
	30	#if defined(CONFIG_FMAN_ENET)
	31	int i, interface;
	32	struct memac_mdio_info dtsec_mdio_info;
	33	struct memac_mdio_info tgec_mdio_info;
	34	struct mii_dev *dev;
	35	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	36	u32 srds_s1;
	37
	38	srds_s1 = in_be32(&gur->rcwsr[4]) &
	39	FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	40	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
	41
	42	dtsec_mdio_info.regs =
	43	(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
	44
	45	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
	46
	47	/* Register the 1G MDIO bus */
	48	fm_memac_mdio_init(bis, &dtsec_mdio_info);
	49
	50	tgec_mdio_info.regs =
	51	(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
	52	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
	53
	54	/* Register the 10G MDIO bus */
	55	fm_memac_mdio_init(bis, &tgec_mdio_info);
	56
e26416a3	57	/* Set the on-board RGMII PHY address */
48c6f328 SL	58	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
	59
	60	switch (srds_s1) {
e8a7f1c3	61	#ifdef CONFIG_T1024RDB
48c6f328	62	case 0x95:
e26416a3 SL	63	/* set the on-board RGMII2 PHY */
	64	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
	65
	66	/* set 10G XFI with Aquantia AQR105 PHY */
48c6f328 SL	67	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
48c6f328 SL	68	break;
e8a7f1c3 SL	69	#endif
	70	case 0x6a:
	71	case 0x6b:
e26416a3 SL	72	case 0x77:
	73	case 0x135:
	74	/* set the on-board 2.5G SGMII AQR105 PHY */
e8a7f1c3 SL	75	fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
	76	#ifdef CONFIG_T1023RDB
	77	/* set the on-board 1G SGMII RTL8211F PHY */
	78	fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
	79	#endif
e26416a3	80	break;
48c6f328 SL	81	default:
	82	printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
	83	srds_s1);
	84	break;
	85	}
	86
	87	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
	88	interface = fm_info_get_enet_if(i);
	89	switch (interface) {
	90	case PHY_INTERFACE_MODE_RGMII:
	91	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
	92	fm_info_set_mdio(i, dev);
	93	break;
e8a7f1c3 SL	94	case PHY_INTERFACE_MODE_SGMII:
	95	#if defined(CONFIG_T1023RDB)
	96	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
	97	#elif defined(CONFIG_T1024RDB)
	98	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
	99	#endif
	100	fm_info_set_mdio(i, dev);
	101	break;
e26416a3 SL	102	case PHY_INTERFACE_MODE_SGMII_2500:
	103	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
	104	fm_info_set_mdio(i, dev);
	105	break;
48c6f328 SL	106	default:
	107	break;
	108	}
	109	}
	110
	111	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
	112	switch (fm_info_get_enet_if(i)) {
	113	case PHY_INTERFACE_MODE_XGMII:
	114	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
	115	fm_info_set_mdio(i, dev);
	116	break;
	117	default:
	118	break;
	119	}
	120	}
	121
	122	cpu_eth_init(bis);
	123	#endif /* CONFIG_FMAN_ENET */
	124
	125	return pci_eth_init(bis);
	126	}
	127
e26416a3 SL	128	void board_ft_fman_fixup_port(void fdt, char compat, phys_addr_t addr,
	129	enum fm_port port, int offset)
	130	{
e8a7f1c3 SL	131	#if defined(CONFIG_T1024RDB)
	132	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) \|\|
	133	(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
	134	(port == FM1_DTSEC3)) {
e26416a3 SL	135	fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
	136	fdt_setprop(fdt, offset, "phy-connection-type",
	137	"sgmii-2500", 10);
	138	fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
	139	}
e8a7f1c3	140	#endif
e26416a3 SL	141	}
e26416a3 SL	142
48c6f328 SL	143	void fdt_fixup_board_enet(void *fdt)
	144	{
	145	}