[people/ms/u-boot.git] / board / freescale / t104xrdb / t104xrdb.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <asm/mpc85xx_gpio.h>

#include "t104xrdb.h"
#include "cpld.h"

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	struct cpu_type *cpu = gd->arch.cpu;
	u8 sw;

	printf("Board: %sRDB\n", cpu->name);
	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));

	sw = CPLD_READ(flash_ctl_status);
	sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);

	if (sw <= 7)
		printf("vBank: %d\n", sw);
	else
		printf("Unsupported Bank=%x\n", sw);

	return 0;
}

int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
	set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
	setup_portals();
#endif

	return 0;
}

int misc_init_r(void)
{
	return 0;
}

void ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#ifdef CONFIG_PCI
	pci_of_setup(blob, bd);
#endif

	fdt_fixup_liodn(blob);

#ifdef CONFIG_HAS_FSL_DR_USB
	fdt_fixup_dr_usb(blob, bd);
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	fdt_fixup_fman_ethernet(blob);
#endif
}

#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
	/* does not provide HW signals for power management */
	CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
	/* Disable MCKE isolation */
	gpio_set_value(2, 0);
	udelay(1);
}
#endif
Commit	Line	Data
062ef1a6 PJ	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <command.h>
	9	#include <netdev.h>
	10	#include <linux/compiler.h>
	11	#include <asm/mmu.h>
	12	#include <asm/processor.h>
	13	#include <asm/cache.h>
	14	#include <asm/immap_85xx.h>
	15	#include <asm/fsl_law.h>
	16	#include <asm/fsl_serdes.h>
	17	#include <asm/fsl_portals.h>
	18	#include <asm/fsl_liodn.h>
	19	#include <fm_eth.h>
5303a3de	20	#include <asm/mpc85xx_gpio.h>
062ef1a6 PJ	21
062ef1a6 PJ	22	#include "t104xrdb.h"
55153d6c	23	#include "cpld.h"
062ef1a6 PJ	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
	27	int checkboard(void)
	28	{
	29	struct cpu_type *cpu = gd->arch.cpu;
55153d6c	30	u8 sw;
062ef1a6 PJ	31
062ef1a6 PJ	32	printf("Board: %sRDB\n", cpu->name);
55153d6c PK	33	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
	34	CPLD_READ(hw_ver), CPLD_READ(sw_ver));
	35
	36	sw = CPLD_READ(flash_ctl_status);
	37	sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
	38
	39	if (sw <= 7)
	40	printf("vBank: %d\n", sw);
	41	else
	42	printf("Unsupported Bank=%x\n", sw);
	43
062ef1a6 PJ	44	return 0;
	45	}
	46
	47	int board_early_init_r(void)
	48	{
	49	#ifdef CONFIG_SYS_FLASH_BASE
	50	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	51	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
	52
	53	/*
	54	* Remap Boot flash region to caching-inhibited
	55	* so that flash can be erased properly.
	56	*/
	57
	58	/* Flush d-cache and invalidate i-cache of any FLASH data */
	59	flush_dcache();
	60	invalidate_icache();
	61
	62	/* invalidate existing TLB entry for flash */
	63	disable_tlb(flash_esel);
	64
	65	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	66	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	67	0, flash_esel, BOOKE_PAGESZ_256M, 1);
	68	#endif
	69	set_liodns();
	70	#ifdef CONFIG_SYS_DPAA_QBMAN
	71	setup_portals();
	72	#endif
	73
	74	return 0;
	75	}
	76
	77	int misc_init_r(void)
	78	{
	79	return 0;
	80	}
	81
	82	void ft_board_setup(void blob, bd_t bd)
	83	{
	84	phys_addr_t base;
	85	phys_size_t size;
	86
	87	ft_cpu_setup(blob, bd);
	88
	89	base = getenv_bootm_low();
	90	size = getenv_bootm_size();
	91
	92	fdt_fixup_memory(blob, (u64)base, (u64)size);
	93
	94	#ifdef CONFIG_PCI
	95	pci_of_setup(blob, bd);
	96	#endif
	97
	98	fdt_fixup_liodn(blob);
	99
	100	#ifdef CONFIG_HAS_FSL_DR_USB
	101	fdt_fixup_dr_usb(blob, bd);
	102	#endif
	103
	104	#ifdef CONFIG_SYS_DPAA_FMAN
	105	fdt_fixup_fman_ethernet(blob);
	106	#endif
	107	}
5303a3de TY	108
	109	#ifdef CONFIG_DEEP_SLEEP
	110	void board_mem_sleep_setup(void)
	111	{
0f1fa36f TY	112	/* does not provide HW signals for power management */
0f1fa36f TY	113	CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
5303a3de TY	114	/* Disable MCKE isolation */
	115	gpio_set_value(2, 0);
	116	udelay(1);
	117	}
	118	#endif