[people/ms/u-boot.git] / board / freescale / t208xqds / ddr.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"

DECLARE_GLOBAL_DATA_PTR;

void fsl_ddr_board_options(memctl_options_t *popts,
				dimm_params_t *pdimm,
				unsigned int ctrl_num)
{
	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
	ulong ddr_freq;

	if (ctrl_num > 1) {
		printf("Not supported controller number %d\n", ctrl_num);
		return;
	}
	if (!pdimm->n_ranks)
		return;

	/*
	 * we use identical timing for all slots. If needed, change the code
	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
	 */
	if (popts->registered_dimm_en)
		pbsp = rdimms[0];
	else
		pbsp = udimms[0];

	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
	 * freqency and n_banks specified in board_specific_parameters table.
	 */
	ddr_freq = get_ddr_freq(0) / 1000000;
	while (pbsp->datarate_mhz_high) {
		if (pbsp->n_ranks == pdimm->n_ranks &&
		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
			if (ddr_freq <= pbsp->datarate_mhz_high) {
				popts->clk_adjust = pbsp->clk_adjust;
				popts->wrlvl_start = pbsp->wrlvl_start;
				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
				goto found;
			}
			pbsp_highest = pbsp;
		}
		pbsp++;
	}

	if (pbsp_highest) {
		printf("Error: board specific timing not found");
		printf("for data rate %lu MT/s\n", ddr_freq);
		printf("Trying to use the highest speed (%u) parameters\n",
		       pbsp_highest->datarate_mhz_high);
		popts->clk_adjust = pbsp_highest->clk_adjust;
		popts->wrlvl_start = pbsp_highest->wrlvl_start;
		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
	} else {
		panic("DIMM is not supported by this board");
	}
found:
	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
		"wrlvl_ctrl_3 0x%x\n",
		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
		pbsp->wrlvl_ctl_3);

	/*
	 * Factors to consider for half-strength driver enable:
	 *	- number of DIMMs installed
	 */
	popts->half_strength_driver_enable = 0;
	/*
	 * Write leveling override
	 */
	popts->wrlvl_override = 1;
	popts->wrlvl_sample = 0xf;

	/*
	 * Rtt and Rtt_WR override
	 */
	popts->rtt_override = 0;

	/* Enable ZQ calibration */
	popts->zq_en = 1;

	/* DHC_EN =1, ODT = 75 Ohm */
	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}

phys_size_t initdram(int board_type)
{
	phys_size_t dram_size;

#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
	puts("Initializing....using SPD\n");
	dram_size = fsl_ddr_sdram();

	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;
#else
	/* DDR has been initialised by first stage boot loader */
	dram_size =  fsl_ddr_sdram_size();
#endif

	return dram_size;
}
Commit	Line	Data
c4d0e811 SL	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
5b8031cc	4	* SPDX-License-Identifier: GPL-2.0
c4d0e811 SL	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <hwconfig.h>
	10	#include <asm/mmu.h>
	11	#include <fsl_ddr_sdram.h>
	12	#include <fsl_ddr_dimm_params.h>
	13	#include <asm/fsl_law.h>
	14	#include "ddr.h"
	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
	18	void fsl_ddr_board_options(memctl_options_t *popts,
	19	dimm_params_t *pdimm,
	20	unsigned int ctrl_num)
	21	{
	22	const struct board_specific_parameters pbsp, pbsp_highest = NULL;
	23	ulong ddr_freq;
	24
3fdc827c	25	if (ctrl_num > 1) {
c4d0e811 SL	26	printf("Not supported controller number %d\n", ctrl_num);
	27	return;
	28	}
	29	if (!pdimm->n_ranks)
	30	return;
	31
	32	/*
	33	* we use identical timing for all slots. If needed, change the code
	34	* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
	35	*/
	36	if (popts->registered_dimm_en)
	37	pbsp = rdimms[0];
	38	else
	39	pbsp = udimms[0];
	40
3fdc827c	41	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
c4d0e811 SL	42	* freqency and n_banks specified in board_specific_parameters table.
	43	*/
	44	ddr_freq = get_ddr_freq(0) / 1000000;
	45	while (pbsp->datarate_mhz_high) {
	46	if (pbsp->n_ranks == pdimm->n_ranks &&
	47	(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
	48	if (ddr_freq <= pbsp->datarate_mhz_high) {
c4d0e811 SL	49	popts->clk_adjust = pbsp->clk_adjust;
	50	popts->wrlvl_start = pbsp->wrlvl_start;
	51	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	52	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
c4d0e811 SL	53	goto found;
	54	}
	55	pbsp_highest = pbsp;
	56	}
	57	pbsp++;
	58	}
	59
	60	if (pbsp_highest) {
	61	printf("Error: board specific timing not found");
	62	printf("for data rate %lu MT/s\n", ddr_freq);
	63	printf("Trying to use the highest speed (%u) parameters\n",
	64	pbsp_highest->datarate_mhz_high);
c4d0e811 SL	65	popts->clk_adjust = pbsp_highest->clk_adjust;
	66	popts->wrlvl_start = pbsp_highest->wrlvl_start;
	67	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	68	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
c4d0e811 SL	69	} else {
	70	panic("DIMM is not supported by this board");
	71	}
	72	found:
	73	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
	74	"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
	75	"wrlvl_ctrl_3 0x%x\n",
	76	pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
	77	pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
	78	pbsp->wrlvl_ctl_3);
	79
	80	/*
	81	* Factors to consider for half-strength driver enable:
	82	* - number of DIMMs installed
	83	*/
	84	popts->half_strength_driver_enable = 0;
	85	/*
	86	* Write leveling override
	87	*/
	88	popts->wrlvl_override = 1;
	89	popts->wrlvl_sample = 0xf;
	90
	91	/*
	92	* Rtt and Rtt_WR override
	93	*/
	94	popts->rtt_override = 0;
	95
	96	/* Enable ZQ calibration */
	97	popts->zq_en = 1;
	98
	99	/* DHC_EN =1, ODT = 75 Ohm */
	100	popts->ddr_cdr1 = DDR_CDR1_DHC_EN \| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
	101	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
	102	}
	103
	104	phys_size_t initdram(int board_type)
	105	{
	106	phys_size_t dram_size;
	107
b19e288f	108	#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_RAMBOOT_PBL)
c4d0e811	109	puts("Initializing....using SPD\n");
c4d0e811 SL	110	dram_size = fsl_ddr_sdram();
	111
	112	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	113	dram_size *= 0x100000;
b19e288f SL	114	#else
	115	/* DDR has been initialised by first stage boot loader */
	116	dram_size = fsl_ddr_sdram_size();
	117	#endif
c4d0e811	118
c4d0e811 SL	119	return dram_size;
c4d0e811 SL	120	}