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Commit | Line | Data |
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8d67c368 SL |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
8d67c368 SL |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <i2c.h> | |
9 | #include <hwconfig.h> | |
10 | #include <asm/mmu.h> | |
11 | #include <fsl_ddr_sdram.h> | |
12 | #include <fsl_ddr_dimm_params.h> | |
13 | #include <asm/fsl_law.h> | |
14 | #include "ddr.h" | |
15 | ||
16 | DECLARE_GLOBAL_DATA_PTR; | |
17 | ||
18 | void fsl_ddr_board_options(memctl_options_t *popts, | |
19 | dimm_params_t *pdimm, | |
20 | unsigned int ctrl_num) | |
21 | { | |
22 | const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; | |
23 | ulong ddr_freq; | |
24 | ||
25 | if (ctrl_num > 1) { | |
26 | printf("Not supported controller number %d\n", ctrl_num); | |
27 | return; | |
28 | } | |
29 | if (!pdimm->n_ranks) | |
30 | return; | |
31 | ||
32 | pbsp = udimms[0]; | |
33 | ||
34 | /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr | |
35 | * freqency and n_banks specified in board_specific_parameters table. | |
36 | */ | |
37 | ddr_freq = get_ddr_freq(0) / 1000000; | |
38 | while (pbsp->datarate_mhz_high) { | |
39 | if (pbsp->n_ranks == pdimm->n_ranks && | |
40 | (pdimm->rank_density >> 30) >= pbsp->rank_gb) { | |
41 | if (ddr_freq <= pbsp->datarate_mhz_high) { | |
42 | popts->clk_adjust = pbsp->clk_adjust; | |
43 | popts->wrlvl_start = pbsp->wrlvl_start; | |
44 | popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; | |
45 | popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; | |
46 | goto found; | |
47 | } | |
48 | pbsp_highest = pbsp; | |
49 | } | |
50 | pbsp++; | |
51 | } | |
52 | ||
53 | if (pbsp_highest) { | |
54 | printf("Error: board specific timing not found"); | |
55 | printf("for data rate %lu MT/s\n", ddr_freq); | |
56 | printf("Trying to use the highest speed (%u) parameters\n", | |
57 | pbsp_highest->datarate_mhz_high); | |
58 | popts->clk_adjust = pbsp_highest->clk_adjust; | |
59 | popts->wrlvl_start = pbsp_highest->wrlvl_start; | |
60 | popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; | |
61 | popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; | |
62 | } else { | |
63 | panic("DIMM is not supported by this board"); | |
64 | } | |
65 | found: | |
66 | debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" | |
67 | "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " | |
68 | "wrlvl_ctrl_3 0x%x\n", | |
69 | pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, | |
70 | pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, | |
71 | pbsp->wrlvl_ctl_3); | |
72 | ||
73 | /* | |
74 | * Factors to consider for half-strength driver enable: | |
75 | * - number of DIMMs installed | |
76 | */ | |
77 | popts->half_strength_driver_enable = 0; | |
78 | /* | |
79 | * Write leveling override | |
80 | */ | |
81 | popts->wrlvl_override = 1; | |
82 | popts->wrlvl_sample = 0xf; | |
83 | ||
84 | /* | |
85 | * Rtt and Rtt_WR override | |
86 | */ | |
87 | popts->rtt_override = 0; | |
88 | ||
89 | /* Enable ZQ calibration */ | |
90 | popts->zq_en = 1; | |
91 | ||
92 | /* DHC_EN =1, ODT = 75 Ohm */ | |
93 | popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); | |
94 | popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); | |
95 | } | |
96 | ||
97 | phys_size_t initdram(int board_type) | |
98 | { | |
99 | phys_size_t dram_size; | |
100 | ||
4d666683 | 101 | #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) |
8d67c368 | 102 | puts("Initializing....using SPD\n"); |
8d67c368 SL |
103 | dram_size = fsl_ddr_sdram(); |
104 | ||
105 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); | |
106 | dram_size *= 0x100000; | |
4d666683 SL |
107 | #else |
108 | /* DDR has been initialised by first stage boot loader */ | |
109 | dram_size = fsl_ddr_sdram_size(); | |
110 | #endif | |
8d67c368 SL |
111 | return dram_size; |
112 | } |