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ee52b188 YS |
1 | /* |
2 | * Copyright 2009-2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <command.h> | |
25 | #include <i2c.h> | |
26 | #include <netdev.h> | |
27 | #include <linux/compiler.h> | |
28 | #include <asm/mmu.h> | |
29 | #include <asm/processor.h> | |
30 | #include <asm/cache.h> | |
31 | #include <asm/immap_85xx.h> | |
32 | #include <asm/fsl_law.h> | |
33 | #include <asm/fsl_serdes.h> | |
34 | #include <asm/fsl_portals.h> | |
35 | #include <asm/fsl_liodn.h> | |
36 | #include <fm_eth.h> | |
37 | ||
38 | #include "../common/qixis.h" | |
39 | #include "../common/vsc3316_3308.h" | |
40 | #include "t4qds.h" | |
41 | #include "t4240qds_qixis.h" | |
42 | ||
43 | DECLARE_GLOBAL_DATA_PTR; | |
44 | ||
de757a7a TT |
45 | static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, |
46 | {8, 8}, {9, 9}, {14, 14}, {15, 15} }; | |
47 | ||
48 | static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, | |
49 | {10, 10}, {11, 11}, {12, 12}, {13, 13} }; | |
50 | ||
51 | static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, | |
52 | {10, 11}, {11, 10}, {12, 2}, {13, 3} }; | |
53 | ||
54 | static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, | |
55 | {8, 9}, {9, 8}, {14, 1}, {15, 0} }; | |
56 | ||
ee52b188 YS |
57 | int checkboard(void) |
58 | { | |
afa2b72b | 59 | char buf[64]; |
ee52b188 | 60 | u8 sw; |
67ac13b1 | 61 | struct cpu_type *cpu = gd->arch.cpu; |
ee52b188 YS |
62 | ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
63 | unsigned int i; | |
64 | ||
65 | printf("Board: %sQDS, ", cpu->name); | |
afa2b72b PK |
66 | printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", |
67 | QIXIS_READ(id), QIXIS_READ(arch)); | |
ee52b188 YS |
68 | |
69 | sw = QIXIS_READ(brdcfg[0]); | |
70 | sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; | |
71 | ||
72 | if (sw < 0x8) | |
73 | printf("vBank: %d\n", sw); | |
74 | else if (sw == 0x8) | |
75 | puts("Promjet\n"); | |
76 | else if (sw == 0x9) | |
77 | puts("NAND\n"); | |
78 | else | |
79 | printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); | |
80 | ||
afa2b72b PK |
81 | printf("FPGA: v%d (%s), build %d", |
82 | (int)QIXIS_READ(scver), qixis_read_tag(buf), | |
83 | (int)qixis_read_minor()); | |
84 | /* the timestamp string contains "\n" at the end */ | |
85 | printf(" on %s", qixis_read_time(buf)); | |
86 | ||
ee52b188 YS |
87 | /* Display the RCW, so that no one gets confused as to what RCW |
88 | * we're actually using for this boot. | |
89 | */ | |
90 | puts("Reset Configuration Word (RCW):"); | |
91 | for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { | |
92 | u32 rcw = in_be32(&gur->rcwsr[i]); | |
93 | ||
94 | if ((i % 4) == 0) | |
95 | printf("\n %08x:", i * 4); | |
96 | printf(" %08x", rcw); | |
97 | } | |
98 | puts("\n"); | |
99 | ||
100 | /* | |
101 | * Display the actual SERDES reference clocks as configured by the | |
102 | * dip switches on the board. Note that the SWx registers could | |
103 | * technically be set to force the reference clocks to match the | |
104 | * values that the SERDES expects (or vice versa). For now, however, | |
105 | * we just display both values and hope the user notices when they | |
106 | * don't match. | |
107 | */ | |
108 | puts("SERDES Reference Clocks: "); | |
109 | sw = QIXIS_READ(brdcfg[2]); | |
110 | for (i = 0; i < MAX_SERDES; i++) { | |
111 | static const char *freq[] = { | |
112 | "100", "125", "156.25", "161.1328125"}; | |
9458f6d8 | 113 | unsigned int clock = (sw >> (6 - 2 * i)) & 3; |
ee52b188 YS |
114 | |
115 | printf("SERDES%u=%sMHz ", i+1, freq[clock]); | |
116 | } | |
117 | puts("\n"); | |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
122 | int select_i2c_ch_pca9547(u8 ch) | |
123 | { | |
124 | int ret; | |
125 | ||
126 | ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); | |
127 | if (ret) { | |
128 | puts("PCA: failed to select proper channel\n"); | |
129 | return ret; | |
130 | } | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
135 | /* Configure Crossbar switches for Front-Side SerDes Ports */ | |
136 | int config_frontside_crossbar_vsc3316(void) | |
137 | { | |
138 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
139 | u32 srds_prtcl_s1, srds_prtcl_s2; | |
140 | int ret; | |
141 | ||
142 | ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); | |
143 | if (ret) | |
144 | return ret; | |
145 | ||
146 | srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & | |
147 | FSL_CORENET2_RCWSR4_SRDS1_PRTCL; | |
148 | srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; | |
149 | if (srds_prtcl_s1) { | |
150 | ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); | |
151 | if (ret) | |
152 | return ret; | |
153 | ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); | |
154 | if (ret) | |
155 | return ret; | |
156 | } | |
157 | ||
158 | srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & | |
159 | FSL_CORENET2_RCWSR4_SRDS2_PRTCL; | |
160 | srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; | |
161 | if (srds_prtcl_s2) { | |
162 | ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); | |
163 | if (ret) | |
164 | return ret; | |
165 | ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); | |
166 | if (ret) | |
167 | return ret; | |
168 | } | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
173 | int config_backside_crossbar_mux(void) | |
174 | { | |
175 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
176 | u32 srds_prtcl_s3, srds_prtcl_s4; | |
177 | u8 brdcfg; | |
178 | ||
179 | srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & | |
180 | FSL_CORENET2_RCWSR4_SRDS3_PRTCL; | |
181 | srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; | |
182 | switch (srds_prtcl_s3) { | |
183 | case 0: | |
184 | /* SerDes3 is not enabled */ | |
185 | break; | |
186 | case 2: | |
187 | case 9: | |
188 | case 10: | |
189 | /* SD3(0:7) => SLOT5(0:7) */ | |
190 | brdcfg = QIXIS_READ(brdcfg[12]); | |
191 | brdcfg &= ~BRDCFG12_SD3MX_MASK; | |
192 | brdcfg |= BRDCFG12_SD3MX_SLOT5; | |
193 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
194 | break; | |
195 | case 4: | |
196 | case 6: | |
197 | case 8: | |
198 | case 12: | |
199 | case 14: | |
200 | case 16: | |
201 | case 17: | |
202 | case 19: | |
203 | case 20: | |
204 | /* SD3(4:7) => SLOT6(0:3) */ | |
205 | brdcfg = QIXIS_READ(brdcfg[12]); | |
206 | brdcfg &= ~BRDCFG12_SD3MX_MASK; | |
207 | brdcfg |= BRDCFG12_SD3MX_SLOT6; | |
208 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
209 | break; | |
210 | default: | |
211 | printf("WARNING: unsupported for SerDes3 Protocol %d\n", | |
212 | srds_prtcl_s3); | |
213 | return -1; | |
214 | } | |
215 | ||
216 | srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & | |
217 | FSL_CORENET2_RCWSR4_SRDS4_PRTCL; | |
218 | srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; | |
219 | switch (srds_prtcl_s4) { | |
220 | case 0: | |
221 | /* SerDes4 is not enabled */ | |
222 | break; | |
223 | case 2: | |
224 | /* 10b, SD4(0:7) => SLOT7(0:7) */ | |
225 | brdcfg = QIXIS_READ(brdcfg[12]); | |
226 | brdcfg &= ~BRDCFG12_SD4MX_MASK; | |
227 | brdcfg |= BRDCFG12_SD4MX_SLOT7; | |
228 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
229 | break; | |
230 | case 4: | |
231 | case 6: | |
232 | case 8: | |
233 | /* x1b, SD4(4:7) => SLOT8(0:3) */ | |
234 | brdcfg = QIXIS_READ(brdcfg[12]); | |
235 | brdcfg &= ~BRDCFG12_SD4MX_MASK; | |
236 | brdcfg |= BRDCFG12_SD4MX_SLOT8; | |
237 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
238 | break; | |
239 | case 10: | |
240 | case 12: | |
241 | case 14: | |
242 | case 16: | |
243 | case 18: | |
244 | /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ | |
245 | brdcfg = QIXIS_READ(brdcfg[12]); | |
246 | brdcfg &= ~BRDCFG12_SD4MX_MASK; | |
247 | brdcfg |= BRDCFG12_SD4MX_AURO_SATA; | |
248 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
249 | break; | |
250 | default: | |
251 | printf("WARNING: unsupported for SerDes4 Protocol %d\n", | |
252 | srds_prtcl_s4); | |
253 | return -1; | |
254 | } | |
255 | ||
256 | return 0; | |
257 | } | |
258 | ||
259 | int board_early_init_r(void) | |
260 | { | |
261 | const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; | |
262 | const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); | |
263 | ||
264 | /* | |
265 | * Remap Boot flash + PROMJET region to caching-inhibited | |
266 | * so that flash can be erased properly. | |
267 | */ | |
268 | ||
269 | /* Flush d-cache and invalidate i-cache of any FLASH data */ | |
270 | flush_dcache(); | |
271 | invalidate_icache(); | |
272 | ||
273 | /* invalidate existing TLB entry for flash + promjet */ | |
274 | disable_tlb(flash_esel); | |
275 | ||
276 | set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, | |
277 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, | |
278 | 0, flash_esel, BOOKE_PAGESZ_256M, 1); | |
279 | ||
280 | set_liodns(); | |
281 | #ifdef CONFIG_SYS_DPAA_QBMAN | |
282 | setup_portals(); | |
283 | #endif | |
284 | ||
285 | /* Disable remote I2C connectoin */ | |
286 | QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET); | |
287 | ||
288 | /* Configure board SERDES ports crossbar */ | |
289 | config_frontside_crossbar_vsc3316(); | |
290 | config_backside_crossbar_mux(); | |
291 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | unsigned long get_board_sys_clk(void) | |
297 | { | |
298 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); | |
299 | ||
300 | switch (sysclk_conf & 0x0F) { | |
301 | case QIXIS_SYSCLK_83: | |
302 | return 83333333; | |
303 | case QIXIS_SYSCLK_100: | |
304 | return 100000000; | |
305 | case QIXIS_SYSCLK_125: | |
306 | return 125000000; | |
307 | case QIXIS_SYSCLK_133: | |
308 | return 133333333; | |
309 | case QIXIS_SYSCLK_150: | |
310 | return 150000000; | |
311 | case QIXIS_SYSCLK_160: | |
312 | return 160000000; | |
313 | case QIXIS_SYSCLK_166: | |
314 | return 166666666; | |
315 | } | |
316 | return 66666666; | |
317 | } | |
318 | ||
319 | unsigned long get_board_ddr_clk(void) | |
320 | { | |
321 | u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); | |
322 | ||
323 | switch ((ddrclk_conf & 0x30) >> 4) { | |
324 | case QIXIS_DDRCLK_100: | |
325 | return 100000000; | |
326 | case QIXIS_DDRCLK_125: | |
327 | return 125000000; | |
328 | case QIXIS_DDRCLK_133: | |
329 | return 133333333; | |
330 | } | |
331 | return 66666666; | |
332 | } | |
333 | ||
334 | static const char *serdes_clock_to_string(u32 clock) | |
335 | { | |
336 | switch (clock) { | |
337 | case SRDS_PLLCR0_RFCK_SEL_100: | |
338 | return "100"; | |
339 | case SRDS_PLLCR0_RFCK_SEL_125: | |
340 | return "125"; | |
341 | case SRDS_PLLCR0_RFCK_SEL_156_25: | |
342 | return "156.25"; | |
343 | case SRDS_PLLCR0_RFCK_SEL_161_13: | |
344 | return "161.1328125"; | |
345 | default: | |
346 | return "???"; | |
347 | } | |
348 | } | |
349 | ||
350 | int misc_init_r(void) | |
351 | { | |
352 | u8 sw; | |
353 | serdes_corenet_t *srds_regs = | |
354 | (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; | |
355 | u32 actual[MAX_SERDES]; | |
356 | unsigned int i; | |
357 | ||
358 | sw = QIXIS_READ(brdcfg[2]); | |
359 | for (i = 0; i < MAX_SERDES; i++) { | |
9458f6d8 | 360 | unsigned int clock = (sw >> (6 - 2 * i)) & 3; |
ee52b188 YS |
361 | switch (clock) { |
362 | case 0: | |
363 | actual[i] = SRDS_PLLCR0_RFCK_SEL_100; | |
364 | break; | |
365 | case 1: | |
366 | actual[i] = SRDS_PLLCR0_RFCK_SEL_125; | |
367 | break; | |
368 | case 2: | |
369 | actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; | |
370 | break; | |
371 | case 3: | |
372 | actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; | |
373 | break; | |
374 | } | |
375 | } | |
376 | ||
377 | for (i = 0; i < MAX_SERDES; i++) { | |
378 | u32 pllcr0 = srds_regs->bank[i].pllcr0; | |
379 | u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; | |
380 | if (expected != actual[i]) { | |
381 | printf("Warning: SERDES%u expects reference clock" | |
382 | " %sMHz, but actual is %sMHz\n", i + 1, | |
383 | serdes_clock_to_string(expected), | |
384 | serdes_clock_to_string(actual[i])); | |
385 | } | |
386 | } | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | void ft_board_setup(void *blob, bd_t *bd) | |
392 | { | |
393 | phys_addr_t base; | |
394 | phys_size_t size; | |
395 | ||
396 | ft_cpu_setup(blob, bd); | |
397 | ||
398 | base = getenv_bootm_low(); | |
399 | size = getenv_bootm_size(); | |
400 | ||
401 | fdt_fixup_memory(blob, (u64)base, (u64)size); | |
402 | ||
403 | #ifdef CONFIG_PCI | |
404 | pci_of_setup(blob, bd); | |
405 | #endif | |
406 | ||
407 | fdt_fixup_liodn(blob); | |
408 | fdt_fixup_dr_usb(blob, bd); | |
409 | ||
410 | #ifdef CONFIG_SYS_DPAA_FMAN | |
411 | fdt_fixup_fman_ethernet(blob); | |
412 | fdt_fixup_board_enet(blob); | |
413 | #endif | |
414 | } | |
4457e3e6 SL |
415 | |
416 | /* | |
417 | * Reverse engineering switch settings. | |
418 | * Some bits cannot be figured out. They will be displayed as | |
419 | * underscore in binary format. mask[] has those bits. | |
420 | * Some bits are calculated differently than the actual switches | |
421 | * if booting with overriding by FPGA. | |
422 | */ | |
423 | void qixis_dump_switch(void) | |
424 | { | |
425 | int i; | |
426 | u8 sw[9]; | |
427 | ||
428 | /* | |
429 | * Any bit with 1 means that bit cannot be reverse engineered. | |
430 | * It will be displayed as _ in binary format. | |
431 | */ | |
432 | static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f}; | |
433 | char buf[10]; | |
434 | u8 brdcfg[16], dutcfg[16]; | |
435 | ||
436 | for (i = 0; i < 16; i++) { | |
437 | brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); | |
438 | dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); | |
439 | } | |
440 | ||
441 | sw[0] = dutcfg[0]; | |
442 | sw[1] = (dutcfg[1] << 0x07) | \ | |
443 | ((dutcfg[12] & 0xC0) >> 1) | \ | |
444 | ((dutcfg[11] & 0xE0) >> 3) | \ | |
445 | ((dutcfg[6] & 0x80) >> 6) | \ | |
446 | ((dutcfg[1] & 0x80) >> 7); | |
447 | sw[2] = ((brdcfg[1] & 0x0f) << 4) | \ | |
448 | ((brdcfg[1] & 0x30) >> 2) | \ | |
449 | ((brdcfg[1] & 0x40) >> 5) | \ | |
450 | ((brdcfg[1] & 0x80) >> 7); | |
451 | sw[3] = brdcfg[2]; | |
452 | sw[4] = ((dutcfg[2] & 0x01) << 7) | \ | |
453 | ((dutcfg[2] & 0x06) << 4) | \ | |
454 | ((~QIXIS_READ(present)) & 0x10) | \ | |
455 | ((brdcfg[3] & 0x80) >> 4) | \ | |
456 | ((brdcfg[3] & 0x01) << 2) | \ | |
457 | ((brdcfg[6] == 0x62) ? 3 : \ | |
458 | ((brdcfg[6] == 0x5a) ? 2 : \ | |
459 | ((brdcfg[6] == 0x5e) ? 1 : 0))); | |
460 | sw[5] = ((brdcfg[0] & 0x0f) << 4) | \ | |
461 | ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \ | |
462 | ((brdcfg[0] & 0x40) >> 5); | |
463 | sw[6] = (brdcfg[11] & 0x20); | |
464 | sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \ | |
465 | ((brdcfg[5] & 0x10) << 2); | |
466 | sw[8] = ((brdcfg[12] & 0x08) << 4) | \ | |
467 | ((brdcfg[12] & 0x03) << 5); | |
468 | ||
469 | puts("DIP switch (reverse-engineering)\n"); | |
470 | for (i = 0; i < 9; i++) { | |
471 | printf("SW%d = 0b%s (0x%02x)\n", | |
472 | i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); | |
473 | } | |
474 | } |