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1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Author: Chunhe Lan <Chunhe.Lan@freescale.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
24b852a7 | 10 | #include <console.h> |
203e94f6 | 11 | #include <environment.h> |
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12 | #include <asm/spl.h> |
13 | #include <malloc.h> | |
14 | #include <ns16550.h> | |
15 | #include <nand.h> | |
16 | #include <mmc.h> | |
17 | #include <fsl_esdhc.h> | |
18 | #include <i2c.h> | |
19 | ||
20 | #include "t4rdb.h" | |
21 | ||
22 | #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 | |
23 | ||
24 | DECLARE_GLOBAL_DATA_PTR; | |
25 | ||
26 | phys_size_t get_effective_memsize(void) | |
27 | { | |
28 | return CONFIG_SYS_L3_SIZE; | |
29 | } | |
30 | ||
31 | unsigned long get_board_sys_clk(void) | |
32 | { | |
33 | return CONFIG_SYS_CLK_FREQ; | |
34 | } | |
35 | ||
36 | unsigned long get_board_ddr_clk(void) | |
37 | { | |
38 | return CONFIG_DDR_CLK_FREQ; | |
39 | } | |
40 | ||
41 | void board_init_f(ulong bootflag) | |
42 | { | |
43 | u32 plat_ratio, sys_clk, ccb_clk; | |
44 | ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; | |
45 | ||
46 | /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ | |
47 | memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); | |
48 | ||
49 | /* Update GD pointer */ | |
50 | gd = (gd_t *)(CONFIG_SPL_GD_ADDR); | |
51 | ||
52 | /* compiler optimization barrier needed for GCC >= 3.4 */ | |
53 | __asm__ __volatile__("" : : : "memory"); | |
54 | ||
55 | console_init_f(); | |
56 | ||
57 | /* initialize selected port with appropriate baud rate */ | |
58 | sys_clk = get_board_sys_clk(); | |
59 | plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; | |
60 | ccb_clk = sys_clk * plat_ratio / 2; | |
61 | ||
62 | NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, | |
63 | ccb_clk / 16 / CONFIG_BAUDRATE); | |
64 | ||
65 | puts("\nSD boot...\n"); | |
66 | ||
67 | relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); | |
68 | } | |
69 | ||
70 | void board_init_r(gd_t *gd, ulong dest_addr) | |
71 | { | |
72 | bd_t *bd; | |
73 | ||
74 | bd = (bd_t *)(gd + sizeof(gd_t)); | |
75 | memset(bd, 0, sizeof(bd_t)); | |
76 | gd->bd = bd; | |
77 | bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; | |
78 | bd->bi_memsize = CONFIG_SYS_L3_SIZE; | |
79 | ||
cbcbf71b | 80 | arch_cpu_init(); |
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81 | get_clocks(); |
82 | mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, | |
83 | CONFIG_SPL_RELOC_MALLOC_SIZE); | |
ed4708aa | 84 | gd->flags |= GD_FLG_FULL_MALLOC_INIT; |
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85 | |
86 | mmc_initialize(bd); | |
87 | mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, | |
88 | (uchar *)CONFIG_ENV_ADDR); | |
89 | ||
90 | gd->env_addr = (ulong)(CONFIG_ENV_ADDR); | |
203e94f6 | 91 | gd->env_valid = ENV_VALID; |
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92 | |
93 | i2c_init_all(); | |
94 | ||
f1683aa7 | 95 | dram_init(); |
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96 | |
97 | mmc_boot(); | |
98 | } |