[people/ms/u-boot.git] / board / gaisler / gr_ep2s60 / u-boot.lds

/* Linker script for Gaisler Research AB's Template design
 * for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
 *
 * (C) Copyright 2008
 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
OUTPUT_ARCH(sparc)
ENTRY(_start)
SECTIONS
{

/* Read-only sections, merged into text segment: */
	. = + SIZEOF_HEADERS;
	.interp : { *(.interp) }
	.hash          : { *(.hash)		}
	.dynsym        : { *(.dynsym)		}
	.dynstr        : { *(.dynstr)		}
	.rel.text      : { *(.rel.text)		}
	.rela.text     : { *(.rela.text)	}
	.rel.data      : { *(.rel.data)		}
	.rela.data     : { *(.rela.data)	}
	.rel.rodata    : { *(.rel.rodata)	}
	.rela.rodata   : { *(.rela.rodata)	}
	.rel.got       : { *(.rel.got)		}
	.rela.got      : { *(.rela.got)		}
	.rel.ctors     : { *(.rel.ctors)	}
	.rela.ctors    : { *(.rela.ctors)	}
	.rel.dtors     : { *(.rel.dtors)	}
	.rela.dtors    : { *(.rela.dtors)	}
	.rel.bss       : { *(.rel.bss)		}
	.rela.bss      : { *(.rela.bss)		}
	.rel.plt       : { *(.rel.plt)		}
	.rela.plt      : { *(.rela.plt)		}
	.init          : { *(.init)		}
	.plt : { *(.plt) }

	.text : {
		_load_addr = .;
		_text = .;

		*(.start)
		arch/sparc/cpu/leon3/start.o (.text)
/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
		. = ALIGN(8192);
/* PROM CODE, Will be relocated to the end of memory,
 * no global data accesses please.
 */
		__prom_start = .;
		*(.prom.pgt)
		*(.prom.data)
		*(.prom.text)
		. = ALIGN(16);
		__prom_end = .;
		*(.text)
		*(.fixup)
		*(.gnu.warning)
/*		*(.got1)*/
		. = ALIGN(16);
		*(.eh_frame)
		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
	}
	. = ALIGN(4);
	_etext = .;

	/* CMD Table */

	__u_boot_cmd_start = .;
	.u_boot_cmd : { *(.u_boot_cmd) }
	. = ALIGN(4);
	__u_boot_cmd_end = .;

	. = ALIGN(4);
	.u_boot_list : {
	#include <u-boot.lst>
	}

	.data	:
	{
		*(.data)
		*(.data1)
		*(.data.rel)
		*(.data.rel.*)
		*(.sdata)
		*(.sdata2)
		*(.dynamic)
		CONSTRUCTORS
	}
	_edata	=	.;
	PROVIDE (edata = .);

	. = ALIGN(4);
	__got_start = .;
	.got : {
		*(.got)
/*		*(.data.rel)
		*(.data.rel.local)*/
		. = ALIGN(16);
	}
	__got_end = .;

/*	.data.rel : { } */

	. = ALIGN(4096);
	__init_begin = .;
	.text.init : { *(.text.init) }
	.data.init : { *(.data.init) }
	. = ALIGN(4096);
	__init_end = .;

	__bss_start = .;
	.bss		:
	{
	 *(.sbss) *(.scommon)
	 *(.dynbss)
	 *(.bss)
	 *(COMMON)
	. = ALIGN(16); /* to speed clearing of bss up */
	}
	__bss_end = . ;
	__bss_end__ = . ;
	PROVIDE (end = .);

/* Relocated into main memory */

	/* Start of main memory */
	/*. = 0x40000000;*/

	.stack (NOLOAD)	: { *(.stack) }

	/* PROM CODE */

	/* global data in RAM passed to kernel after booting */

  .stab 0		: { *(.stab) }
  .stabstr 0		: { *(.stabstr) }
  .stab.excl 0		: { *(.stab.excl) }
  .stab.exclstr 0	: { *(.stab.exclstr) }
  .stab.index 0		: { *(.stab.index) }
  .stab.indexstr 0	: { *(.stab.indexstr) }
  .comment 0		: { *(.comment) }

}
Commit	Line	Data
6940383d DH	1	/* Linker script for Gaisler Research AB's Template design
	2	* for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
	3	*
	4	* (C) Copyright 2008
	5	* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*
	25	*/
	26
	27	OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
	28	OUTPUT_ARCH(sparc)
	29	ENTRY(_start)
	30	SECTIONS
	31	{
	32
	33	/* Read-only sections, merged into text segment: */
	34	. = + SIZEOF_HEADERS;
	35	.interp : { *(.interp) }
	36	.hash : { *(.hash) }
	37	.dynsym : { *(.dynsym) }
	38	.dynstr : { *(.dynstr) }
	39	.rel.text : { *(.rel.text) }
	40	.rela.text : { *(.rela.text) }
	41	.rel.data : { *(.rel.data) }
	42	.rela.data : { *(.rela.data) }
	43	.rel.rodata : { *(.rel.rodata) }
	44	.rela.rodata : { *(.rela.rodata) }
	45	.rel.got : { *(.rel.got) }
	46	.rela.got : { *(.rela.got) }
	47	.rel.ctors : { *(.rel.ctors) }
	48	.rela.ctors : { *(.rela.ctors) }
	49	.rel.dtors : { *(.rel.dtors) }
	50	.rela.dtors : { *(.rela.dtors) }
	51	.rel.bss : { *(.rel.bss) }
	52	.rela.bss : { *(.rela.bss) }
	53	.rel.plt : { *(.rel.plt) }
	54	.rela.plt : { *(.rela.plt) }
	55	.init : { *(.init) }
	56	.plt : { *(.plt) }
	57
	58	.text : {
	59	_load_addr = .;
	60	_text = .;
	61
	62	*(.start)
1e9c2657	63	arch/sparc/cpu/leon3/start.o (.text)
6d0f6bcf	64	/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
6940383d DH	65	. = ALIGN(8192);
	66	/* PROM CODE, Will be relocated to the end of memory,
	67	* no global data accesses please.
	68	*/
	69	__prom_start = .;
	70	*(.prom.pgt)
	71	*(.prom.data)
	72	*(.prom.text)
	73	. = ALIGN(16);
	74	__prom_end = .;
	75	*(.text)
	76	*(.fixup)
	77	*(.gnu.warning)
	78	/* (.got1)/
	79	. = ALIGN(16);
6940383d	80	*(.eh_frame)
f62fb999	81	(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata)))
6940383d DH	82	}
	83	. = ALIGN(4);
	84	_etext = .;
	85
	86	/* CMD Table */
	87
	88	__u_boot_cmd_start = .;
	89	.u_boot_cmd : { *(.u_boot_cmd) }
	90	. = ALIGN(4);
	91	__u_boot_cmd_end = .;
	92
55675142 MV	93	. = ALIGN(4);
	94	.u_boot_list : {
	95	#include <u-boot.lst>
	96	}
	97
6940383d DH	98	.data :
	99	{
	100	*(.data)
	101	*(.data1)
	102	*(.data.rel)
	103	(.data.rel.)
	104	*(.sdata)
	105	*(.sdata2)
	106	*(.dynamic)
	107	CONSTRUCTORS
	108	}
	109	_edata = .;
	110	PROVIDE (edata = .);
	111
	112	. = ALIGN(4);
	113	__got_start = .;
	114	.got : {
	115	*(.got)
	116	/* *(.data.rel)
	117	(.data.rel.local)/
	118	. = ALIGN(16);
	119	}
	120	__got_end = .;
	121
	122	/* .data.rel : { } */
	123
	124	. = ALIGN(4096);
	125	__init_begin = .;
	126	.text.init : { *(.text.init) }
	127	.data.init : { *(.data.init) }
	128	. = ALIGN(4096);
	129	__init_end = .;
	130
	131	__bss_start = .;
	132	.bss :
	133	{
	134	(.sbss) (.scommon)
	135	*(.dynbss)
	136	*(.bss)
	137	*(COMMON)
	138	. = ALIGN(16); /* to speed clearing of bss up */
	139	}
	140	__bss_end = . ;
44c6e659	141	__bss_end__ = . ;
6940383d DH	142	PROVIDE (end = .);
	143
	144	/* Relocated into main memory */
	145
	146	/* Start of main memory */
	147	/. = 0x40000000;/
	148
	149	.stack (NOLOAD) : { *(.stack) }
	150
	151	/* PROM CODE */
	152
	153	/* global data in RAM passed to kernel after booting */
	154
	155	.stab 0 : { *(.stab) }
	156	.stabstr 0 : { *(.stabstr) }
	157	.stab.excl 0 : { *(.stab.excl) }
	158	.stab.exclstr 0 : { *(.stab.exclstr) }
	159	.stab.index 0 : { *(.stab.index) }
	160	.stab.indexstr 0 : { *(.stab.indexstr) }
	161	.comment 0 : { *(.comment) }
	162
	163	}