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e56c5791 TH |
1 | /* |
2 | * Copyright (C) 2013 Gateworks Corporation | |
3 | * | |
4 | * Author: Tim Harvey <tharvey@gateworks.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
65da5c3b | 9 | #include <asm/arch/clock.h> |
e56c5791 TH |
10 | #include <asm/arch/mx6-pins.h> |
11 | #include <asm/arch/sys_proto.h> | |
12 | #include <asm/gpio.h> | |
552a848e | 13 | #include <asm/mach-imx/mxc_i2c.h> |
65da5c3b | 14 | #include <fsl_esdhc.h> |
e56c5791 TH |
15 | #include <hwconfig.h> |
16 | #include <power/pmic.h> | |
17 | #include <power/ltc3676_pmic.h> | |
18 | #include <power/pfuze100_pmic.h> | |
19 | ||
20 | #include "common.h" | |
21 | ||
22 | /* UART1: Function varies per baseboard */ | |
23 | static iomux_v3_cfg_t const uart1_pads[] = { | |
24 | IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
25 | IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
26 | }; | |
27 | ||
28 | /* UART2: Serial Console */ | |
29 | static iomux_v3_cfg_t const uart2_pads[] = { | |
30 | IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
31 | IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
32 | }; | |
33 | ||
34 | void setup_iomux_uart(void) | |
35 | { | |
36 | SETUP_IOMUX_PADS(uart1_pads); | |
37 | SETUP_IOMUX_PADS(uart2_pads); | |
38 | } | |
39 | ||
65da5c3b | 40 | /* MMC */ |
8d1a6ff8 TH |
41 | static iomux_v3_cfg_t const gw5904_emmc_pads[] = { |
42 | IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
43 | IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
44 | IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
45 | IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
46 | IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
47 | IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
48 | IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
49 | IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
50 | IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
51 | IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
52 | IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
53 | }; | |
214fb19b TH |
54 | /* 4-bit microSD on SD2 */ |
55 | static iomux_v3_cfg_t const gw5904_mmc_pads[] = { | |
56 | IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
57 | IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
58 | IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
59 | IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
60 | IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
61 | IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
62 | /* CD */ | |
63 | IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
64 | }; | |
94a1d6c6 TH |
65 | /* 8-bit eMMC on SD2/NAND */ |
66 | static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = { | |
67 | IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
68 | IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
69 | IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
70 | IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
71 | IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
72 | IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
73 | IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
74 | IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
75 | IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
76 | IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
77 | }; | |
78 | ||
65da5c3b TH |
79 | static iomux_v3_cfg_t const usdhc3_pads[] = { |
80 | IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
81 | IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
82 | IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
83 | IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
84 | IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
85 | IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
86 | IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
87 | }; | |
88 | ||
e56c5791 TH |
89 | /* I2C1: GSC */ |
90 | static struct i2c_pads_info mx6q_i2c_pad_info0 = { | |
91 | .scl = { | |
92 | .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, | |
93 | .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, | |
94 | .gp = IMX_GPIO_NR(3, 21) | |
95 | }, | |
96 | .sda = { | |
97 | .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, | |
98 | .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, | |
99 | .gp = IMX_GPIO_NR(3, 28) | |
100 | } | |
101 | }; | |
102 | static struct i2c_pads_info mx6dl_i2c_pad_info0 = { | |
103 | .scl = { | |
104 | .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, | |
105 | .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, | |
106 | .gp = IMX_GPIO_NR(3, 21) | |
107 | }, | |
108 | .sda = { | |
109 | .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, | |
110 | .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, | |
111 | .gp = IMX_GPIO_NR(3, 28) | |
112 | } | |
113 | }; | |
114 | ||
115 | /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ | |
116 | static struct i2c_pads_info mx6q_i2c_pad_info1 = { | |
117 | .scl = { | |
118 | .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, | |
119 | .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, | |
120 | .gp = IMX_GPIO_NR(4, 12) | |
121 | }, | |
122 | .sda = { | |
123 | .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, | |
124 | .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, | |
125 | .gp = IMX_GPIO_NR(4, 13) | |
126 | } | |
127 | }; | |
128 | static struct i2c_pads_info mx6dl_i2c_pad_info1 = { | |
129 | .scl = { | |
130 | .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, | |
131 | .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, | |
132 | .gp = IMX_GPIO_NR(4, 12) | |
133 | }, | |
134 | .sda = { | |
135 | .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, | |
136 | .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, | |
137 | .gp = IMX_GPIO_NR(4, 13) | |
138 | } | |
139 | }; | |
140 | ||
141 | /* I2C3: Misc/Expansion */ | |
142 | static struct i2c_pads_info mx6q_i2c_pad_info2 = { | |
143 | .scl = { | |
144 | .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, | |
145 | .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, | |
146 | .gp = IMX_GPIO_NR(1, 3) | |
147 | }, | |
148 | .sda = { | |
149 | .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, | |
150 | .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, | |
151 | .gp = IMX_GPIO_NR(1, 6) | |
152 | } | |
153 | }; | |
154 | static struct i2c_pads_info mx6dl_i2c_pad_info2 = { | |
155 | .scl = { | |
156 | .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, | |
157 | .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, | |
158 | .gp = IMX_GPIO_NR(1, 3) | |
159 | }, | |
160 | .sda = { | |
161 | .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, | |
162 | .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, | |
163 | .gp = IMX_GPIO_NR(1, 6) | |
164 | } | |
165 | }; | |
166 | ||
167 | void setup_ventana_i2c(void) | |
168 | { | |
169 | if (is_cpu_type(MXC_CPU_MX6Q)) { | |
170 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); | |
171 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); | |
172 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); | |
173 | } else { | |
174 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); | |
175 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); | |
176 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); | |
177 | } | |
178 | } | |
179 | ||
180 | /* | |
181 | * Baseboard specific GPIO | |
182 | */ | |
e56c5791 TH |
183 | static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { |
184 | /* PANLEDG# */ | |
185 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
186 | /* PANLEDR# */ | |
187 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
188 | /* IOEXP_PWREN# */ | |
189 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
190 | /* IOEXP_IRQ# */ | |
191 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
192 | ||
193 | /* GPS_SHDN */ | |
194 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
195 | /* VID_PWR */ | |
196 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
197 | /* PCI_RST# */ | |
198 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
199 | /* PCIESKT_WDIS# */ | |
200 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
201 | }; | |
202 | ||
203 | static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { | |
f3a8546b TH |
204 | /* SD3_VSELECT */ |
205 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
e49621b3 TH |
206 | /* RS232_EN# */ |
207 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
5c55572f TH |
208 | /* MSATA_EN */ |
209 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
e56c5791 TH |
210 | /* PANLEDG# */ |
211 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
212 | /* PANLEDR# */ | |
213 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
214 | /* IOEXP_PWREN# */ | |
215 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
216 | /* IOEXP_IRQ# */ | |
217 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
9a83a815 TH |
218 | /* CAN_STBY */ |
219 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
220 | /* MX6_LOCLED# */ |
221 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
222 | /* GPS_SHDN */ | |
223 | IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), | |
224 | /* USBOTG_SEL */ | |
225 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
226 | /* VID_PWR */ | |
227 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
228 | /* PCI_RST# */ | |
229 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
230 | /* PCI_RST# (GW522x) */ | |
231 | IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), | |
9a83a815 TH |
232 | /* RS485_EN */ |
233 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
234 | /* PCIESKT_WDIS# */ |
235 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
236 | }; | |
237 | ||
238 | static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { | |
f3a8546b TH |
239 | /* SD3_VSELECT */ |
240 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
e49621b3 TH |
241 | /* RS232_EN# */ |
242 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
5c55572f TH |
243 | /* MSATA_EN */ |
244 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
9a83a815 TH |
245 | /* CAN_STBY */ |
246 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
247 | /* USB_HUBRST# */ | |
248 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
249 | /* PANLEDG# */ |
250 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
251 | /* PANLEDR# */ | |
252 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
253 | /* MX6_LOCLED# */ | |
254 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
255 | /* IOEXP_PWREN# */ | |
256 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
257 | /* IOEXP_IRQ# */ | |
258 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
259 | /* DIOI2C_DIS# */ | |
260 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
261 | /* GPS_SHDN */ | |
262 | IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), | |
263 | /* VID_EN */ | |
264 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
265 | /* PCI_RST# */ | |
266 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
9a83a815 TH |
267 | /* RS485_EN */ |
268 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
269 | /* PCIESKT_WDIS# */ |
270 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
271 | }; | |
272 | ||
273 | static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { | |
f3a8546b TH |
274 | /* SD3_VSELECT */ |
275 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
e49621b3 TH |
276 | /* RS232_EN# */ |
277 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
5c55572f TH |
278 | /* MSATA_EN */ |
279 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
9a83a815 TH |
280 | /* CAN_STBY */ |
281 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
e56c5791 TH |
282 | /* PANLEDG# */ |
283 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
284 | /* PANLEDR# */ | |
9a83a815 | 285 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
e56c5791 TH |
286 | /* MX6_LOCLED# */ |
287 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
9a83a815 TH |
288 | /* USB_HUBRST# */ |
289 | IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG), | |
e56c5791 TH |
290 | /* MIPI_DIO */ |
291 | IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), | |
292 | /* RS485_EN */ | |
293 | IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), | |
294 | /* IOEXP_PWREN# */ | |
9a83a815 | 295 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), |
e56c5791 | 296 | /* IOEXP_IRQ# */ |
9a83a815 | 297 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
e56c5791 TH |
298 | /* DIOI2C_DIS# */ |
299 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
300 | /* PCI_RST# */ | |
301 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
302 | /* VID_EN */ | |
303 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
9a83a815 TH |
304 | /* RS485_EN */ |
305 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
306 | /* PCIESKT_WDIS# */ |
307 | IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), | |
308 | }; | |
309 | ||
310 | static iomux_v3_cfg_t const gw551x_gpio_pads[] = { | |
9a83a815 TH |
311 | /* CAN_STBY */ |
312 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
313 | /* PANLED# */ |
314 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
315 | /* PCI_RST# */ | |
316 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
317 | /* PCIESKT_WDIS# */ | |
318 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
319 | }; | |
320 | ||
321 | static iomux_v3_cfg_t const gw552x_gpio_pads[] = { | |
5c55572f TH |
322 | /* MSATA_EN */ |
323 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
9a83a815 TH |
324 | /* USBOTG_SEL */ |
325 | IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), | |
326 | /* USB_HUBRST# */ | |
327 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
328 | /* PANLEDG# */ |
329 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
330 | /* PANLEDR# */ | |
331 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
332 | /* MX6_LOCLED# */ | |
333 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
334 | /* PCI_RST# */ | |
335 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
336 | /* MX6_DIO[4:9] */ | |
337 | IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), | |
338 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
339 | IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), | |
340 | IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), | |
341 | IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), | |
342 | IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), | |
343 | /* PCIEGBE1_OFF# */ | |
344 | IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), | |
345 | /* PCIEGBE2_OFF# */ | |
346 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
347 | /* PCIESKT_WDIS# */ | |
348 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
349 | }; | |
350 | ||
385575bc | 351 | static iomux_v3_cfg_t const gw553x_gpio_pads[] = { |
f3a8546b TH |
352 | /* SD3_VSELECT */ |
353 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
385575bc TH |
354 | /* PANLEDG# */ |
355 | IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), | |
356 | /* PANLEDR# */ | |
357 | IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG), | |
385575bc TH |
358 | /* VID_PWR */ |
359 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
360 | /* PCI_RST# */ | |
361 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
362 | /* PCIESKT_WDIS# */ | |
363 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
364 | }; | |
365 | ||
94a1d6c6 TH |
366 | static iomux_v3_cfg_t const gw560x_gpio_pads[] = { |
367 | /* RS232_EN# */ | |
368 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
369 | /* CAN_STBY */ | |
370 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
371 | /* USB_HUBRST# */ | |
372 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
373 | /* PANLEDG# */ | |
374 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
375 | /* PANLEDR# */ | |
376 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
377 | /* MX6_LOCLED# */ | |
378 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
379 | /* IOEXP_PWREN# */ | |
380 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
381 | /* IOEXP_IRQ# */ | |
382 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
383 | /* DIOI2C_DIS# */ | |
384 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
385 | /* VID_EN */ | |
386 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
387 | /* PCI_RST# */ | |
388 | IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG), | |
389 | /* RS485_EN */ | |
390 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
391 | /* PCIESKT_WDIS# */ | |
392 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
393 | /* USBH2_PEN (OTG) */ | |
394 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
395 | /* 12V0_PWR_EN */ | |
396 | IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG), | |
397 | }; | |
398 | ||
214fb19b TH |
399 | static iomux_v3_cfg_t const gw5903_gpio_pads[] = { |
400 | /* BKLT_12VEN */ | |
401 | IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), | |
402 | /* EMMY_PDN# */ | |
403 | IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG), | |
404 | /* EMMY_CFG1# */ | |
405 | IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG), | |
406 | /* EMMY_CFG1# */ | |
407 | IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG), | |
408 | /* USBH1_PEN (EHCI) */ | |
409 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
410 | /* USBH2_PEN (OTG) */ | |
411 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
412 | /* USBDPC_PEN */ | |
413 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
414 | /* TOUCH_RST */ | |
415 | IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG), | |
416 | /* AUDIO_RST# */ | |
417 | IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), | |
418 | /* UART1_TEN# */ | |
419 | IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG), | |
420 | /* MX6_LOCLED# */ | |
421 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
422 | /* LVDS_BKLEN # */ | |
423 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
424 | /* RGMII_PDWN# */ | |
425 | IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG), | |
426 | /* TOUCH_IRQ# */ | |
427 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
428 | /* TOUCH_RST# */ | |
429 | IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG), | |
430 | }; | |
431 | ||
8d1a6ff8 TH |
432 | static iomux_v3_cfg_t const gw5904_gpio_pads[] = { |
433 | /* USB_HUBRST# */ | |
434 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
435 | /* PANLEDG# */ | |
436 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
437 | /* PANLEDR# */ | |
438 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
439 | /* MX6_LOCLED# */ | |
440 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
441 | /* IOEXP_PWREN# */ | |
442 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
443 | /* IOEXP_IRQ# */ | |
444 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
445 | /* DIOI2C_DIS# */ | |
446 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
447 | /* UART_RS485 */ | |
448 | IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG), | |
449 | /* UART_HALF */ | |
450 | IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG), | |
451 | /* SKT1_WDIS# */ | |
452 | IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG), | |
453 | /* SKT1_RST# */ | |
454 | IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG), | |
455 | /* SKT2_WDIS# */ | |
456 | IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG), | |
457 | /* SKT2_RST# */ | |
458 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
459 | /* M2_OFF# */ | |
460 | IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG), | |
461 | /* M2_WDIS# */ | |
462 | IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG), | |
463 | /* M2_RST# */ | |
464 | IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG), | |
465 | }; | |
466 | ||
1800ffa8 TH |
467 | /* Digital I/O */ |
468 | struct dio_cfg gw51xx_dio[] = { | |
469 | { | |
470 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
471 | IMX_GPIO_NR(1, 16), | |
472 | { 0, 0 }, | |
473 | 0 | |
474 | }, | |
475 | { | |
476 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
477 | IMX_GPIO_NR(1, 19), | |
478 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
479 | 2 | |
480 | }, | |
481 | { | |
482 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
483 | IMX_GPIO_NR(1, 17), | |
484 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
485 | 3 | |
486 | }, | |
487 | { | |
488 | { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, | |
489 | IMX_GPIO_NR(1, 18), | |
490 | { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, | |
491 | 4 | |
492 | }, | |
493 | }; | |
494 | ||
495 | struct dio_cfg gw52xx_dio[] = { | |
496 | { | |
497 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
498 | IMX_GPIO_NR(1, 16), | |
499 | { 0, 0 }, | |
500 | 0 | |
501 | }, | |
502 | { | |
503 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
504 | IMX_GPIO_NR(1, 19), | |
505 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
506 | 2 | |
507 | }, | |
508 | { | |
509 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
510 | IMX_GPIO_NR(1, 17), | |
511 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
512 | 3 | |
513 | }, | |
514 | { | |
515 | { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
516 | IMX_GPIO_NR(1, 20), | |
517 | { 0, 0 }, | |
518 | 0 | |
519 | }, | |
520 | }; | |
521 | ||
522 | struct dio_cfg gw53xx_dio[] = { | |
523 | { | |
524 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
525 | IMX_GPIO_NR(1, 16), | |
526 | { 0, 0 }, | |
527 | 0 | |
528 | }, | |
529 | { | |
530 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
531 | IMX_GPIO_NR(1, 19), | |
532 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
533 | 2 | |
534 | }, | |
535 | { | |
536 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
537 | IMX_GPIO_NR(1, 17), | |
538 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
539 | 3 | |
540 | }, | |
541 | { | |
542 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
543 | IMX_GPIO_NR(1, 20), | |
544 | { 0, 0 }, | |
545 | 0 | |
546 | }, | |
547 | }; | |
548 | ||
549 | struct dio_cfg gw54xx_dio[] = { | |
550 | { | |
551 | { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, | |
552 | IMX_GPIO_NR(1, 9), | |
553 | { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, | |
554 | 1 | |
555 | }, | |
556 | { | |
557 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
558 | IMX_GPIO_NR(1, 19), | |
559 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
560 | 2 | |
561 | }, | |
562 | { | |
563 | { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, | |
564 | IMX_GPIO_NR(2, 9), | |
565 | { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, | |
566 | 3 | |
567 | }, | |
568 | { | |
569 | { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, | |
570 | IMX_GPIO_NR(2, 10), | |
571 | { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, | |
572 | 4 | |
573 | }, | |
574 | }; | |
575 | ||
576 | struct dio_cfg gw551x_dio[] = { | |
577 | { | |
578 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
579 | IMX_GPIO_NR(1, 19), | |
580 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
581 | 2 | |
582 | }, | |
583 | { | |
584 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
585 | IMX_GPIO_NR(1, 17), | |
586 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
587 | 3 | |
588 | }, | |
589 | }; | |
590 | ||
591 | struct dio_cfg gw552x_dio[] = { | |
592 | { | |
593 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
594 | IMX_GPIO_NR(1, 16), | |
595 | { 0, 0 }, | |
596 | 0 | |
597 | }, | |
598 | { | |
599 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
600 | IMX_GPIO_NR(1, 19), | |
601 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
602 | 2 | |
603 | }, | |
604 | { | |
605 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
606 | IMX_GPIO_NR(1, 17), | |
607 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
608 | 3 | |
609 | }, | |
610 | { | |
611 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
612 | IMX_GPIO_NR(1, 20), | |
613 | { 0, 0 }, | |
614 | 0 | |
615 | }, | |
e86b7adf TH |
616 | { |
617 | {IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) }, | |
618 | IMX_GPIO_NR(5, 18), | |
619 | { 0, 0 }, | |
620 | 0 | |
621 | }, | |
622 | { | |
623 | {IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) }, | |
624 | IMX_GPIO_NR(5, 20), | |
625 | { 0, 0 }, | |
626 | 0 | |
627 | }, | |
628 | { | |
629 | {IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) }, | |
630 | IMX_GPIO_NR(5, 21), | |
631 | { 0, 0 }, | |
632 | 0 | |
633 | }, | |
634 | { | |
635 | {IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) }, | |
636 | IMX_GPIO_NR(5, 22), | |
637 | { 0, 0 }, | |
638 | 0 | |
639 | }, | |
640 | { | |
641 | {IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) }, | |
642 | IMX_GPIO_NR(5, 23), | |
643 | { 0, 0 }, | |
644 | 0 | |
645 | }, | |
646 | { | |
647 | {IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) }, | |
648 | IMX_GPIO_NR(5, 25), | |
649 | { 0, 0 }, | |
650 | 0 | |
651 | }, | |
1800ffa8 TH |
652 | }; |
653 | ||
654 | struct dio_cfg gw553x_dio[] = { | |
655 | { | |
656 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
657 | IMX_GPIO_NR(1, 16), | |
658 | { 0, 0 }, | |
659 | 0 | |
660 | }, | |
661 | { | |
662 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
663 | IMX_GPIO_NR(1, 19), | |
664 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
665 | 2 | |
666 | }, | |
667 | { | |
668 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
669 | IMX_GPIO_NR(1, 17), | |
670 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
671 | 3 | |
672 | }, | |
673 | { | |
674 | { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, | |
675 | IMX_GPIO_NR(1, 18), | |
676 | { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, | |
677 | 4 | |
678 | }, | |
679 | }; | |
e56c5791 | 680 | |
94a1d6c6 TH |
681 | struct dio_cfg gw560x_dio[] = { |
682 | { | |
683 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
684 | IMX_GPIO_NR(1, 16), | |
685 | { 0, 0 }, | |
686 | 0 | |
687 | }, | |
688 | { | |
689 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
690 | IMX_GPIO_NR(1, 19), | |
691 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
692 | 2 | |
693 | }, | |
694 | { | |
695 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
696 | IMX_GPIO_NR(1, 17), | |
697 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
698 | 3 | |
699 | }, | |
700 | { | |
701 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
702 | IMX_GPIO_NR(1, 20), | |
703 | { 0, 0 }, | |
704 | 0 | |
705 | }, | |
706 | }; | |
707 | ||
214fb19b TH |
708 | struct dio_cfg gw5903_dio[] = { |
709 | }; | |
710 | ||
8d1a6ff8 TH |
711 | struct dio_cfg gw5904_dio[] = { |
712 | { | |
713 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
714 | IMX_GPIO_NR(1, 16), | |
715 | { 0, 0 }, | |
716 | 0 | |
717 | }, | |
718 | { | |
719 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
720 | IMX_GPIO_NR(1, 19), | |
721 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
722 | 2 | |
723 | }, | |
724 | { | |
725 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
726 | IMX_GPIO_NR(1, 17), | |
727 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
728 | 3 | |
729 | }, | |
730 | { | |
731 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
732 | IMX_GPIO_NR(1, 20), | |
733 | { 0, 0 }, | |
734 | 0 | |
735 | }, | |
736 | { | |
737 | {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) }, | |
738 | IMX_GPIO_NR(2, 0), | |
739 | { 0, 0 }, | |
740 | 0 | |
741 | }, | |
742 | { | |
743 | {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) }, | |
744 | IMX_GPIO_NR(2, 1), | |
745 | { 0, 0 }, | |
746 | 0 | |
747 | }, | |
748 | { | |
749 | {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) }, | |
750 | IMX_GPIO_NR(2, 2), | |
751 | { 0, 0 }, | |
752 | 0 | |
753 | }, | |
754 | { | |
755 | {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) }, | |
756 | IMX_GPIO_NR(2, 3), | |
757 | { 0, 0 }, | |
758 | 0 | |
759 | }, | |
760 | { | |
761 | {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) }, | |
762 | IMX_GPIO_NR(2, 4), | |
763 | { 0, 0 }, | |
764 | 0 | |
765 | }, | |
766 | { | |
767 | {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) }, | |
768 | IMX_GPIO_NR(2, 5), | |
769 | { 0, 0 }, | |
770 | 0 | |
771 | }, | |
772 | { | |
773 | {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) }, | |
774 | IMX_GPIO_NR(2, 6), | |
775 | { 0, 0 }, | |
776 | 0 | |
777 | }, | |
778 | { | |
779 | {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) }, | |
780 | IMX_GPIO_NR(2, 7), | |
781 | { 0, 0 }, | |
782 | 0 | |
783 | }, | |
784 | }; | |
785 | ||
e56c5791 TH |
786 | /* |
787 | * Board Specific GPIO | |
788 | */ | |
789 | struct ventana gpio_cfg[GW_UNKNOWN] = { | |
790 | /* GW5400proto */ | |
791 | { | |
792 | .gpio_pads = gw54xx_gpio_pads, | |
793 | .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, | |
1800ffa8 TH |
794 | .dio_cfg = gw54xx_dio, |
795 | .dio_num = ARRAY_SIZE(gw54xx_dio), | |
e56c5791 TH |
796 | .leds = { |
797 | IMX_GPIO_NR(4, 6), | |
798 | IMX_GPIO_NR(4, 10), | |
799 | IMX_GPIO_NR(4, 15), | |
800 | }, | |
801 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
802 | .mezz_pwren = IMX_GPIO_NR(4, 7), | |
803 | .mezz_irq = IMX_GPIO_NR(4, 9), | |
804 | .rs485en = IMX_GPIO_NR(3, 24), | |
805 | .dioi2c_en = IMX_GPIO_NR(4, 5), | |
806 | .pcie_sson = IMX_GPIO_NR(1, 20), | |
f938500f | 807 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
8d1a6ff8 | 808 | .mmc_cd = IMX_GPIO_NR(7, 0), |
e56c5791 TH |
809 | }, |
810 | ||
811 | /* GW51xx */ | |
812 | { | |
813 | .gpio_pads = gw51xx_gpio_pads, | |
814 | .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, | |
1800ffa8 TH |
815 | .dio_cfg = gw51xx_dio, |
816 | .dio_num = ARRAY_SIZE(gw51xx_dio), | |
e56c5791 TH |
817 | .leds = { |
818 | IMX_GPIO_NR(4, 6), | |
819 | IMX_GPIO_NR(4, 10), | |
820 | }, | |
821 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
822 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
823 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
824 | .gps_shdn = IMX_GPIO_NR(1, 2), | |
825 | .vidin_en = IMX_GPIO_NR(5, 20), | |
826 | .wdis = IMX_GPIO_NR(7, 12), | |
f938500f | 827 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
e56c5791 TH |
828 | }, |
829 | ||
830 | /* GW52xx */ | |
831 | { | |
832 | .gpio_pads = gw52xx_gpio_pads, | |
833 | .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, | |
1800ffa8 TH |
834 | .dio_cfg = gw52xx_dio, |
835 | .dio_num = ARRAY_SIZE(gw52xx_dio), | |
e56c5791 TH |
836 | .leds = { |
837 | IMX_GPIO_NR(4, 6), | |
838 | IMX_GPIO_NR(4, 7), | |
839 | IMX_GPIO_NR(4, 15), | |
840 | }, | |
841 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
842 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
843 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
844 | .gps_shdn = IMX_GPIO_NR(1, 27), | |
845 | .vidin_en = IMX_GPIO_NR(3, 31), | |
846 | .usb_sel = IMX_GPIO_NR(1, 2), | |
847 | .wdis = IMX_GPIO_NR(7, 12), | |
5c55572f | 848 | .msata_en = GP_MSATA_SEL, |
e49621b3 | 849 | .rs232_en = GP_RS232_EN, |
f938500f | 850 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
f3a8546b | 851 | .vsel_pin = IMX_GPIO_NR(6, 14), |
8d1a6ff8 | 852 | .mmc_cd = IMX_GPIO_NR(7, 0), |
e56c5791 TH |
853 | }, |
854 | ||
855 | /* GW53xx */ | |
856 | { | |
857 | .gpio_pads = gw53xx_gpio_pads, | |
858 | .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, | |
1800ffa8 TH |
859 | .dio_cfg = gw53xx_dio, |
860 | .dio_num = ARRAY_SIZE(gw53xx_dio), | |
e56c5791 TH |
861 | .leds = { |
862 | IMX_GPIO_NR(4, 6), | |
863 | IMX_GPIO_NR(4, 7), | |
864 | IMX_GPIO_NR(4, 15), | |
865 | }, | |
866 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
867 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
868 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
869 | .gps_shdn = IMX_GPIO_NR(1, 27), | |
870 | .vidin_en = IMX_GPIO_NR(3, 31), | |
871 | .wdis = IMX_GPIO_NR(7, 12), | |
5c55572f | 872 | .msata_en = GP_MSATA_SEL, |
e49621b3 | 873 | .rs232_en = GP_RS232_EN, |
f938500f | 874 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
f3a8546b | 875 | .vsel_pin = IMX_GPIO_NR(6, 14), |
8d1a6ff8 | 876 | .mmc_cd = IMX_GPIO_NR(7, 0), |
e56c5791 TH |
877 | }, |
878 | ||
879 | /* GW54xx */ | |
880 | { | |
881 | .gpio_pads = gw54xx_gpio_pads, | |
882 | .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, | |
1800ffa8 TH |
883 | .dio_cfg = gw54xx_dio, |
884 | .dio_num = ARRAY_SIZE(gw54xx_dio), | |
e56c5791 TH |
885 | .leds = { |
886 | IMX_GPIO_NR(4, 6), | |
887 | IMX_GPIO_NR(4, 7), | |
888 | IMX_GPIO_NR(4, 15), | |
889 | }, | |
890 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
891 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
892 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
893 | .rs485en = IMX_GPIO_NR(7, 1), | |
894 | .vidin_en = IMX_GPIO_NR(3, 31), | |
895 | .dioi2c_en = IMX_GPIO_NR(4, 5), | |
896 | .pcie_sson = IMX_GPIO_NR(1, 20), | |
897 | .wdis = IMX_GPIO_NR(5, 17), | |
5c55572f | 898 | .msata_en = GP_MSATA_SEL, |
e49621b3 | 899 | .rs232_en = GP_RS232_EN, |
f938500f | 900 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
f3a8546b | 901 | .vsel_pin = IMX_GPIO_NR(6, 14), |
8d1a6ff8 | 902 | .mmc_cd = IMX_GPIO_NR(7, 0), |
e56c5791 TH |
903 | }, |
904 | ||
905 | /* GW551x */ | |
906 | { | |
907 | .gpio_pads = gw551x_gpio_pads, | |
908 | .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, | |
1800ffa8 TH |
909 | .dio_cfg = gw551x_dio, |
910 | .dio_num = ARRAY_SIZE(gw551x_dio), | |
e56c5791 TH |
911 | .leds = { |
912 | IMX_GPIO_NR(4, 7), | |
913 | }, | |
914 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
915 | .wdis = IMX_GPIO_NR(7, 12), | |
916 | }, | |
917 | ||
918 | /* GW552x */ | |
919 | { | |
920 | .gpio_pads = gw552x_gpio_pads, | |
921 | .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, | |
1800ffa8 TH |
922 | .dio_cfg = gw552x_dio, |
923 | .dio_num = ARRAY_SIZE(gw552x_dio), | |
e56c5791 TH |
924 | .leds = { |
925 | IMX_GPIO_NR(4, 6), | |
926 | IMX_GPIO_NR(4, 7), | |
927 | IMX_GPIO_NR(4, 15), | |
928 | }, | |
929 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
9a83a815 | 930 | .usb_sel = IMX_GPIO_NR(1, 7), |
e56c5791 | 931 | .wdis = IMX_GPIO_NR(7, 12), |
5c55572f | 932 | .msata_en = GP_MSATA_SEL, |
e56c5791 | 933 | }, |
385575bc TH |
934 | |
935 | /* GW553x */ | |
936 | { | |
937 | .gpio_pads = gw553x_gpio_pads, | |
938 | .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2, | |
1800ffa8 TH |
939 | .dio_cfg = gw553x_dio, |
940 | .dio_num = ARRAY_SIZE(gw553x_dio), | |
385575bc TH |
941 | .leds = { |
942 | IMX_GPIO_NR(4, 10), | |
943 | IMX_GPIO_NR(4, 11), | |
944 | }, | |
945 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
946 | .vidin_en = IMX_GPIO_NR(5, 20), | |
947 | .wdis = IMX_GPIO_NR(7, 12), | |
f938500f | 948 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
f3a8546b | 949 | .vsel_pin = IMX_GPIO_NR(6, 14), |
8d1a6ff8 TH |
950 | .mmc_cd = IMX_GPIO_NR(7, 0), |
951 | }, | |
952 | ||
94a1d6c6 TH |
953 | /* GW560x */ |
954 | { | |
955 | .gpio_pads = gw560x_gpio_pads, | |
956 | .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2, | |
957 | .dio_cfg = gw560x_dio, | |
958 | .dio_num = ARRAY_SIZE(gw560x_dio), | |
959 | .leds = { | |
960 | IMX_GPIO_NR(4, 6), | |
961 | IMX_GPIO_NR(4, 7), | |
962 | IMX_GPIO_NR(4, 15), | |
963 | }, | |
964 | .pcie_rst = IMX_GPIO_NR(4, 31), | |
965 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
966 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
967 | .rs232_en = GP_RS232_EN, | |
968 | .vidin_en = IMX_GPIO_NR(3, 31), | |
969 | .wdis = IMX_GPIO_NR(7, 12), | |
970 | .otgpwr_en = IMX_GPIO_NR(4, 15), | |
971 | .mmc_cd = IMX_GPIO_NR(7, 0), | |
972 | }, | |
973 | ||
214fb19b TH |
974 | /* GW5903 */ |
975 | { | |
976 | .gpio_pads = gw5903_gpio_pads, | |
977 | .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2, | |
978 | .dio_cfg = gw5903_dio, | |
979 | .dio_num = ARRAY_SIZE(gw5903_dio), | |
980 | .leds = { | |
981 | IMX_GPIO_NR(6, 14), | |
982 | }, | |
983 | .otgpwr_en = IMX_GPIO_NR(4, 15), | |
984 | .mmc_cd = IMX_GPIO_NR(6, 11), | |
985 | }, | |
986 | ||
8d1a6ff8 TH |
987 | /* GW5904 */ |
988 | { | |
989 | .gpio_pads = gw5904_gpio_pads, | |
990 | .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2, | |
991 | .dio_cfg = gw5904_dio, | |
992 | .dio_num = ARRAY_SIZE(gw5904_dio), | |
993 | .leds = { | |
994 | IMX_GPIO_NR(4, 6), | |
995 | IMX_GPIO_NR(4, 7), | |
996 | IMX_GPIO_NR(4, 15), | |
997 | }, | |
998 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
999 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
1000 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
1001 | .otgpwr_en = IMX_GPIO_NR(3, 22), | |
385575bc | 1002 | }, |
e56c5791 TH |
1003 | }; |
1004 | ||
1005 | void setup_iomux_gpio(int board, struct ventana_board_info *info) | |
1006 | { | |
1007 | int i; | |
1008 | ||
e56c5791 TH |
1009 | if (board >= GW_UNKNOWN) |
1010 | return; | |
1011 | ||
1012 | /* board specific iomux */ | |
1013 | imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads, | |
1014 | gpio_cfg[board].num_pads); | |
1015 | ||
e49621b3 TH |
1016 | /* RS232_EN# */ |
1017 | if (gpio_cfg[board].rs232_en) { | |
095968f1 | 1018 | gpio_request(gpio_cfg[board].rs232_en, "rs232_en#"); |
e49621b3 TH |
1019 | gpio_direction_output(gpio_cfg[board].rs232_en, 0); |
1020 | } | |
1021 | ||
e56c5791 TH |
1022 | /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ |
1023 | if (board == GW52xx && info->model[4] == '2') | |
1024 | gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); | |
1025 | ||
1026 | /* assert PCI_RST# */ | |
1027 | gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); | |
1028 | gpio_direction_output(gpio_cfg[board].pcie_rst, 0); | |
1029 | ||
1030 | /* turn off (active-high) user LED's */ | |
1031 | for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { | |
1032 | char name[16]; | |
1033 | if (gpio_cfg[board].leds[i]) { | |
1034 | sprintf(name, "led_user%d", i); | |
1035 | gpio_request(gpio_cfg[board].leds[i], name); | |
1036 | gpio_direction_output(gpio_cfg[board].leds[i], 1); | |
1037 | } | |
1038 | } | |
1039 | ||
5c55572f TH |
1040 | /* MSATA Enable - default to PCI */ |
1041 | if (gpio_cfg[board].msata_en) { | |
1042 | gpio_request(gpio_cfg[board].msata_en, "msata_en"); | |
1043 | gpio_direction_output(gpio_cfg[board].msata_en, 0); | |
1044 | } | |
1045 | ||
e56c5791 TH |
1046 | /* Expansion Mezzanine IO */ |
1047 | if (gpio_cfg[board].mezz_pwren) { | |
1048 | gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); | |
1049 | gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); | |
1050 | } | |
1051 | if (gpio_cfg[board].mezz_irq) { | |
1052 | gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#"); | |
1053 | gpio_direction_input(gpio_cfg[board].mezz_irq); | |
1054 | } | |
1055 | ||
1056 | /* RS485 Transmit Enable */ | |
1057 | if (gpio_cfg[board].rs485en) { | |
1058 | gpio_request(gpio_cfg[board].rs485en, "rs485_en"); | |
1059 | gpio_direction_output(gpio_cfg[board].rs485en, 0); | |
1060 | } | |
1061 | ||
1062 | /* GPS_SHDN */ | |
1063 | if (gpio_cfg[board].gps_shdn) { | |
1064 | gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn"); | |
1065 | gpio_direction_output(gpio_cfg[board].gps_shdn, 1); | |
1066 | } | |
1067 | ||
1068 | /* Analog video codec power enable */ | |
1069 | if (gpio_cfg[board].vidin_en) { | |
1070 | gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); | |
1071 | gpio_direction_output(gpio_cfg[board].vidin_en, 1); | |
1072 | } | |
1073 | ||
1074 | /* DIOI2C_DIS# */ | |
1075 | if (gpio_cfg[board].dioi2c_en) { | |
1076 | gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); | |
1077 | gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); | |
1078 | } | |
1079 | ||
1080 | /* PCICK_SSON: disable spread-spectrum clock */ | |
1081 | if (gpio_cfg[board].pcie_sson) { | |
1082 | gpio_request(gpio_cfg[board].pcie_sson, "pci_sson"); | |
1083 | gpio_direction_output(gpio_cfg[board].pcie_sson, 0); | |
1084 | } | |
1085 | ||
1086 | /* USBOTG mux routing */ | |
1087 | if (gpio_cfg[board].usb_sel) { | |
1088 | gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel"); | |
1089 | gpio_direction_output(gpio_cfg[board].usb_sel, 0); | |
1090 | } | |
1091 | ||
1092 | /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ | |
1093 | if (gpio_cfg[board].wdis) { | |
1094 | gpio_request(gpio_cfg[board].wdis, "wlan_dis"); | |
1095 | gpio_direction_output(gpio_cfg[board].wdis, 1); | |
1096 | } | |
34b080b7 | 1097 | |
f938500f TH |
1098 | /* OTG power off */ |
1099 | if (gpio_cfg[board].otgpwr_en) { | |
1100 | gpio_request(gpio_cfg[board].otgpwr_en, "usbotg_pwr"); | |
1101 | gpio_direction_output(gpio_cfg[board].otgpwr_en, 0); | |
1102 | } | |
1103 | ||
34b080b7 | 1104 | /* sense vselect pin to see if we support uhs-i */ |
f3a8546b TH |
1105 | if (gpio_cfg[board].vsel_pin) { |
1106 | gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect"); | |
1107 | gpio_direction_input(gpio_cfg[board].vsel_pin); | |
1108 | gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin); | |
1109 | } | |
8d1a6ff8 TH |
1110 | |
1111 | /* microSD CD */ | |
1112 | if (gpio_cfg[board].mmc_cd) { | |
1113 | gpio_request(gpio_cfg[board].mmc_cd, "sd_cd"); | |
1114 | gpio_direction_input(gpio_cfg[board].mmc_cd); | |
1115 | } | |
1116 | ||
1117 | /* Anything else board specific */ | |
1118 | switch(board) { | |
94a1d6c6 TH |
1119 | case GW560x: |
1120 | gpio_request(IMX_GPIO_NR(4, 26), "12p0_en"); | |
1121 | gpio_direction_output(IMX_GPIO_NR(4, 26), 1); | |
1122 | break; | |
214fb19b TH |
1123 | case GW5903: |
1124 | gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr"); | |
1125 | gpio_direction_output(IMX_GPIO_NR(3, 31), 1); | |
1126 | gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr"); | |
1127 | gpio_direction_output(IMX_GPIO_NR(4, 15), 1); | |
1128 | gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr"); | |
1129 | gpio_direction_output(IMX_GPIO_NR(4, 15), 1); | |
1130 | gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en"); | |
1131 | gpio_direction_output(IMX_GPIO_NR(1, 25), 1); | |
1132 | gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#"); | |
1133 | gpio_direction_input(IMX_GPIO_NR(4, 6)); | |
1134 | gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst"); | |
1135 | gpio_direction_output(IMX_GPIO_NR(4, 8), 1); | |
1136 | gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven"); | |
1137 | gpio_direction_output(IMX_GPIO_NR(1, 7), 1); | |
1138 | break; | |
8d1a6ff8 TH |
1139 | case GW5904: |
1140 | gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#"); | |
1141 | gpio_direction_output(IMX_GPIO_NR(5, 11), 1); | |
1142 | gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#"); | |
1143 | gpio_direction_output(IMX_GPIO_NR(5, 12), 1); | |
1144 | gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#"); | |
1145 | gpio_direction_output(IMX_GPIO_NR(5, 13), 1); | |
1146 | gpio_request(IMX_GPIO_NR(1, 15), "m2_off#"); | |
1147 | gpio_direction_output(IMX_GPIO_NR(1, 15), 1); | |
1148 | gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#"); | |
1149 | gpio_direction_output(IMX_GPIO_NR(1, 14), 1); | |
1150 | gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#"); | |
1151 | gpio_direction_output(IMX_GPIO_NR(1, 13), 1); | |
1152 | break; | |
1153 | } | |
e56c5791 TH |
1154 | } |
1155 | ||
1156 | /* setup GPIO pinmux and default configuration per baseboard and env */ | |
1157 | void setup_board_gpio(int board, struct ventana_board_info *info) | |
1158 | { | |
1159 | const char *s; | |
1160 | char arg[10]; | |
1161 | size_t len; | |
1162 | int i; | |
00caae6d | 1163 | int quiet = simple_strtol(env_get("quiet"), NULL, 10); |
e56c5791 TH |
1164 | |
1165 | if (board >= GW_UNKNOWN) | |
1166 | return; | |
1167 | ||
1168 | /* RS232_EN# */ | |
e49621b3 TH |
1169 | if (gpio_cfg[board].rs232_en) { |
1170 | gpio_direction_output(gpio_cfg[board].rs232_en, | |
1171 | (hwconfig("rs232")) ? 0 : 1); | |
1172 | } | |
e56c5791 TH |
1173 | |
1174 | /* MSATA Enable */ | |
5c55572f | 1175 | if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { |
e56c5791 | 1176 | gpio_direction_output(GP_MSATA_SEL, |
5c55572f | 1177 | (hwconfig("msata")) ? 1 : 0); |
e56c5791 TH |
1178 | } |
1179 | ||
1180 | /* USBOTG Select (PCISKT or FrontPanel) */ | |
1181 | if (gpio_cfg[board].usb_sel) { | |
1182 | gpio_direction_output(gpio_cfg[board].usb_sel, | |
1183 | (hwconfig("usb_pcisel")) ? 1 : 0); | |
1184 | } | |
1185 | ||
1186 | /* | |
1187 | * Configure DIO pinmux/padctl registers | |
1188 | * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions | |
1189 | */ | |
1800ffa8 | 1190 | for (i = 0; i < gpio_cfg[board].dio_num; i++) { |
e56c5791 TH |
1191 | struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; |
1192 | iomux_v3_cfg_t ctrl = DIO_PAD_CFG; | |
1193 | unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; | |
1194 | ||
1195 | if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) | |
1196 | continue; | |
1197 | sprintf(arg, "dio%d", i); | |
1198 | if (!hwconfig(arg)) | |
1199 | continue; | |
1200 | s = hwconfig_subarg(arg, "padctrl", &len); | |
1201 | if (s) { | |
1202 | ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) | |
1203 | & 0x1ffff) | MUX_MODE_SION; | |
1204 | } | |
1205 | if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { | |
1206 | if (!quiet) { | |
1207 | printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, | |
1208 | (cfg->gpio_param/32)+1, | |
1209 | cfg->gpio_param%32, | |
1210 | cfg->gpio_param); | |
1211 | } | |
1212 | imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | | |
1213 | ctrl); | |
1214 | gpio_requestf(cfg->gpio_param, "dio%d", i); | |
1215 | gpio_direction_input(cfg->gpio_param); | |
83e00f19 | 1216 | } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") && |
e56c5791 | 1217 | cfg->pwm_padmux) { |
f17a9af8 TH |
1218 | if (!cfg->pwm_param) { |
1219 | printf("DIO%d: Error: pwm config invalid\n", | |
1220 | i); | |
1221 | continue; | |
1222 | } | |
e56c5791 TH |
1223 | if (!quiet) |
1224 | printf("DIO%d: pwm%d\n", i, cfg->pwm_param); | |
1225 | imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | | |
1226 | MUX_PAD_CTRL(ctrl)); | |
1227 | } | |
1228 | } | |
1229 | ||
1230 | if (!quiet) { | |
5c55572f | 1231 | if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { |
e56c5791 TH |
1232 | printf("MSATA: %s\n", (hwconfig("msata") ? |
1233 | "enabled" : "disabled")); | |
1234 | } | |
e49621b3 TH |
1235 | if (gpio_cfg[board].rs232_en) { |
1236 | printf("RS232: %s\n", (hwconfig("rs232")) ? | |
1237 | "enabled" : "disabled"); | |
1238 | } | |
e56c5791 TH |
1239 | } |
1240 | } | |
1241 | ||
1242 | /* setup board specific PMIC */ | |
6d38f3a8 | 1243 | void setup_pmic(void) |
e56c5791 TH |
1244 | { |
1245 | struct pmic *p; | |
94a1d6c6 TH |
1246 | struct ventana_board_info ventana_info; |
1247 | int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); | |
0fd28b1f | 1248 | const int i2c_pmic = 1; |
e56c5791 TH |
1249 | u32 reg; |
1250 | ||
0fd28b1f | 1251 | i2c_set_bus_num(i2c_pmic); |
6d38f3a8 | 1252 | |
e56c5791 | 1253 | /* configure PFUZE100 PMIC */ |
6d38f3a8 TH |
1254 | if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { |
1255 | debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); | |
0fd28b1f | 1256 | power_pfuze100_init(i2c_pmic); |
e56c5791 TH |
1257 | p = pmic_get("PFUZE100"); |
1258 | if (p && !pmic_probe(p)) { | |
1259 | pmic_reg_read(p, PFUZE100_DEVICEID, ®); | |
1260 | printf("PMIC: PFUZE100 ID=0x%02x\n", reg); | |
1261 | ||
1262 | /* Set VGEN1 to 1.5V and enable */ | |
1263 | pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); | |
1264 | reg &= ~(LDO_VOL_MASK); | |
1265 | reg |= (LDOA_1_50V | LDO_EN); | |
1266 | pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); | |
1267 | ||
1268 | /* Set SWBST to 5.0V and enable */ | |
1269 | pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); | |
1270 | reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); | |
18e02ffe | 1271 | reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT)); |
e56c5791 TH |
1272 | pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); |
1273 | } | |
1274 | } | |
1275 | ||
1276 | /* configure LTC3676 PMIC */ | |
6d38f3a8 TH |
1277 | else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { |
1278 | debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); | |
0fd28b1f | 1279 | power_ltc3676_init(i2c_pmic); |
e56c5791 | 1280 | p = pmic_get("LTC3676_PMIC"); |
94a1d6c6 TH |
1281 | if (!p || pmic_probe(p)) |
1282 | return; | |
1283 | puts("PMIC: LTC3676\n"); | |
1284 | /* | |
1285 | * set board-specific scalar for max CPU frequency | |
1286 | * per CPU based on the LDO enabled Operating Ranges | |
1287 | * defined in the respective IMX6DQ and IMX6SDL | |
1288 | * datasheets. The voltage resulting from the R1/R2 | |
1289 | * feedback inputs on Ventana is 1308mV. Note that this | |
1290 | * is a bit shy of the Vmin of 1350mV in the datasheet | |
1291 | * for LDO enabled mode but is as high as we can go. | |
1292 | */ | |
1293 | switch (board) { | |
1294 | case GW560x: | |
1295 | /* mask PGOOD during SW3 transition */ | |
1296 | pmic_reg_write(p, LTC3676_DVB3B, | |
1297 | 0x1f | LTC3676_PGOOD_MASK); | |
1298 | /* set SW3 (VDD_ARM) */ | |
1299 | pmic_reg_write(p, LTC3676_DVB3A, 0x1f); | |
1300 | break; | |
214fb19b | 1301 | case GW5903: |
d576d6f3 TH |
1302 | /* mask PGOOD during SW1 transition */ |
1303 | pmic_reg_write(p, LTC3676_DVB3B, | |
1304 | 0x1f | LTC3676_PGOOD_MASK); | |
1305 | /* set SW3 (VDD_ARM) */ | |
1306 | pmic_reg_write(p, LTC3676_DVB3A, 0x1f); | |
1307 | ||
214fb19b TH |
1308 | /* mask PGOOD during SW4 transition */ |
1309 | pmic_reg_write(p, LTC3676_DVB4B, | |
1310 | 0x1f | LTC3676_PGOOD_MASK); | |
1311 | /* set SW4 (VDD_SOC) */ | |
1312 | pmic_reg_write(p, LTC3676_DVB4A, 0x1f); | |
1313 | break; | |
94a1d6c6 | 1314 | default: |
e56c5791 TH |
1315 | /* mask PGOOD during SW1 transition */ |
1316 | pmic_reg_write(p, LTC3676_DVB1B, | |
1317 | 0x1f | LTC3676_PGOOD_MASK); | |
1318 | /* set SW1 (VDD_SOC) */ | |
1319 | pmic_reg_write(p, LTC3676_DVB1A, 0x1f); | |
1320 | ||
1321 | /* mask PGOOD during SW3 transition */ | |
1322 | pmic_reg_write(p, LTC3676_DVB3B, | |
1323 | 0x1f | LTC3676_PGOOD_MASK); | |
1324 | /* set SW3 (VDD_ARM) */ | |
1325 | pmic_reg_write(p, LTC3676_DVB3A, 0x1f); | |
1326 | } | |
1327 | } | |
1328 | } | |
65da5c3b TH |
1329 | |
1330 | #ifdef CONFIG_FSL_ESDHC | |
94a1d6c6 | 1331 | static struct fsl_esdhc_cfg usdhc_cfg[2]; |
65da5c3b TH |
1332 | |
1333 | int board_mmc_init(bd_t *bis) | |
1334 | { | |
8d1a6ff8 TH |
1335 | struct ventana_board_info ventana_info; |
1336 | int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); | |
1337 | int ret; | |
1338 | ||
1339 | switch (board_type) { | |
1340 | case GW52xx: | |
1341 | case GW53xx: | |
1342 | case GW54xx: | |
1343 | case GW553x: | |
1344 | /* usdhc3: 4bit microSD */ | |
1345 | SETUP_IOMUX_PADS(usdhc3_pads); | |
94a1d6c6 TH |
1346 | usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
1347 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
1348 | usdhc_cfg[0].max_bus_width = 4; | |
1349 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); | |
1350 | case GW560x: | |
1351 | /* usdhc2: 8-bit eMMC */ | |
1352 | SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads); | |
1353 | usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; | |
1354 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | |
1355 | usdhc_cfg[0].max_bus_width = 8; | |
1356 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); | |
1357 | if (ret) | |
1358 | return ret; | |
1359 | /* usdhc3: 4-bit microSD */ | |
1360 | SETUP_IOMUX_PADS(usdhc3_pads); | |
1361 | usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; | |
1362 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
1363 | usdhc_cfg[1].max_bus_width = 4; | |
1364 | return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); | |
214fb19b TH |
1365 | case GW5903: |
1366 | /* usdhc3: 8-bit eMMC */ | |
1367 | SETUP_IOMUX_PADS(gw5904_emmc_pads); | |
1368 | usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; | |
1369 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
1370 | usdhc_cfg[0].max_bus_width = 8; | |
1371 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); | |
1372 | if (ret) | |
1373 | return ret; | |
1374 | /* usdhc2: 4-bit microSD */ | |
1375 | SETUP_IOMUX_PADS(gw5904_mmc_pads); | |
1376 | usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR; | |
1377 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | |
1378 | usdhc_cfg[1].max_bus_width = 4; | |
1379 | return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); | |
8d1a6ff8 TH |
1380 | case GW5904: |
1381 | /* usdhc3: 8bit eMMC */ | |
1382 | SETUP_IOMUX_PADS(gw5904_emmc_pads); | |
94a1d6c6 TH |
1383 | usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
1384 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
1385 | usdhc_cfg[0].max_bus_width = 8; | |
1386 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); | |
8d1a6ff8 TH |
1387 | default: |
1388 | /* doesn't have MMC */ | |
1389 | return -1; | |
1390 | } | |
65da5c3b TH |
1391 | } |
1392 | ||
1393 | int board_mmc_getcd(struct mmc *mmc) | |
1394 | { | |
8d1a6ff8 TH |
1395 | struct ventana_board_info ventana_info; |
1396 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
1397 | int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); | |
1398 | int gpio = gpio_cfg[board].mmc_cd; | |
1399 | ||
65da5c3b | 1400 | /* Card Detect */ |
8d1a6ff8 | 1401 | switch (board) { |
94a1d6c6 TH |
1402 | case GW560x: |
1403 | /* emmc is always present */ | |
1404 | if (cfg->esdhc_base == USDHC2_BASE_ADDR) | |
1405 | return 1; | |
1406 | break; | |
214fb19b | 1407 | case GW5903: |
8d1a6ff8 TH |
1408 | case GW5904: |
1409 | /* emmc is always present */ | |
1410 | if (cfg->esdhc_base == USDHC3_BASE_ADDR) | |
1411 | return 1; | |
1412 | break; | |
1413 | } | |
1414 | ||
1415 | if (gpio) { | |
1416 | debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio)); | |
1417 | return !gpio_get_value(gpio); | |
1418 | } | |
1419 | ||
1420 | return -1; | |
65da5c3b | 1421 | } |
8d1a6ff8 | 1422 | |
65da5c3b | 1423 | #endif /* CONFIG_FSL_ESDHC */ |