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e56c5791 TH |
1 | /* |
2 | * Copyright (C) 2013 Gateworks Corporation | |
3 | * | |
4 | * Author: Tim Harvey <tharvey@gateworks.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <asm/arch/mx6-pins.h> | |
10 | #include <asm/arch/sys_proto.h> | |
11 | #include <asm/gpio.h> | |
12 | #include <asm/imx-common/mxc_i2c.h> | |
13 | #include <hwconfig.h> | |
14 | #include <power/pmic.h> | |
15 | #include <power/ltc3676_pmic.h> | |
16 | #include <power/pfuze100_pmic.h> | |
17 | ||
18 | #include "common.h" | |
19 | ||
20 | /* UART1: Function varies per baseboard */ | |
21 | static iomux_v3_cfg_t const uart1_pads[] = { | |
22 | IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
23 | IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
24 | }; | |
25 | ||
26 | /* UART2: Serial Console */ | |
27 | static iomux_v3_cfg_t const uart2_pads[] = { | |
28 | IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
29 | IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
30 | }; | |
31 | ||
32 | void setup_iomux_uart(void) | |
33 | { | |
34 | SETUP_IOMUX_PADS(uart1_pads); | |
35 | SETUP_IOMUX_PADS(uart2_pads); | |
36 | } | |
37 | ||
38 | /* I2C1: GSC */ | |
39 | static struct i2c_pads_info mx6q_i2c_pad_info0 = { | |
40 | .scl = { | |
41 | .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, | |
42 | .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, | |
43 | .gp = IMX_GPIO_NR(3, 21) | |
44 | }, | |
45 | .sda = { | |
46 | .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, | |
47 | .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, | |
48 | .gp = IMX_GPIO_NR(3, 28) | |
49 | } | |
50 | }; | |
51 | static struct i2c_pads_info mx6dl_i2c_pad_info0 = { | |
52 | .scl = { | |
53 | .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, | |
54 | .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, | |
55 | .gp = IMX_GPIO_NR(3, 21) | |
56 | }, | |
57 | .sda = { | |
58 | .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, | |
59 | .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, | |
60 | .gp = IMX_GPIO_NR(3, 28) | |
61 | } | |
62 | }; | |
63 | ||
64 | /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ | |
65 | static struct i2c_pads_info mx6q_i2c_pad_info1 = { | |
66 | .scl = { | |
67 | .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, | |
68 | .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, | |
69 | .gp = IMX_GPIO_NR(4, 12) | |
70 | }, | |
71 | .sda = { | |
72 | .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, | |
73 | .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, | |
74 | .gp = IMX_GPIO_NR(4, 13) | |
75 | } | |
76 | }; | |
77 | static struct i2c_pads_info mx6dl_i2c_pad_info1 = { | |
78 | .scl = { | |
79 | .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, | |
80 | .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, | |
81 | .gp = IMX_GPIO_NR(4, 12) | |
82 | }, | |
83 | .sda = { | |
84 | .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, | |
85 | .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, | |
86 | .gp = IMX_GPIO_NR(4, 13) | |
87 | } | |
88 | }; | |
89 | ||
90 | /* I2C3: Misc/Expansion */ | |
91 | static struct i2c_pads_info mx6q_i2c_pad_info2 = { | |
92 | .scl = { | |
93 | .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, | |
94 | .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, | |
95 | .gp = IMX_GPIO_NR(1, 3) | |
96 | }, | |
97 | .sda = { | |
98 | .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, | |
99 | .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, | |
100 | .gp = IMX_GPIO_NR(1, 6) | |
101 | } | |
102 | }; | |
103 | static struct i2c_pads_info mx6dl_i2c_pad_info2 = { | |
104 | .scl = { | |
105 | .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, | |
106 | .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, | |
107 | .gp = IMX_GPIO_NR(1, 3) | |
108 | }, | |
109 | .sda = { | |
110 | .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, | |
111 | .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, | |
112 | .gp = IMX_GPIO_NR(1, 6) | |
113 | } | |
114 | }; | |
115 | ||
116 | void setup_ventana_i2c(void) | |
117 | { | |
118 | if (is_cpu_type(MXC_CPU_MX6Q)) { | |
119 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); | |
120 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); | |
121 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); | |
122 | } else { | |
123 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); | |
124 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); | |
125 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); | |
126 | } | |
127 | } | |
128 | ||
129 | /* | |
130 | * Baseboard specific GPIO | |
131 | */ | |
132 | ||
133 | /* common to add baseboards */ | |
134 | static iomux_v3_cfg_t const gw_gpio_pads[] = { | |
e56c5791 TH |
135 | /* RS232_EN# */ |
136 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
34b080b7 TH |
137 | /* SD3_VSELECT */ |
138 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
e56c5791 TH |
139 | }; |
140 | ||
141 | /* prototype */ | |
142 | static iomux_v3_cfg_t const gwproto_gpio_pads[] = { | |
143 | /* PANLEDG# */ | |
144 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
145 | /* PANLEDR# */ | |
146 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
147 | /* LOCLED# */ | |
148 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
149 | /* RS485_EN */ | |
150 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
151 | /* IOEXP_PWREN# */ | |
152 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
153 | /* IOEXP_IRQ# */ | |
154 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
155 | /* VID_EN */ | |
156 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
157 | /* DIOI2C_DIS# */ | |
158 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
159 | /* PCICK_SSON */ | |
160 | IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), | |
161 | /* PCI_RST# */ | |
162 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
163 | }; | |
164 | ||
165 | static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { | |
166 | /* PANLEDG# */ | |
167 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
168 | /* PANLEDR# */ | |
169 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
170 | /* IOEXP_PWREN# */ | |
171 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
172 | /* IOEXP_IRQ# */ | |
173 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
174 | ||
175 | /* GPS_SHDN */ | |
176 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
177 | /* VID_PWR */ | |
178 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
179 | /* PCI_RST# */ | |
180 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
181 | /* PCIESKT_WDIS# */ | |
182 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
183 | }; | |
184 | ||
185 | static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { | |
5c55572f TH |
186 | /* MSATA_EN */ |
187 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
e56c5791 TH |
188 | /* PANLEDG# */ |
189 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
190 | /* PANLEDR# */ | |
191 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
192 | /* IOEXP_PWREN# */ | |
193 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
194 | /* IOEXP_IRQ# */ | |
195 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
9a83a815 TH |
196 | /* CAN_STBY */ |
197 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
198 | /* MX6_LOCLED# */ |
199 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
200 | /* GPS_SHDN */ | |
201 | IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), | |
202 | /* USBOTG_SEL */ | |
203 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
204 | /* VID_PWR */ | |
205 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
206 | /* PCI_RST# */ | |
207 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
208 | /* PCI_RST# (GW522x) */ | |
209 | IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), | |
9a83a815 TH |
210 | /* RS485_EN */ |
211 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
212 | /* PCIESKT_WDIS# */ |
213 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
214 | }; | |
215 | ||
216 | static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { | |
5c55572f TH |
217 | /* MSATA_EN */ |
218 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
9a83a815 TH |
219 | /* CAN_STBY */ |
220 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
221 | /* USB_HUBRST# */ | |
222 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
223 | /* PANLEDG# */ |
224 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
225 | /* PANLEDR# */ | |
226 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
227 | /* MX6_LOCLED# */ | |
228 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
229 | /* IOEXP_PWREN# */ | |
230 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
231 | /* IOEXP_IRQ# */ | |
232 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
233 | /* DIOI2C_DIS# */ | |
234 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
235 | /* GPS_SHDN */ | |
236 | IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), | |
237 | /* VID_EN */ | |
238 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
239 | /* PCI_RST# */ | |
240 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
9a83a815 TH |
241 | /* RS485_EN */ |
242 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
243 | /* PCIESKT_WDIS# */ |
244 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
245 | }; | |
246 | ||
247 | static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { | |
5c55572f TH |
248 | /* MSATA_EN */ |
249 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
9a83a815 TH |
250 | /* CAN_STBY */ |
251 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
e56c5791 TH |
252 | /* PANLEDG# */ |
253 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
254 | /* PANLEDR# */ | |
9a83a815 | 255 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
e56c5791 TH |
256 | /* MX6_LOCLED# */ |
257 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
9a83a815 TH |
258 | /* USB_HUBRST# */ |
259 | IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG), | |
e56c5791 TH |
260 | /* MIPI_DIO */ |
261 | IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), | |
262 | /* RS485_EN */ | |
263 | IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), | |
264 | /* IOEXP_PWREN# */ | |
9a83a815 | 265 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), |
e56c5791 | 266 | /* IOEXP_IRQ# */ |
9a83a815 | 267 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
e56c5791 TH |
268 | /* DIOI2C_DIS# */ |
269 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
270 | /* PCI_RST# */ | |
271 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
272 | /* VID_EN */ | |
273 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
9a83a815 TH |
274 | /* RS485_EN */ |
275 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
276 | /* PCIESKT_WDIS# */ |
277 | IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), | |
278 | }; | |
279 | ||
280 | static iomux_v3_cfg_t const gw551x_gpio_pads[] = { | |
9a83a815 TH |
281 | /* CAN_STBY */ |
282 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
283 | /* PANLED# */ |
284 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
285 | /* PCI_RST# */ | |
286 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
287 | /* PCIESKT_WDIS# */ | |
288 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
289 | }; | |
290 | ||
291 | static iomux_v3_cfg_t const gw552x_gpio_pads[] = { | |
5c55572f TH |
292 | /* MSATA_EN */ |
293 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
9a83a815 TH |
294 | /* USBOTG_SEL */ |
295 | IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), | |
296 | /* USB_HUBRST# */ | |
297 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
298 | /* PANLEDG# */ |
299 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
300 | /* PANLEDR# */ | |
301 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
302 | /* MX6_LOCLED# */ | |
303 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
304 | /* PCI_RST# */ | |
305 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
306 | /* MX6_DIO[4:9] */ | |
307 | IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), | |
308 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
309 | IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), | |
310 | IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), | |
311 | IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), | |
312 | IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), | |
313 | /* PCIEGBE1_OFF# */ | |
314 | IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), | |
315 | /* PCIEGBE2_OFF# */ | |
316 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
317 | /* PCIESKT_WDIS# */ | |
318 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
319 | }; | |
320 | ||
385575bc TH |
321 | static iomux_v3_cfg_t const gw553x_gpio_pads[] = { |
322 | /* PANLEDG# */ | |
323 | IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), | |
324 | /* PANLEDR# */ | |
325 | IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG), | |
326 | ||
327 | /* VID_PWR */ | |
328 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
329 | /* PCI_RST# */ | |
330 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
331 | /* PCIESKT_WDIS# */ | |
332 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
333 | }; | |
334 | ||
e56c5791 TH |
335 | |
336 | /* | |
337 | * Board Specific GPIO | |
338 | */ | |
339 | struct ventana gpio_cfg[GW_UNKNOWN] = { | |
340 | /* GW5400proto */ | |
341 | { | |
342 | .gpio_pads = gw54xx_gpio_pads, | |
343 | .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, | |
344 | .dio_cfg = { | |
345 | { | |
346 | { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, | |
347 | IMX_GPIO_NR(1, 9), | |
348 | { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, | |
349 | 1 | |
350 | }, | |
351 | { | |
352 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
353 | IMX_GPIO_NR(1, 19), | |
354 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
355 | 2 | |
356 | }, | |
357 | { | |
358 | { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, | |
359 | IMX_GPIO_NR(2, 9), | |
360 | { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, | |
361 | 3 | |
362 | }, | |
363 | { | |
364 | { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, | |
365 | IMX_GPIO_NR(2, 10), | |
366 | { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, | |
367 | 4 | |
368 | }, | |
369 | }, | |
370 | .num_gpios = 4, | |
371 | .leds = { | |
372 | IMX_GPIO_NR(4, 6), | |
373 | IMX_GPIO_NR(4, 10), | |
374 | IMX_GPIO_NR(4, 15), | |
375 | }, | |
376 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
377 | .mezz_pwren = IMX_GPIO_NR(4, 7), | |
378 | .mezz_irq = IMX_GPIO_NR(4, 9), | |
379 | .rs485en = IMX_GPIO_NR(3, 24), | |
380 | .dioi2c_en = IMX_GPIO_NR(4, 5), | |
381 | .pcie_sson = IMX_GPIO_NR(1, 20), | |
382 | }, | |
383 | ||
384 | /* GW51xx */ | |
385 | { | |
386 | .gpio_pads = gw51xx_gpio_pads, | |
387 | .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, | |
388 | .dio_cfg = { | |
389 | { | |
390 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
391 | IMX_GPIO_NR(1, 16), | |
392 | { 0, 0 }, | |
393 | 0 | |
394 | }, | |
395 | { | |
396 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
397 | IMX_GPIO_NR(1, 19), | |
398 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
399 | 2 | |
400 | }, | |
401 | { | |
402 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
403 | IMX_GPIO_NR(1, 17), | |
404 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
405 | 3 | |
406 | }, | |
407 | { | |
408 | { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, | |
409 | IMX_GPIO_NR(1, 18), | |
410 | { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, | |
411 | 4 | |
412 | }, | |
413 | }, | |
414 | .num_gpios = 4, | |
415 | .leds = { | |
416 | IMX_GPIO_NR(4, 6), | |
417 | IMX_GPIO_NR(4, 10), | |
418 | }, | |
419 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
420 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
421 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
422 | .gps_shdn = IMX_GPIO_NR(1, 2), | |
423 | .vidin_en = IMX_GPIO_NR(5, 20), | |
424 | .wdis = IMX_GPIO_NR(7, 12), | |
425 | }, | |
426 | ||
427 | /* GW52xx */ | |
428 | { | |
429 | .gpio_pads = gw52xx_gpio_pads, | |
430 | .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, | |
431 | .dio_cfg = { | |
432 | { | |
433 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
434 | IMX_GPIO_NR(1, 16), | |
435 | { 0, 0 }, | |
436 | 0 | |
437 | }, | |
438 | { | |
439 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
440 | IMX_GPIO_NR(1, 19), | |
441 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
442 | 2 | |
443 | }, | |
444 | { | |
445 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
446 | IMX_GPIO_NR(1, 17), | |
447 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
448 | 3 | |
449 | }, | |
450 | { | |
451 | { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
452 | IMX_GPIO_NR(1, 20), | |
453 | { 0, 0 }, | |
454 | 0 | |
455 | }, | |
456 | }, | |
457 | .num_gpios = 4, | |
458 | .leds = { | |
459 | IMX_GPIO_NR(4, 6), | |
460 | IMX_GPIO_NR(4, 7), | |
461 | IMX_GPIO_NR(4, 15), | |
462 | }, | |
463 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
464 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
465 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
466 | .gps_shdn = IMX_GPIO_NR(1, 27), | |
467 | .vidin_en = IMX_GPIO_NR(3, 31), | |
468 | .usb_sel = IMX_GPIO_NR(1, 2), | |
469 | .wdis = IMX_GPIO_NR(7, 12), | |
5c55572f | 470 | .msata_en = GP_MSATA_SEL, |
e56c5791 TH |
471 | }, |
472 | ||
473 | /* GW53xx */ | |
474 | { | |
475 | .gpio_pads = gw53xx_gpio_pads, | |
476 | .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, | |
477 | .dio_cfg = { | |
478 | { | |
479 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
480 | IMX_GPIO_NR(1, 16), | |
481 | { 0, 0 }, | |
482 | 0 | |
483 | }, | |
484 | { | |
485 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
486 | IMX_GPIO_NR(1, 19), | |
487 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
488 | 2 | |
489 | }, | |
490 | { | |
491 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
492 | IMX_GPIO_NR(1, 17), | |
493 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
494 | 3 | |
495 | }, | |
496 | { | |
497 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
498 | IMX_GPIO_NR(1, 20), | |
499 | { 0, 0 }, | |
500 | 0 | |
501 | }, | |
502 | }, | |
503 | .num_gpios = 4, | |
504 | .leds = { | |
505 | IMX_GPIO_NR(4, 6), | |
506 | IMX_GPIO_NR(4, 7), | |
507 | IMX_GPIO_NR(4, 15), | |
508 | }, | |
509 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
510 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
511 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
512 | .gps_shdn = IMX_GPIO_NR(1, 27), | |
513 | .vidin_en = IMX_GPIO_NR(3, 31), | |
514 | .wdis = IMX_GPIO_NR(7, 12), | |
5c55572f | 515 | .msata_en = GP_MSATA_SEL, |
e56c5791 TH |
516 | }, |
517 | ||
518 | /* GW54xx */ | |
519 | { | |
520 | .gpio_pads = gw54xx_gpio_pads, | |
521 | .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, | |
522 | .dio_cfg = { | |
523 | { | |
524 | { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, | |
525 | IMX_GPIO_NR(1, 9), | |
526 | { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, | |
527 | 1 | |
528 | }, | |
529 | { | |
530 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
531 | IMX_GPIO_NR(1, 19), | |
532 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
533 | 2 | |
534 | }, | |
535 | { | |
536 | { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, | |
537 | IMX_GPIO_NR(2, 9), | |
538 | { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, | |
539 | 3 | |
540 | }, | |
541 | { | |
542 | { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, | |
543 | IMX_GPIO_NR(2, 10), | |
544 | { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, | |
545 | 4 | |
546 | }, | |
547 | }, | |
548 | .num_gpios = 4, | |
549 | .leds = { | |
550 | IMX_GPIO_NR(4, 6), | |
551 | IMX_GPIO_NR(4, 7), | |
552 | IMX_GPIO_NR(4, 15), | |
553 | }, | |
554 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
555 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
556 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
557 | .rs485en = IMX_GPIO_NR(7, 1), | |
558 | .vidin_en = IMX_GPIO_NR(3, 31), | |
559 | .dioi2c_en = IMX_GPIO_NR(4, 5), | |
560 | .pcie_sson = IMX_GPIO_NR(1, 20), | |
561 | .wdis = IMX_GPIO_NR(5, 17), | |
5c55572f | 562 | .msata_en = GP_MSATA_SEL, |
e56c5791 TH |
563 | }, |
564 | ||
565 | /* GW551x */ | |
566 | { | |
567 | .gpio_pads = gw551x_gpio_pads, | |
568 | .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, | |
569 | .dio_cfg = { | |
e56c5791 TH |
570 | { |
571 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
572 | IMX_GPIO_NR(1, 19), | |
573 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
574 | 2 | |
575 | }, | |
576 | { | |
577 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
578 | IMX_GPIO_NR(1, 17), | |
579 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
580 | 3 | |
581 | }, | |
e56c5791 TH |
582 | }, |
583 | .num_gpios = 2, | |
584 | .leds = { | |
585 | IMX_GPIO_NR(4, 7), | |
586 | }, | |
587 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
588 | .wdis = IMX_GPIO_NR(7, 12), | |
589 | }, | |
590 | ||
591 | /* GW552x */ | |
592 | { | |
593 | .gpio_pads = gw552x_gpio_pads, | |
594 | .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, | |
595 | .dio_cfg = { | |
9a83a815 TH |
596 | { |
597 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
598 | IMX_GPIO_NR(1, 16), | |
599 | { 0, 0 }, | |
600 | 0 | |
601 | }, | |
e56c5791 TH |
602 | { |
603 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
604 | IMX_GPIO_NR(1, 19), | |
605 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
606 | 2 | |
607 | }, | |
608 | { | |
609 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
610 | IMX_GPIO_NR(1, 17), | |
611 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
612 | 3 | |
613 | }, | |
9a83a815 TH |
614 | { |
615 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
616 | IMX_GPIO_NR(1, 20), | |
617 | { 0, 0 }, | |
618 | 0 | |
619 | }, | |
e56c5791 TH |
620 | }, |
621 | .num_gpios = 4, | |
622 | .leds = { | |
623 | IMX_GPIO_NR(4, 6), | |
624 | IMX_GPIO_NR(4, 7), | |
625 | IMX_GPIO_NR(4, 15), | |
626 | }, | |
627 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
9a83a815 | 628 | .usb_sel = IMX_GPIO_NR(1, 7), |
e56c5791 | 629 | .wdis = IMX_GPIO_NR(7, 12), |
5c55572f | 630 | .msata_en = GP_MSATA_SEL, |
e56c5791 | 631 | }, |
385575bc TH |
632 | |
633 | /* GW553x */ | |
634 | { | |
635 | .gpio_pads = gw553x_gpio_pads, | |
636 | .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2, | |
637 | .dio_cfg = { | |
638 | { | |
639 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
640 | IMX_GPIO_NR(1, 16), | |
641 | { 0, 0 }, | |
642 | 0 | |
643 | }, | |
644 | { | |
645 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
646 | IMX_GPIO_NR(1, 19), | |
647 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
648 | 2 | |
649 | }, | |
650 | { | |
651 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
652 | IMX_GPIO_NR(1, 17), | |
653 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
654 | 3 | |
655 | }, | |
656 | { | |
657 | { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, | |
658 | IMX_GPIO_NR(1, 18), | |
659 | { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, | |
660 | 4 | |
661 | }, | |
662 | }, | |
663 | .num_gpios = 4, | |
664 | .leds = { | |
665 | IMX_GPIO_NR(4, 10), | |
666 | IMX_GPIO_NR(4, 11), | |
667 | }, | |
668 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
669 | .vidin_en = IMX_GPIO_NR(5, 20), | |
670 | .wdis = IMX_GPIO_NR(7, 12), | |
671 | }, | |
e56c5791 TH |
672 | }; |
673 | ||
674 | void setup_iomux_gpio(int board, struct ventana_board_info *info) | |
675 | { | |
676 | int i; | |
677 | ||
678 | /* iomux common to all Ventana boards */ | |
679 | SETUP_IOMUX_PADS(gw_gpio_pads); | |
680 | ||
681 | /* OTG power off */ | |
682 | gpio_request(GP_USB_OTG_PWR, "usbotg_pwr"); | |
683 | gpio_direction_output(GP_USB_OTG_PWR, 0); | |
684 | ||
e56c5791 TH |
685 | /* RS232_EN# */ |
686 | gpio_request(GP_RS232_EN, "rs232_en"); | |
687 | gpio_direction_output(GP_RS232_EN, 0); | |
688 | ||
689 | if (board >= GW_UNKNOWN) | |
690 | return; | |
691 | ||
692 | /* board specific iomux */ | |
693 | imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads, | |
694 | gpio_cfg[board].num_pads); | |
695 | ||
696 | /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ | |
697 | if (board == GW52xx && info->model[4] == '2') | |
698 | gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); | |
699 | ||
700 | /* assert PCI_RST# */ | |
701 | gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); | |
702 | gpio_direction_output(gpio_cfg[board].pcie_rst, 0); | |
703 | ||
704 | /* turn off (active-high) user LED's */ | |
705 | for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { | |
706 | char name[16]; | |
707 | if (gpio_cfg[board].leds[i]) { | |
708 | sprintf(name, "led_user%d", i); | |
709 | gpio_request(gpio_cfg[board].leds[i], name); | |
710 | gpio_direction_output(gpio_cfg[board].leds[i], 1); | |
711 | } | |
712 | } | |
713 | ||
5c55572f TH |
714 | /* MSATA Enable - default to PCI */ |
715 | if (gpio_cfg[board].msata_en) { | |
716 | gpio_request(gpio_cfg[board].msata_en, "msata_en"); | |
717 | gpio_direction_output(gpio_cfg[board].msata_en, 0); | |
718 | } | |
719 | ||
e56c5791 TH |
720 | /* Expansion Mezzanine IO */ |
721 | if (gpio_cfg[board].mezz_pwren) { | |
722 | gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); | |
723 | gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); | |
724 | } | |
725 | if (gpio_cfg[board].mezz_irq) { | |
726 | gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#"); | |
727 | gpio_direction_input(gpio_cfg[board].mezz_irq); | |
728 | } | |
729 | ||
730 | /* RS485 Transmit Enable */ | |
731 | if (gpio_cfg[board].rs485en) { | |
732 | gpio_request(gpio_cfg[board].rs485en, "rs485_en"); | |
733 | gpio_direction_output(gpio_cfg[board].rs485en, 0); | |
734 | } | |
735 | ||
736 | /* GPS_SHDN */ | |
737 | if (gpio_cfg[board].gps_shdn) { | |
738 | gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn"); | |
739 | gpio_direction_output(gpio_cfg[board].gps_shdn, 1); | |
740 | } | |
741 | ||
742 | /* Analog video codec power enable */ | |
743 | if (gpio_cfg[board].vidin_en) { | |
744 | gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); | |
745 | gpio_direction_output(gpio_cfg[board].vidin_en, 1); | |
746 | } | |
747 | ||
748 | /* DIOI2C_DIS# */ | |
749 | if (gpio_cfg[board].dioi2c_en) { | |
750 | gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); | |
751 | gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); | |
752 | } | |
753 | ||
754 | /* PCICK_SSON: disable spread-spectrum clock */ | |
755 | if (gpio_cfg[board].pcie_sson) { | |
756 | gpio_request(gpio_cfg[board].pcie_sson, "pci_sson"); | |
757 | gpio_direction_output(gpio_cfg[board].pcie_sson, 0); | |
758 | } | |
759 | ||
760 | /* USBOTG mux routing */ | |
761 | if (gpio_cfg[board].usb_sel) { | |
762 | gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel"); | |
763 | gpio_direction_output(gpio_cfg[board].usb_sel, 0); | |
764 | } | |
765 | ||
766 | /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ | |
767 | if (gpio_cfg[board].wdis) { | |
768 | gpio_request(gpio_cfg[board].wdis, "wlan_dis"); | |
769 | gpio_direction_output(gpio_cfg[board].wdis, 1); | |
770 | } | |
34b080b7 TH |
771 | |
772 | /* sense vselect pin to see if we support uhs-i */ | |
773 | gpio_request(GP_SD3_VSELECT, "sd3_vselect"); | |
774 | gpio_direction_input(GP_SD3_VSELECT); | |
775 | gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT); | |
e56c5791 TH |
776 | } |
777 | ||
778 | /* setup GPIO pinmux and default configuration per baseboard and env */ | |
779 | void setup_board_gpio(int board, struct ventana_board_info *info) | |
780 | { | |
781 | const char *s; | |
782 | char arg[10]; | |
783 | size_t len; | |
784 | int i; | |
785 | int quiet = simple_strtol(getenv("quiet"), NULL, 10); | |
786 | ||
787 | if (board >= GW_UNKNOWN) | |
788 | return; | |
789 | ||
790 | /* RS232_EN# */ | |
791 | gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); | |
792 | ||
793 | /* MSATA Enable */ | |
5c55572f | 794 | if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { |
e56c5791 | 795 | gpio_direction_output(GP_MSATA_SEL, |
5c55572f | 796 | (hwconfig("msata")) ? 1 : 0); |
e56c5791 TH |
797 | } |
798 | ||
799 | /* USBOTG Select (PCISKT or FrontPanel) */ | |
800 | if (gpio_cfg[board].usb_sel) { | |
801 | gpio_direction_output(gpio_cfg[board].usb_sel, | |
802 | (hwconfig("usb_pcisel")) ? 1 : 0); | |
803 | } | |
804 | ||
805 | /* | |
806 | * Configure DIO pinmux/padctl registers | |
807 | * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions | |
808 | */ | |
9a83a815 | 809 | for (i = 0; i < gpio_cfg[board].num_gpios; i++) { |
e56c5791 TH |
810 | struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; |
811 | iomux_v3_cfg_t ctrl = DIO_PAD_CFG; | |
812 | unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; | |
813 | ||
814 | if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) | |
815 | continue; | |
816 | sprintf(arg, "dio%d", i); | |
817 | if (!hwconfig(arg)) | |
818 | continue; | |
819 | s = hwconfig_subarg(arg, "padctrl", &len); | |
820 | if (s) { | |
821 | ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) | |
822 | & 0x1ffff) | MUX_MODE_SION; | |
823 | } | |
824 | if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { | |
825 | if (!quiet) { | |
826 | printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, | |
827 | (cfg->gpio_param/32)+1, | |
828 | cfg->gpio_param%32, | |
829 | cfg->gpio_param); | |
830 | } | |
831 | imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | | |
832 | ctrl); | |
833 | gpio_requestf(cfg->gpio_param, "dio%d", i); | |
834 | gpio_direction_input(cfg->gpio_param); | |
83e00f19 | 835 | } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") && |
e56c5791 | 836 | cfg->pwm_padmux) { |
f17a9af8 TH |
837 | if (!cfg->pwm_param) { |
838 | printf("DIO%d: Error: pwm config invalid\n", | |
839 | i); | |
840 | continue; | |
841 | } | |
e56c5791 TH |
842 | if (!quiet) |
843 | printf("DIO%d: pwm%d\n", i, cfg->pwm_param); | |
844 | imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | | |
845 | MUX_PAD_CTRL(ctrl)); | |
846 | } | |
847 | } | |
848 | ||
849 | if (!quiet) { | |
5c55572f | 850 | if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { |
e56c5791 TH |
851 | printf("MSATA: %s\n", (hwconfig("msata") ? |
852 | "enabled" : "disabled")); | |
853 | } | |
854 | printf("RS232: %s\n", (hwconfig("rs232")) ? | |
855 | "enabled" : "disabled"); | |
856 | } | |
857 | } | |
858 | ||
859 | /* setup board specific PMIC */ | |
6d38f3a8 | 860 | void setup_pmic(void) |
e56c5791 TH |
861 | { |
862 | struct pmic *p; | |
863 | u32 reg; | |
864 | ||
6d38f3a8 TH |
865 | i2c_set_bus_num(CONFIG_I2C_PMIC); |
866 | ||
e56c5791 | 867 | /* configure PFUZE100 PMIC */ |
6d38f3a8 TH |
868 | if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { |
869 | debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); | |
e56c5791 TH |
870 | power_pfuze100_init(CONFIG_I2C_PMIC); |
871 | p = pmic_get("PFUZE100"); | |
872 | if (p && !pmic_probe(p)) { | |
873 | pmic_reg_read(p, PFUZE100_DEVICEID, ®); | |
874 | printf("PMIC: PFUZE100 ID=0x%02x\n", reg); | |
875 | ||
876 | /* Set VGEN1 to 1.5V and enable */ | |
877 | pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); | |
878 | reg &= ~(LDO_VOL_MASK); | |
879 | reg |= (LDOA_1_50V | LDO_EN); | |
880 | pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); | |
881 | ||
882 | /* Set SWBST to 5.0V and enable */ | |
883 | pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); | |
884 | reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); | |
18e02ffe | 885 | reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT)); |
e56c5791 TH |
886 | pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); |
887 | } | |
888 | } | |
889 | ||
890 | /* configure LTC3676 PMIC */ | |
6d38f3a8 TH |
891 | else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { |
892 | debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); | |
e56c5791 TH |
893 | power_ltc3676_init(CONFIG_I2C_PMIC); |
894 | p = pmic_get("LTC3676_PMIC"); | |
895 | if (p && !pmic_probe(p)) { | |
896 | puts("PMIC: LTC3676\n"); | |
897 | /* | |
898 | * set board-specific scalar for max CPU frequency | |
899 | * per CPU based on the LDO enabled Operating Ranges | |
900 | * defined in the respective IMX6DQ and IMX6SDL | |
901 | * datasheets. The voltage resulting from the R1/R2 | |
902 | * feedback inputs on Ventana is 1308mV. Note that this | |
903 | * is a bit shy of the Vmin of 1350mV in the datasheet | |
904 | * for LDO enabled mode but is as high as we can go. | |
905 | * | |
906 | * We will rely on an OS kernel driver to properly | |
907 | * regulate these per CPU operating point and use LDO | |
908 | * bypass mode when using the higher frequency | |
909 | * operating points to compensate as LDO bypass mode | |
910 | * allows the rails be 125mV lower. | |
911 | */ | |
912 | /* mask PGOOD during SW1 transition */ | |
913 | pmic_reg_write(p, LTC3676_DVB1B, | |
914 | 0x1f | LTC3676_PGOOD_MASK); | |
915 | /* set SW1 (VDD_SOC) */ | |
916 | pmic_reg_write(p, LTC3676_DVB1A, 0x1f); | |
917 | ||
918 | /* mask PGOOD during SW3 transition */ | |
919 | pmic_reg_write(p, LTC3676_DVB3B, | |
920 | 0x1f | LTC3676_PGOOD_MASK); | |
921 | /* set SW3 (VDD_ARM) */ | |
922 | pmic_reg_write(p, LTC3676_DVB3A, 0x1f); | |
923 | } | |
924 | } | |
925 | } |