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imx: ventana: add fdt fixup to enable UHS-I support on selected boards
[people/ms/u-boot.git] / board / gateworks / gw_ventana / gw_ventana.c
CommitLineData
59189a8b
TH		 1/*
2 * Copyright (C) 2013 Gateworks Corporation
3 *
4 * Author: Tim Harvey <tharvey@gateworks.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
59189a8b 10#include <asm/arch/clock.h>
e56c5791 11#include <asm/arch/crm_regs.h>
59189a8b
TH		 12#include <asm/arch/iomux.h>
13#include <asm/arch/mx6-pins.h>
7a278f9f 14#include <asm/arch/mxc_hdmi.h>
59189a8b
TH		 15#include <asm/arch/sys_proto.h>
16#include <asm/gpio.h>
59189a8b
TH		 17#include <asm/imx-common/boot_mode.h>
18#include <asm/imx-common/sata.h>
3acb011c 19#include <asm/imx-common/spi.h>
7a278f9f 20#include <asm/imx-common/video.h>
e56c5791
TH		 21#include <asm/io.h>
22#include <dm.h>
d41c8c8e 23#include <dm/platform_data/serial_mxc.h>
f17a9af8 24#include <hwconfig.h>
59189a8b 25#include <i2c.h>
59189a8b
TH		 26#include <fdt_support.h>
27#include <fsl_esdhc.h>
e56c5791
TH		 28#include <jffs2/load_kernel.h>
29#include <linux/ctype.h>
59189a8b 30#include <miiphy.h>
59189a8b
TH		 31#include <mtd_node.h>
32#include <netdev.h>
dad08286 33#include <pci.h>
59189a8b 34#include <power/pmic.h>
234d89da 35#include <power/ltc3676_pmic.h>
59189a8b 36#include <power/pfuze100_pmic.h>
59189a8b
TH		 37#include <fdt_support.h>
38#include <jffs2/load_kernel.h>
39#include <spi_flash.h>
40
41#include "gsc.h"
e56c5791 42#include "common.h"
59189a8b
TH		 43
44DECLARE_GLOBAL_DATA_PTR;
45
d9d41492 46
59189a8b
TH		 47/*
48 * EEPROM board info struct populated by read_eeprom so that we only have to
49 * read it once.
50 */
9c0fe83e 51struct ventana_board_info ventana_info;
59189a8b 52
1274bd2c 53static int board_type;
59189a8b 54
59189a8b 55/* MMC */
1274bd2c 56static iomux_v3_cfg_t const usdhc3_pads[] = {
680e8db4
TH		 57 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
58 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
60 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
62 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
34b080b7 63 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59189a8b
TH		 64};
65
66/* ENET */
1274bd2c 67static iomux_v3_cfg_t const enet_pads[] = {
680e8db4
TH		 68 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
72 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
76 MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
78 MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
85 MUX_PAD_CTRL(ENET_PAD_CTRL)),
59189a8b 86 /* PHY nRST */
d9d41492 87 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
59189a8b
TH		 88};
89
90/* NAND */
1274bd2c 91static iomux_v3_cfg_t const nfc_pads[] = {
680e8db4
TH		 92 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
99 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
100 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
102 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
103 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
104 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
105 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
106 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
59189a8b
TH		 107};
108
109#ifdef CONFIG_CMD_NAND
110static void setup_gpmi_nand(void)
111{
112 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
113
114 /* config gpmi nand iomux */
680e8db4 115 SETUP_IOMUX_PADS(nfc_pads);
59189a8b
TH		 116
117 /* config gpmi and bch clock to 100 MHz */
118 clrsetbits_le32(&mxc_ccm->cs2cdr,
119 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
120 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
121 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
122 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
123 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
124 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
125
126 /* enable gpmi and bch clock gating */
127 setbits_le32(&mxc_ccm->CCGR4,
128 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
129 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
130 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
131 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
132 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
133
134 /* enable apbh clock gating */
135 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
136}
137#endif
138
def60315 139static void setup_iomux_enet(int gpio)
59189a8b 140{
680e8db4 141 SETUP_IOMUX_PADS(enet_pads);
59189a8b
TH		 142
143 /* toggle PHY_RST# */
def60315
TH		 144 gpio_request(gpio, "phy_rst#");
145 gpio_direction_output(gpio, 0);
59189a8b 146 mdelay(2);
def60315 147 gpio_set_value(gpio, 1);
59189a8b
TH		 148}
149
59189a8b 150#ifdef CONFIG_USB_EHCI_MX6
1274bd2c 151static iomux_v3_cfg_t const usb_pads[] = {
d9d41492
TH		 152 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
153 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
680e8db4 154 /* OTG PWR */
d9d41492 155 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
59189a8b
TH		 156};
157
158int board_ehci_hcd_init(int port)
159{
def60315 160 int gpio;
59189a8b 161
680e8db4 162 SETUP_IOMUX_PADS(usb_pads);
59189a8b 163
9a83a815
TH		 164 /* Reset USB HUB */
165 switch (board_type) {
166 case GW53xx:
167 case GW552x:
def60315 168 gpio = (IMX_GPIO_NR(1, 9));
59189a8b 169 break;
9a83a815
TH		 170 case GW54proto:
171 case GW54xx:
def60315 172 gpio = (IMX_GPIO_NR(1, 16));
59189a8b 173 break;
def60315
TH		 174 default:
175 return 0;
59189a8b
TH		 176 }
177
def60315
TH		 178 /* request and toggle hub rst */
179 gpio_request(gpio, "usb_hub_rst#");
180 gpio_direction_output(gpio, 0);
181 mdelay(2);
182 gpio_set_value(gpio, 1);
183
59189a8b
TH		 184 return 0;
185}
186
187int board_ehci_power(int port, int on)
188{
189 if (port)
190 return 0;
191 gpio_set_value(GP_USB_OTG_PWR, on);
192 return 0;
193}
194#endif /* CONFIG_USB_EHCI_MX6 */
195
196#ifdef CONFIG_FSL_ESDHC
1274bd2c 197static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
59189a8b
TH		 198
199int board_mmc_getcd(struct mmc *mmc)
200{
201 /* Card Detect */
def60315 202 gpio_request(GP_SD3_CD, "sd_cd");
59189a8b
TH		 203 gpio_direction_input(GP_SD3_CD);
204 return !gpio_get_value(GP_SD3_CD);
205}
206
207int board_mmc_init(bd_t *bis)
208{
209 /* Only one USDHC controller on Ventana */
680e8db4 210 SETUP_IOMUX_PADS(usdhc3_pads);
59189a8b
TH		 211 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
212 usdhc_cfg.max_bus_width = 4;
213
214 return fsl_esdhc_initialize(bis, &usdhc_cfg);
215}
216#endif /* CONFIG_FSL_ESDHC */
217
218#ifdef CONFIG_MXC_SPI
219iomux_v3_cfg_t const ecspi1_pads[] = {
220 /* SS1 */
680e8db4
TH		 221 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
222 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
223 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
224 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
59189a8b
TH		 225};
226
155fa9af
NK		 227int board_spi_cs_gpio(unsigned bus, unsigned cs)
228{
229 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
230}
231
59189a8b
TH		 232static void setup_spi(void)
233{
def60315 234 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
155fa9af 235 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
680e8db4 236 SETUP_IOMUX_PADS(ecspi1_pads);
59189a8b
TH		 237}
238#endif
239
240/* configure eth0 PHY board-specific LED behavior */
241int board_phy_config(struct phy_device *phydev)
242{
243 unsigned short val;
244
245 /* Marvel 88E1510 */
246 if (phydev->phy_id == 0x1410dd1) {
247 /*
248 * Page 3, Register 16: LED[2:0] Function Control Register
249 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
250 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
251 */
252 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
253 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
254 val &= 0xff00;
255 val |= 0x0017;
256 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
257 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
258 }
259
260 if (phydev->drv->config)
261 phydev->drv->config(phydev);
262
263 return 0;
264}
265
266int board_eth_init(bd_t *bis)
267{
59189a8b 268#ifdef CONFIG_FEC_MXC
385575bc
TH		 269 struct ventana_board_info *info = &ventana_info;
270
271 if (test_bit(EECONFIG_ETH0, info->config)) {
def60315 272 setup_iomux_enet(GP_PHY_RST);
3aa22674 273 cpu_eth_init(bis);
aec3761a 274 }
59189a8b
TH		 275#endif
276
0a6ee033
TH		 277#ifdef CONFIG_E1000
278 e1000_initialize(bis);
279#endif
280
59189a8b
TH		 281#ifdef CONFIG_CI_UDC
282 /* For otg ethernet*/
283 usb_eth_initialize(bis);
284#endif
285
e806b229
TH		 286 /* default to the first detected enet dev */
287 if (!getenv("ethprime")) {
288 struct eth_device *dev = eth_get_dev_by_index(0);
289 if (dev) {
290 setenv("ethprime", dev->name);
291 printf("set ethprime to %s\n", getenv("ethprime"));
292 }
293 }
294
59189a8b
TH		 295 return 0;
296}
297
7a278f9f
TH		 298#if defined(CONFIG_VIDEO_IPUV3)
299
300static void enable_hdmi(struct display_info_t const *dev)
301{
302 imx_enable_hdmi_phy();
303}
304
305static int detect_i2c(struct display_info_t const *dev)
306{
307 return i2c_set_bus_num(dev->bus) == 0 &&
308 i2c_probe(dev->addr) == 0;
309}
310
311static void enable_lvds(struct display_info_t const *dev)
312{
313 struct iomuxc *iomux = (struct iomuxc *)
314 IOMUXC_BASE_ADDR;
315
316 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
317 u32 reg = readl(&iomux->gpr[2]);
318 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
319 writel(reg, &iomux->gpr[2]);
320
321 /* Enable Backlight */
78532623
TH		 322 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
323 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
def60315 324 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
d9d41492 325 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
7a278f9f
TH		 326 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
327}
328
329struct display_info_t const displays[] = {{
330 /* HDMI Output */
331 .bus = -1,
332 .addr = 0,
333 .pixfmt = IPU_PIX_FMT_RGB24,
334 .detect = detect_hdmi,
335 .enable = enable_hdmi,
336 .mode = {
337 .name = "HDMI",
338 .refresh = 60,
339 .xres = 1024,
340 .yres = 768,
341 .pixclock = 15385,
342 .left_margin = 220,
343 .right_margin = 40,
344 .upper_margin = 21,
345 .lower_margin = 7,
346 .hsync_len = 60,
347 .vsync_len = 10,
348 .sync = FB_SYNC_EXT,
349 .vmode = FB_VMODE_NONINTERLACED
350} }, {
351 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
352 .bus = 2,
353 .addr = 0x4,
354 .pixfmt = IPU_PIX_FMT_LVDS666,
355 .detect = detect_i2c,
356 .enable = enable_lvds,
357 .mode = {
358 .name = "Hannstar-XGA",
359 .refresh = 60,
360 .xres = 1024,
361 .yres = 768,
362 .pixclock = 15385,
363 .left_margin = 220,
364 .right_margin = 40,
365 .upper_margin = 21,
366 .lower_margin = 7,
367 .hsync_len = 60,
368 .vsync_len = 10,
369 .sync = FB_SYNC_EXT,
370 .vmode = FB_VMODE_NONINTERLACED
f02390b6
TH		 371} }, {
372 /* DLC700JMG-T-4 */
373 .bus = 0,
374 .addr = 0,
375 .detect = NULL,
376 .enable = enable_lvds,
377 .pixfmt = IPU_PIX_FMT_LVDS666,
378 .mode = {
379 .name = "DLC700JMGT4",
380 .refresh = 60,
381 .xres = 1024, /* 1024x600active pixels */
382 .yres = 600,
383 .pixclock = 15385, /* 64MHz */
384 .left_margin = 220,
385 .right_margin = 40,
386 .upper_margin = 21,
387 .lower_margin = 7,
388 .hsync_len = 60,
389 .vsync_len = 10,
390 .sync = FB_SYNC_EXT,
391 .vmode = FB_VMODE_NONINTERLACED
392} }, {
393 /* DLC800FIG-T-3 */
394 .bus = 0,
395 .addr = 0,
396 .detect = NULL,
397 .enable = enable_lvds,
398 .pixfmt = IPU_PIX_FMT_LVDS666,
399 .mode = {
400 .name = "DLC800FIGT3",
401 .refresh = 60,
402 .xres = 1024, /* 1024x768 active pixels */
403 .yres = 768,
404 .pixclock = 15385, /* 64MHz */
405 .left_margin = 220,
406 .right_margin = 40,
407 .upper_margin = 21,
408 .lower_margin = 7,
409 .hsync_len = 60,
410 .vsync_len = 10,
411 .sync = FB_SYNC_EXT,
412 .vmode = FB_VMODE_NONINTERLACED
7a278f9f
TH		 413} } };
414size_t display_count = ARRAY_SIZE(displays);
415
416static void setup_display(void)
417{
418 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
419 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
420 int reg;
421
422 enable_ipu_clock();
423 imx_setup_hdmi();
424 /* Turn on LDB0,IPU,IPU DI0 clocks */
425 reg = __raw_readl(&mxc_ccm->CCGR3);
426 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
427 writel(reg, &mxc_ccm->CCGR3);
428
429 /* set LDB0, LDB1 clk select to 011/011 */
430 reg = readl(&mxc_ccm->cs2cdr);
431 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
432 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
433 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
434 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
435 writel(reg, &mxc_ccm->cs2cdr);
436
437 reg = readl(&mxc_ccm->cscmr2);
438 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
439 writel(reg, &mxc_ccm->cscmr2);
440
441 reg = readl(&mxc_ccm->chsccdr);
442 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
443 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
444 writel(reg, &mxc_ccm->chsccdr);
445
446 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
447 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
448 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
449 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
450 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
451 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
452 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
453 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
454 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
455 writel(reg, &iomux->gpr[2]);
456
457 reg = readl(&iomux->gpr[3]);
458 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
459 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
460 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
461 writel(reg, &iomux->gpr[3]);
462
78532623 463 /* LVDS Backlight GPIO on LVDS connector - output low */
d9d41492 464 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
7a278f9f
TH		 465 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
466}
467#endif /* CONFIG_VIDEO_IPUV3 */
468
234d89da
TH		 469/* setup board specific PMIC */
470int power_init_board(void)
471{
6d38f3a8 472 setup_pmic();
234d89da
TH		 473 return 0;
474}
475
59189a8b
TH		 476#if defined(CONFIG_CMD_PCI)
477int imx6_pcie_toggle_reset(void)
478{
479 if (board_type < GW_UNKNOWN) {
680e8db4 480 uint pin = gpio_cfg[board_type].pcie_rst;
def60315 481 gpio_request(pin, "pci_rst#");
680e8db4 482 gpio_direction_output(pin, 0);
59189a8b 483 mdelay(50);
680e8db4 484 gpio_direction_output(pin, 1);
59189a8b
TH		 485 }
486 return 0;
487}
dad08286
TH		 488
489/*
490 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
491 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
492 * properly and assert reset for 100ms.
493 */
494void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
495 unsigned short vendor, unsigned short device,
496 unsigned short class)
497{
498 u32 dw;
499
500 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
501 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
502 if (vendor == PCI_VENDOR_ID_PLX &&
503 (device & 0xfff0) == 0x8600 &&
504 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
505 debug("configuring PLX 860X downstream PERST#\n");
506 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
507 dw |= 0xaaa8; /* GPIO1-7 outputs */
508 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
509
510 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
511 dw |= 0xfe; /* GPIO1-7 output high */
512 pci_hose_write_config_dword(hose, dev, 0x644, dw);
513
514 mdelay(100);
515 }
516}
59189a8b
TH		 517#endif /* CONFIG_CMD_PCI */
518
519#ifdef CONFIG_SERIAL_TAG
520/*
521 * called when setting up ATAGS before booting kernel
522 * populate serialnum from the following (in order of priority):
523 * serial# env var
524 * eeprom
525 */
526void get_board_serial(struct tag_serialnr *serialnr)
527{
528 char *serial = getenv("serial#");
529
530 if (serial) {
531 serialnr->high = 0;
532 serialnr->low = simple_strtoul(serial, NULL, 10);
533 } else if (ventana_info.model[0]) {
534 serialnr->high = 0;
535 serialnr->low = ventana_info.serial;
536 } else {
537 serialnr->high = 0;
538 serialnr->low = 0;
539 }
540}
541#endif
542
543/*
544 * Board Support
545 */
546
547int board_early_init_f(void)
548{
549 setup_iomux_uart();
def60315 550
7a278f9f
TH		 551#if defined(CONFIG_VIDEO_IPUV3)
552 setup_display();
553#endif
59189a8b
TH		 554 return 0;
555}
556
557int dram_init(void)
558{
0cc11dea 559 gd->ram_size = imx_ddr_size();
59189a8b
TH		 560 return 0;
561}
562
563int board_init(void)
564{
0a11d6f2 565 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
59189a8b
TH		 566
567 clrsetbits_le32(&iomuxc_regs->gpr[1],
568 IOMUXC_GPR1_OTG_ID_MASK,
569 IOMUXC_GPR1_OTG_ID_GPIO1);
570
571 /* address of linux boot parameters */
572 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
573
574#ifdef CONFIG_CMD_NAND
575 setup_gpmi_nand();
576#endif
577#ifdef CONFIG_MXC_SPI
578 setup_spi();
579#endif
e56c5791 580 setup_ventana_i2c();
59189a8b
TH		 581
582#ifdef CONFIG_CMD_SATA
583 setup_sata();
584#endif
585 /* read Gateworks EEPROM into global struct (used later) */
9c0fe83e 586 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
59189a8b 587
e56c5791 588 setup_iomux_gpio(board_type, &ventana_info);
59189a8b
TH		 589
590 return 0;
591}
592
593#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
594/*
595 * called during late init (after relocation and after board_init())
596 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
597 * EEPROM read.
598 */
599int checkboard(void)
600{
601 struct ventana_board_info *info = &ventana_info;
602 unsigned char buf[4];
603 const char *p;
604 int quiet; /* Quiet or minimal output mode */
605
606 quiet = 0;
607 p = getenv("quiet");
608 if (p)
609 quiet = simple_strtol(p, NULL, 10);
610 else
611 setenv("quiet", "0");
612
613 puts("\nGateworks Corporation Copyright 2014\n");
614 if (info->model[0]) {
615 printf("Model: %s\n", info->model);
616 printf("MFGDate: %02x-%02x-%02x%02x\n",
617 info->mfgdate[0], info->mfgdate[1],
618 info->mfgdate[2], info->mfgdate[3]);
619 printf("Serial:%d\n", info->serial);
620 } else {
621 puts("Invalid EEPROM - board will not function fully\n");
622 }
623 if (quiet)
624 return 0;
625
626 /* Display GSC firmware revision/CRC/status */
ee5931d4
TH		 627 gsc_info(0);
628
59189a8b
TH		 629 /* Display RTC */
630 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
631 printf("RTC: %d\n",
632 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
633 }
634
635 return 0;
636}
637#endif
638
639#ifdef CONFIG_CMD_BMODE
640/*
641 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
642 * see Table 8-11 and Table 5-9
643 * BOOT_CFG1[7] = 1 (boot from NAND)
644 * BOOT_CFG1[5] = 0 - raw NAND
645 * BOOT_CFG1[4] = 0 - default pad settings
646 * BOOT_CFG1[3:2] = 00 - devices = 1
647 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
648 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
649 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
650 * BOOT_CFG2[0] = 0 - Reset time 12ms
651 */
652static const struct boot_mode board_boot_modes[] = {
653 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
654 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
655 { NULL, 0 },
656};
657#endif
658
659/* late init */
660int misc_init_r(void)
661{
662 struct ventana_board_info *info = &ventana_info;
59189a8b
TH		 663
664 /* set env vars based on EEPROM data */
665 if (ventana_info.model[0]) {
666 char str[16], fdt[36];
667 char *p;
668 const char *cputype = "";
669 int i;
670
671 /*
672 * FDT name will be prefixed with CPU type. Three versions
673 * will be created each increasingly generic and bootloader
674 * env scripts will try loading each from most specific to
675 * least.
676 */
0cc11dea
TH		 677 if (is_cpu_type(MXC_CPU_MX6Q) ||
678 is_cpu_type(MXC_CPU_MX6D))
59189a8b 679 cputype = "imx6q";
0cc11dea
TH		 680 else if (is_cpu_type(MXC_CPU_MX6DL) ||
681 is_cpu_type(MXC_CPU_MX6SOLO))
59189a8b 682 cputype = "imx6dl";
a7c67d7c 683 setenv("soctype", cputype);
63b85adc
TH		 684 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
685 setenv("flash_layout", "large");
686 else
687 setenv("flash_layout", "normal");
59189a8b
TH		 688 memset(str, 0, sizeof(str));
689 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
690 str[i] = tolower(info->model[i]);
40c74675 691 setenv("model", str);
59189a8b
TH		 692 if (!getenv("fdt_file")) {
693 sprintf(fdt, "%s-%s.dtb", cputype, str);
694 setenv("fdt_file", fdt);
695 }
696 p = strchr(str, '-');
697 if (p) {
698 *p++ = 0;
699
700 setenv("model_base", str);
80d1a3ee
TH		 701 sprintf(fdt, "%s-%s.dtb", cputype, str);
702 setenv("fdt_file1", fdt);
385575bc
TH		 703 if (board_type != GW551x &&
704 board_type != GW552x &&
705 board_type != GW553x)
3aa22674 706 str[4] = 'x';
59189a8b
TH		 707 str[5] = 'x';
708 str[6] = 0;
80d1a3ee
TH		 709 sprintf(fdt, "%s-%s.dtb", cputype, str);
710 setenv("fdt_file2", fdt);
59189a8b
TH		 711 }
712
713 /* initialize env from EEPROM */
714 if (test_bit(EECONFIG_ETH0, info->config) &&
715 !getenv("ethaddr")) {
716 eth_setenv_enetaddr("ethaddr", info->mac0);
717 }
718 if (test_bit(EECONFIG_ETH1, info->config) &&
719 !getenv("eth1addr")) {
720 eth_setenv_enetaddr("eth1addr", info->mac1);
721 }
722
723 /* board serial-number */
724 sprintf(str, "%6d", info->serial);
725 setenv("serial#", str);
e7329174
TH		 726
727 /* memory MB */
728 sprintf(str, "%d", (int) (gd->ram_size >> 20));
729 setenv("mem_mb", str);
59189a8b
TH		 730 }
731
59189a8b 732
e56c5791
TH		 733 /* setup baseboard specific GPIO based on board and env */
734 setup_board_gpio(board_type, info);
59189a8b
TH		 735
736#ifdef CONFIG_CMD_BMODE
737 add_board_boot_modes(board_boot_modes);
738#endif
739
2d833c85
TH		 740 /* disable boot watchdog */
741 gsc_boot_wd_disable();
59189a8b
TH		 742
743 return 0;
744}
745
746#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
747
a2559f11
TH		 748static int ft_sethdmiinfmt(void *blob, char *mode)
749{
750 int off;
751
752 if (!mode)
753 return -EINVAL;
754
755 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
756 if (off < 0)
757 return off;
758
759 if (0 == strcasecmp(mode, "yuv422bt656")) {
760 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
761 0x00, 0x00, 0x00 };
762 mode = "422_ccir";
763 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
764 fdt_setprop_u32(blob, off, "vidout_trc", 1);
765 fdt_setprop_u32(blob, off, "vidout_blc", 1);
766 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
767 printf(" set HDMI input mode to %s\n", mode);
768 } else if (0 == strcasecmp(mode, "yuv422smp")) {
769 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
770 0x82, 0x81, 0x00 };
771 mode = "422_smp";
772 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
773 fdt_setprop_u32(blob, off, "vidout_trc", 0);
774 fdt_setprop_u32(blob, off, "vidout_blc", 0);
775 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
776 printf(" set HDMI input mode to %s\n", mode);
777 } else {
778 return -EINVAL;
779 }
780
781 return 0;
782}
783
f17a9af8
TH		 784/* enable a property of a node if the node is found */
785static inline void ft_enable_path(void *blob, const char *path)
786{
787 int i = fdt_path_offset(blob, path);
788 if (i >= 0) {
789 debug("enabling %s\n", path);
790 fdt_status_okay(blob, i);
791 }
792}
793
34b080b7
TH		 794/* remove a property of a node if the node is found */
795static inline void ft_delprop_path(void *blob, const char *path,
796 const char *name)
797{
798 int i = fdt_path_offset(blob, path);
799 if (i) {
800 debug("removing %s/%s\n", path, name);
801 fdt_delprop(blob, i, name);
802 }
803}
804
59189a8b
TH		 805/*
806 * called prior to booting kernel or by 'fdt boardsetup' command
807 *
808 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
809 * - mtd partitions based on mtdparts/mtdids env
810 * - system-serial (board serial num from EEPROM)
811 * - board (full model from EEPROM)
812 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
813 */
e895a4b0 814int ft_board_setup(void *blob, bd_t *bd)
59189a8b 815{
59189a8b 816 struct ventana_board_info *info = &ventana_info;
9c0fe83e 817 struct ventana_eeprom_config *cfg;
59189a8b
TH		 818 struct node_info nodes[] = {
819 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
820 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
821 };
822 const char *model = getenv("model");
4569cd56 823 const char *display = getenv("display");
0c81b14f
TH		 824 int i;
825 char rev = 0;
826
827 /* determine board revision */
828 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
829 if (ventana_info.model[i] >= 'A') {
830 rev = ventana_info.model[i];
831 break;
832 }
833 }
59189a8b
TH		 834
835 if (getenv("fdt_noauto")) {
836 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
e895a4b0 837 return 0;
59189a8b
TH		 838 }
839
c2fd3f57
TH		 840 if (test_bit(EECONFIG_NAND, info->config)) {
841 /* Update partition nodes using info from mtdparts env var */
842 puts(" Updating MTD partitions...\n");
843 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
844 }
59189a8b 845
4569cd56
TH		 846 /* Update display timings from display env var */
847 if (display) {
848 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
849 display) >= 0)
850 printf(" Set display timings for %s...\n", display);
851 }
852
59189a8b
TH		 853 printf(" Adjusting FDT per EEPROM for %s...\n", model);
854
855 /* board serial number */
856 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
483a435d 857 strlen(getenv("serial#")) + 1);
59189a8b
TH		 858
859 /* board (model contains model from device-tree) */
860 fdt_setprop(blob, 0, "board", info->model,
861 strlen((const char *)info->model) + 1);
862
a2559f11
TH		 863 /* set desired digital video capture format */
864 ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
865
95069704
TH		 866 /*
867 * disable serial2 node for GW54xx for compatibility with older
868 * 3.10.x kernel that improperly had this node enabled in the DT
869 */
870 if (board_type == GW54xx) {
871 i = fdt_path_offset(blob,
872 "/soc/aips-bus@02100000/serial@021ec000");
873 if (i)
874 fdt_del_node(blob, i);
875 }
876
0c81b14f
TH		 877 /*
878 * disable wdog1/wdog2 nodes for GW51xx below revC to work around
879 * errata causing wdog timer to be unreliable.
880 */
881 if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
882 i = fdt_path_offset(blob,
883 "/soc/aips-bus@02000000/wdog@020bc000");
884 if (i)
885 fdt_status_disabled(blob, i);
886 }
887
e9fc6d13
PS		 888 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
889 else if (board_type == GW52xx && info->model[4] == '2') {
890 u32 handle = 0;
891 u32 *range = NULL;
892
893 i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
894 if (i)
895 range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
896 NULL);
897
898 if (range) {
899 i = fdt_path_offset(blob,
900 "/soc/aips-bus@02000000/gpio@020a4000");
901 if (i)
902 handle = fdt_get_phandle(blob, i);
903 if (handle) {
904 range[0] = cpu_to_fdt32(handle);
905 range[1] = cpu_to_fdt32(23);
906 }
907 }
34b080b7
TH		 908
909 /* these have broken usd_vsel */
910 if (strstr((const char *)info->model, "SP318-B") ||
911 strstr((const char *)info->model, "SP331-B"))
912 gpio_cfg[board_type].usd_vsel = 0;
e9fc6d13
PS		 913 }
914
eeca451a
TH		 915 /*
916 * isolate CSI0_DATA_EN for GW551x below revB to work around
917 * errata causing non functional digital video in (it is not hooked up)
918 */
919 else if (board_type == GW551x && rev == 'A') {
920 u32 *range = NULL;
921 int len;
922 const u32 *handle = NULL;
923
924 i = fdt_node_offset_by_compatible(blob, -1,
925 "fsl,imx-tda1997x-video");
926 if (i)
927 handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
928 if (handle)
929 i = fdt_node_offset_by_phandle(blob,
930 fdt32_to_cpu(*handle));
931 if (i)
932 range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
933 if (range) {
934 len /= sizeof(u32);
935 for (i = 0; i < len; i += 6) {
936 u32 mux_reg = fdt32_to_cpu(range[i+0]);
937 u32 conf_reg = fdt32_to_cpu(range[i+1]);
938 /* mux PAD_CSI0_DATA_EN to GPIO */
939 if (is_cpu_type(MXC_CPU_MX6Q) &&
940 mux_reg == 0x260 && conf_reg == 0x630)
941 range[i+3] = cpu_to_fdt32(0x5);
942 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
943 mux_reg == 0x08c && conf_reg == 0x3a0)
944 range[i+3] = cpu_to_fdt32(0x5);
945 }
946 fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
947 }
18b3a91a
TH		 948
949 /* set BT656 video format */
950 ft_sethdmiinfmt(blob, "yuv422bt656");
eeca451a
TH		 951 }
952
f17a9af8
TH		 953 /* Configure DIO */
954 for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) {
955 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
956 char arg[10];
957
958 sprintf(arg, "dio%d", i);
959 if (!hwconfig(arg))
960 continue;
961 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
962 {
963 char path[48];
964 sprintf(path, "/soc/aips-bus@02000000/pwm@%08x",
965 0x02080000 + (0x4000 * (cfg->pwm_param - 1)));
966 printf(" Enabling pwm%d for DIO%d\n",
967 cfg->pwm_param, i);
968 ft_enable_path(blob, path);
969 }
970 }
971
34b080b7
TH		 972 /* remove no-1-8-v if UHS-I support is present */
973 if (gpio_cfg[board_type].usd_vsel) {
974 debug("Enabling UHS-I support\n");
975 ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000",
976 "no-1-8-v");
977 }
978
59189a8b
TH		 979 /*
980 * Peripheral Config:
981 * remove nodes by alias path if EEPROM config tells us the
982 * peripheral is not loaded on the board.
983 */
9c0fe83e
TH		 984 if (getenv("fdt_noconfig")) {
985 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
e895a4b0 986 return 0;
9c0fe83e
TH		 987 }
988 cfg = econfig;
989 while (cfg->name) {
990 if (!test_bit(cfg->bit, info->config)) {
991 fdt_del_node_and_alias(blob, cfg->dtalias ?
992 cfg->dtalias : cfg->name);
993 }
994 cfg++;
59189a8b 995 }
e895a4b0
SG		 996
997 return 0;
59189a8b
TH		 998}
999#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1000
d41c8c8e
TH		 1001static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1002 .reg = (struct mxc_uart *)UART2_BASE,
1003};
1004
1005U_BOOT_DEVICE(ventana_serial) = {
1006 .name = "serial_mxc",
1007 .platdata = &ventana_mxc_serial_plat,
1008};
"Das U-Boot" Source Tree