[people/ms/u-boot.git] / board / gateworks / gw_ventana / gw_ventana_spl.c

/*
 * Copyright (C) 2014 Gateworks Corporation
 * Author: Tim Harvey <tharvey@gateworks.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <spl.h>

#include "ventana_eeprom.h"

DECLARE_GLOBAL_DATA_PTR;

#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
#define I2C_GSC			0
#define GSC_EEPROM_ADDR		0x51
#define GSC_EEPROM_DDR_SIZE	0x2B	/* enum (512,1024,2048) MB */
#define GSC_EEPROM_DDR_WIDTH	0x2D	/* enum (32,64) bit */
#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
#define CONFIG_SYS_I2C_SPEED	100000

/* I2C1: GSC */
static struct i2c_pads_info mx6q_i2c_pad_info0 = {
	.scl = {
		.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
		.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
		.gp = IMX_GPIO_NR(3, 21)
	},
	.sda = {
		.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
		.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
		.gp = IMX_GPIO_NR(3, 28)
	}
};
static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
	.scl = {
		.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
		.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
		.gp = IMX_GPIO_NR(3, 21)
	},
	.sda = {
		.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
		.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
		.gp = IMX_GPIO_NR(3, 28)
	}
};

static void i2c_setup_iomux(void)
{
	if (is_cpu_type(MXC_CPU_MX6Q))
		setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
	else
		setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
}

/* configure MX6Q/DUAL mmdc DDR io registers */
struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
	.dram_sdclk_0 = 0x00020030,
	.dram_sdclk_1 = 0x00020030,
	.dram_cas = 0x00020030,
	.dram_ras = 0x00020030,
	.dram_reset = 0x00020030,
	/* SDCKE[0:1]: 100k pull-up */
	.dram_sdcke0 = 0x00003000,
	.dram_sdcke1 = 0x00003000,
	/* SDBA2: pull-up disabled */
	.dram_sdba2 = 0x00000000,
	/* SDODT[0:1]: 100k pull-up, 40 ohm */
	.dram_sdodt0 = 0x00003030,
	.dram_sdodt1 = 0x00003030,
	/* SDQS[0:7]: Differential input, 40 ohm */
	.dram_sdqs0 = 0x00000030,
	.dram_sdqs1 = 0x00000030,
	.dram_sdqs2 = 0x00000030,
	.dram_sdqs3 = 0x00000030,
	.dram_sdqs4 = 0x00000030,
	.dram_sdqs5 = 0x00000030,
	.dram_sdqs6 = 0x00000030,
	.dram_sdqs7 = 0x00000030,

	/* DQM[0:7]: Differential input, 40 ohm */
	.dram_dqm0 = 0x00020030,
	.dram_dqm1 = 0x00020030,
	.dram_dqm2 = 0x00020030,
	.dram_dqm3 = 0x00020030,
	.dram_dqm4 = 0x00020030,
	.dram_dqm5 = 0x00020030,
	.dram_dqm6 = 0x00020030,
	.dram_dqm7 = 0x00020030,
};

/* configure MX6Q/DUAL mmdc GRP io registers */
struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	/* DDR3 */
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	/* disable DDR pullups */
	.grp_ddrpke = 0x00000000,
	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
	.grp_addds = 0x00000030,
	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
	.grp_ctlds = 0x00000030,
	/* DATA[00:63]: Differential input, 40 ohm */
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_b2ds = 0x00000030,
	.grp_b3ds = 0x00000030,
	.grp_b4ds = 0x00000030,
	.grp_b5ds = 0x00000030,
	.grp_b6ds = 0x00000030,
	.grp_b7ds = 0x00000030,
};

/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
	.dram_sdclk_0 = 0x00020030,
	.dram_sdclk_1 = 0x00020030,
	.dram_cas = 0x00020030,
	.dram_ras = 0x00020030,
	.dram_reset = 0x00020030,
	/* SDCKE[0:1]: 100k pull-up */
	.dram_sdcke0 = 0x00003000,
	.dram_sdcke1 = 0x00003000,
	/* SDBA2: pull-up disabled */
	.dram_sdba2 = 0x00000000,
	/* SDODT[0:1]: 100k pull-up, 40 ohm */
	.dram_sdodt0 = 0x00003030,
	.dram_sdodt1 = 0x00003030,
	/* SDQS[0:7]: Differential input, 40 ohm */
	.dram_sdqs0 = 0x00000030,
	.dram_sdqs1 = 0x00000030,
	.dram_sdqs2 = 0x00000030,
	.dram_sdqs3 = 0x00000030,
	.dram_sdqs4 = 0x00000030,
	.dram_sdqs5 = 0x00000030,
	.dram_sdqs6 = 0x00000030,
	.dram_sdqs7 = 0x00000030,

	/* DQM[0:7]: Differential input, 40 ohm */
	.dram_dqm0 = 0x00020030,
	.dram_dqm1 = 0x00020030,
	.dram_dqm2 = 0x00020030,
	.dram_dqm3 = 0x00020030,
	.dram_dqm4 = 0x00020030,
	.dram_dqm5 = 0x00020030,
	.dram_dqm6 = 0x00020030,
	.dram_dqm7 = 0x00020030,
};

/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	/* DDR3 */
	.grp_ddr_type = 0x000c0000,
	/* SDQS[0:7]: Differential input, 40 ohm */
	.grp_ddrmode_ctl = 0x00020000,
	/* disable DDR pullups */
	.grp_ddrpke = 0x00000000,
	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
	.grp_addds = 0x00000030,
	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
	.grp_ctlds = 0x00000030,
	/* DATA[00:63]: Differential input, 40 ohm */
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_b2ds = 0x00000030,
	.grp_b3ds = 0x00000030,
	.grp_b4ds = 0x00000030,
	.grp_b5ds = 0x00000030,
	.grp_b6ds = 0x00000030,
	.grp_b7ds = 0x00000030,
};

/* MT41K128M16JT-125 (2Gb density) */
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
	.mem_speed = 1600,
	.density = 2,
	.width = 16,
	.banks = 8,
	.rowaddr = 14,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/* MT41K256M16HA-125 (4Gb density) */
static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
	.mem_speed = 1600,
	.density = 4,
	.width = 16,
	.banks = 8,
	.rowaddr = 15,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/*
 * calibration - these are the various CPU/DDR3 combinations we support
 */

static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
};

static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
};

static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
};

static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
};

static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	.p0_mpwldectrl1 = 0x00140026,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	.p0_mpdgctrl1 = 0x433C034D,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
};

static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x003C003C,
	.p0_mpwldectrl1 = 0x001F002A,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x42410244,
	.p0_mpdgctrl1 = 0x4234023A,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x484A4C4B,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x33342B32,
};

static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	.p0_mpwldectrl1 = 0x00140026,
	.p1_mpwldectrl0 = 0x0021001C,
	.p1_mpwldectrl1 = 0x0011001D,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	.p0_mpdgctrl1 = 0x433C034D,
	.p1_mpdgctrl0 = 0x032C0324,
	.p1_mpdgctrl1 = 0x03310232,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	.p1_mprddlctl = 0x37343141,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
	.p1_mpwrdlctl = 0x42344438,
};

static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x003C003C,
	.p0_mpwldectrl1 = 0x001F002A,
	.p1_mpwldectrl0 = 0x00330038,
	.p1_mpwldectrl1 = 0x0022003F,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x42410244,
	.p0_mpdgctrl1 = 0x4234023A,
	.p1_mpdgctrl0 = 0x022D022D,
	.p1_mpdgctrl1 = 0x021C0228,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x484A4C4B,
	.p1_mprddlctl = 0x4B4D4E4B,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x33342B32,
	.p1_mpwrdlctl = 0x3933332B,
};

static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x001E001A,
	.p0_mpwldectrl1 = 0x0026001F,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43370349,
	.p0_mpdgctrl1 = 0x032D0327,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3D303639,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x32363934,
};

static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0X00480047,
	.p0_mpwldectrl1 = 0X003D003F,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0X423E0241,
	.p0_mpdgctrl1 = 0X022B022C,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0X49454A4A,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0X2E372C32,
};

static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0X00220021,
	.p0_mpwldectrl1 = 0X00200030,
	.p1_mpwldectrl0 = 0X002D0027,
	.p1_mpwldectrl1 = 0X00150026,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43330342,
	.p0_mpdgctrl1 = 0x0339034A,
	.p1_mpdgctrl0 = 0x032F0325,
	.p1_mpdgctrl1 = 0x032F022E,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0X3A2E3437,
	.p1_mprddlctl = 0X35312F3F,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0X33363B37,
	.p1_mpwrdlctl = 0X40304239,
};

static void spl_dram_init(int width, int size_mb, int board_model)
{
	struct mx6_ddr3_cfg *mem = NULL;
	struct mx6_mmdc_calibration *calib = NULL;
	struct mx6_ddr_sysinfo sysinfo = {
		/* width of data bus:0=16,1=32,2=64 */
		.dsize = width/32,
		/* config for full 4GB range so that get_mem_size() works */
		.cs_density = 32, /* 32Gb per CS */
		/* single chip select */
		.ncs = 1,
		.cs1_mirror = 0,
		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
#else
		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
#endif
		.walat = 1,	/* Write additional latency */
		.ralat = 5,	/* Read additional latency */
		.mif3_mode = 3,	/* Command prediction working mode */
		.bi_on = 1,	/* Bank interleaving enabled */
		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
	};

	/*
	 * MMDC Calibration requires the following data:
	 *   mx6_mmdc_calibration - board-specific calibration (routing delays)
	 *      these calibration values depend on board routing, SoC, and DDR
	 *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
	 *   mx6_ddr_cfg - chip specific timing/layout details
	 */
	if (width == 16 && size_mb == 256) {
		mem = &mt41k128m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_128x16_mmdc_calib;
		else
			calib = &mx6sdl_128x16_mmdc_calib;
		debug("2gB density\n");
	} else if (width == 16 && size_mb == 512) {
		mem = &mt41k256m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_256x16_mmdc_calib;
		else
			calib = &mx6sdl_256x16_mmdc_calib;
		debug("4gB density\n");
	} else if (width == 32 && size_mb == 512) {
		mem = &mt41k128m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_128x32_mmdc_calib;
		else
			calib = &mx6sdl_128x32_mmdc_calib;
		debug("2gB density\n");
	} else if (width == 64 && size_mb == 1024) {
		mem = &mt41k128m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_128x64_mmdc_calib;
		else
			calib = &mx6sdl_128x64_mmdc_calib;
		debug("2gB density\n");
	} else if (width == 32 && size_mb == 1024) {
		mem = &mt41k256m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_256x32_mmdc_calib;
		else
			calib = &mx6sdl_256x32_mmdc_calib;
		debug("4gB density\n");
	} else if (width == 64 && size_mb == 2048) {
		mem = &mt41k256m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_256x64_mmdc_calib;
		debug("4gB density\n");
	}

	if (!mem) {
		puts("Error: Invalid Memory Configuration\n");
		hang();
	}
	if (!calib) {
		puts("Error: Invalid Board Calibration Configuration\n");
		hang();
	}

	if (is_cpu_type(MXC_CPU_MX6Q))
		mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
				 &mx6dq_grp_ioregs);
	else
		mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
				  &mx6sdl_grp_ioregs);
	mx6_dram_cfg(&sysinfo, calib, mem);
}

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00C03F3F, &ccm->CCGR0);
	writel(0x0030FC03, &ccm->CCGR1);
	writel(0x0FFFC000, &ccm->CCGR2);
	writel(0x3FF00000, &ccm->CCGR3);
	writel(0xFFFFF300, &ccm->CCGR4);	/* enable NAND/GPMI/BCH clks */
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003FF, &ccm->CCGR6);
}

static void gpr_init(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* enable AXI cache for VDOA/VPU/IPU */
	writel(0xF00000CF, &iomux->gpr[4]);
	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	writel(0x007F007F, &iomux->gpr[6]);
	writel(0x007F007F, &iomux->gpr[7]);
}

/*
 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 * - we have a stack and a place to store GD, both in SRAM
 * - no variable global data is available
 */
void board_init_f(ulong dummy)
{
	struct ventana_board_info ventana_info;
	int board_model;

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	ccgr_init();
	gpr_init();

	/* iomux and setup of i2c */
	board_early_init_f();
	i2c_setup_iomux();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* read/validate EEPROM info to determine board model and SDRAM cfg */
	board_model = read_eeprom(I2C_GSC, &ventana_info);

	/* provide some some default: 32bit 128MB */
	if (GW_UNKNOWN == board_model) {
		ventana_info.sdram_width = 2;
		ventana_info.sdram_size = 3;
	}

	/* configure MMDC for SDRAM width/size and per-model calibration */
	spl_dram_init(8 << ventana_info.sdram_width,
		      16 << ventana_info.sdram_size,
		      board_model);

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}

void reset_cpu(ulong addr)
{
}
Commit	Line	Data
0cc11dea TH	1	/*
	2	* Copyright (C) 2014 Gateworks Corporation
	3	* Author: Tim Harvey <tharvey@gateworks.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <i2c.h>
	10	#include <asm/io.h>
e25fbe3f	11	#include <asm/arch/crm_regs.h>
0cc11dea TH	12	#include <asm/arch/iomux.h>
	13	#include <asm/arch/mx6-ddr.h>
	14	#include <asm/arch/mx6-pins.h>
	15	#include <asm/arch/sys_proto.h>
	16	#include <asm/imx-common/boot_mode.h>
	17	#include <asm/imx-common/iomux-v3.h>
	18	#include <asm/imx-common/mxc_i2c.h>
	19	#include <spl.h>
	20
	21	#include "ventana_eeprom.h"
	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
	25	#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
	26	#define I2C_GSC 0
	27	#define GSC_EEPROM_ADDR 0x51
	28	#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
	29	#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
	30	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	31	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	32	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	33	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	34	#define CONFIG_SYS_I2C_SPEED 100000
	35
	36	/* I2C1: GSC */
	37	static struct i2c_pads_info mx6q_i2c_pad_info0 = {
	38	.scl = {
	39	.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL \| PC,
	40	.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 \| PC,
	41	.gp = IMX_GPIO_NR(3, 21)
	42	},
	43	.sda = {
	44	.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA \| PC,
	45	.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 \| PC,
	46	.gp = IMX_GPIO_NR(3, 28)
	47	}
	48	};
	49	static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
	50	.scl = {
	51	.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL \| PC,
	52	.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 \| PC,
	53	.gp = IMX_GPIO_NR(3, 21)
	54	},
	55	.sda = {
	56	.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA \| PC,
	57	.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 \| PC,
	58	.gp = IMX_GPIO_NR(3, 28)
	59	}
	60	};
	61
	62	static void i2c_setup_iomux(void)
	63	{
	64	if (is_cpu_type(MXC_CPU_MX6Q))
	65	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
	66	else
	67	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
	68	}
	69
	70	/* configure MX6Q/DUAL mmdc DDR io registers */
	71	struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	72	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
	73	.dram_sdclk_0 = 0x00020030,
	74	.dram_sdclk_1 = 0x00020030,
	75	.dram_cas = 0x00020030,
76	.dram_ras = 0x00020030,
77	.dram_reset = 0x00020030,
78	/* SDCKE[0:1]: 100k pull-up */
79	.dram_sdcke0 = 0x00003000,
80	.dram_sdcke1 = 0x00003000,
81	/* SDBA2: pull-up disabled */
82	.dram_sdba2 = 0x00000000,
83	/* SDODT[0:1]: 100k pull-up, 40 ohm */
84	.dram_sdodt0 = 0x00003030,
85	.dram_sdodt1 = 0x00003030,
86	/* SDQS[0:7]: Differential input, 40 ohm */
87	.dram_sdqs0 = 0x00000030,
88	.dram_sdqs1 = 0x00000030,
89	.dram_sdqs2 = 0x00000030,
90	.dram_sdqs3 = 0x00000030,
91	.dram_sdqs4 = 0x00000030,
92	.dram_sdqs5 = 0x00000030,
93	.dram_sdqs6 = 0x00000030,
94	.dram_sdqs7 = 0x00000030,
95
96	/* DQM[0:7]: Differential input, 40 ohm */
97	.dram_dqm0 = 0x00020030,
98	.dram_dqm1 = 0x00020030,
99	.dram_dqm2 = 0x00020030,
100	.dram_dqm3 = 0x00020030,
101	.dram_dqm4 = 0x00020030,
102	.dram_dqm5 = 0x00020030,
103	.dram_dqm6 = 0x00020030,
104	.dram_dqm7 = 0x00020030,
105	};
106
107	/* configure MX6Q/DUAL mmdc GRP io registers */
108	struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
109	/* DDR3 */
110	.grp_ddr_type = 0x000c0000,
111	.grp_ddrmode_ctl = 0x00020000,
112	/* disable DDR pullups */
113	.grp_ddrpke = 0x00000000,
114	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
115	.grp_addds = 0x00000030,
116	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
117	.grp_ctlds = 0x00000030,
118	/* DATA[00:63]: Differential input, 40 ohm */
119	.grp_ddrmode = 0x00020000,
120	.grp_b0ds = 0x00000030,
121	.grp_b1ds = 0x00000030,
122	.grp_b2ds = 0x00000030,
123	.grp_b3ds = 0x00000030,
124	.grp_b4ds = 0x00000030,
125	.grp_b5ds = 0x00000030,
126	.grp_b6ds = 0x00000030,
127	.grp_b7ds = 0x00000030,
128	};
129
130	/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
131	struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
132	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
133	.dram_sdclk_0 = 0x00020030,
134	.dram_sdclk_1 = 0x00020030,
135	.dram_cas = 0x00020030,
136	.dram_ras = 0x00020030,
137	.dram_reset = 0x00020030,
138	/* SDCKE[0:1]: 100k pull-up */
139	.dram_sdcke0 = 0x00003000,
140	.dram_sdcke1 = 0x00003000,
141	/* SDBA2: pull-up disabled */
142	.dram_sdba2 = 0x00000000,
143	/* SDODT[0:1]: 100k pull-up, 40 ohm */
144	.dram_sdodt0 = 0x00003030,
145	.dram_sdodt1 = 0x00003030,
146	/* SDQS[0:7]: Differential input, 40 ohm */
147	.dram_sdqs0 = 0x00000030,
148	.dram_sdqs1 = 0x00000030,
149	.dram_sdqs2 = 0x00000030,
150	.dram_sdqs3 = 0x00000030,
151	.dram_sdqs4 = 0x00000030,
152	.dram_sdqs5 = 0x00000030,
153	.dram_sdqs6 = 0x00000030,
154	.dram_sdqs7 = 0x00000030,
155
156	/* DQM[0:7]: Differential input, 40 ohm */
157	.dram_dqm0 = 0x00020030,
158	.dram_dqm1 = 0x00020030,
159	.dram_dqm2 = 0x00020030,
160	.dram_dqm3 = 0x00020030,
161	.dram_dqm4 = 0x00020030,
162	.dram_dqm5 = 0x00020030,
163	.dram_dqm6 = 0x00020030,
164	.dram_dqm7 = 0x00020030,
165	};
166
167	/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
168	struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
169	/* DDR3 */
170	.grp_ddr_type = 0x000c0000,
171	/* SDQS[0:7]: Differential input, 40 ohm */
172	.grp_ddrmode_ctl = 0x00020000,
173	/* disable DDR pullups */
174	.grp_ddrpke = 0x00000000,
175	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
176	.grp_addds = 0x00000030,
177	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
178	.grp_ctlds = 0x00000030,
179	/* DATA[00:63]: Differential input, 40 ohm */
180	.grp_ddrmode = 0x00020000,
181	.grp_b0ds = 0x00000030,
182	.grp_b1ds = 0x00000030,
183	.grp_b2ds = 0x00000030,
184	.grp_b3ds = 0x00000030,
185	.grp_b4ds = 0x00000030,
186	.grp_b5ds = 0x00000030,
187	.grp_b6ds = 0x00000030,
188	.grp_b7ds = 0x00000030,
189	};
190
b0b83347	191	/* MT41K128M16JT-125 (2Gb density) */
0cc11dea TH	192	static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
	193	.mem_speed = 1600,
	194	.density = 2,
	195	.width = 16,
	196	.banks = 8,
	197	.rowaddr = 14,
	198	.coladdr = 10,
	199	.pagesz = 2,
	200	.trcd = 1375,
	201	.trcmin = 4875,
	202	.trasmin = 3500,
	203	};
	204
b0b83347	205	/* MT41K256M16HA-125 (4Gb density) */
c91e4b8b TH	206	static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
	207	.mem_speed = 1600,
	208	.density = 4,
	209	.width = 16,
	210	.banks = 8,
	211	.rowaddr = 15,
	212	.coladdr = 10,
	213	.pagesz = 2,
	214	.trcd = 1375,
	215	.trcmin = 4875,
	216	.trasmin = 3500,
	217	};
	218
	219	/*
	220	* calibration - these are the various CPU/DDR3 combinations we support
	221	*/
	222
75f21e31 TH	223	static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = {
	224	/* write leveling calibration determine */
	225	.p0_mpwldectrl0 = 0x00190017,
	226	/* Read DQS Gating calibration */
	227	.p0_mpdgctrl0 = 0x43380347,
	228	/* Read Calibration: DQS delay relative to DQ read access */
	229	.p0_mprddlctl = 0x3C313539,
	230	/* Write Calibration: DQ/DM delay relative to DQS write access */
	231	.p0_mpwrdlctl = 0x36393C39,
	232	};
	233
	234	static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
	235	/* write leveling calibration determine */
	236	.p0_mpwldectrl0 = 0x00190017,
	237	/* Read DQS Gating calibration */
	238	.p0_mpdgctrl0 = 0x43380347,
	239	/* Read Calibration: DQS delay relative to DQ read access */
	240	.p0_mprddlctl = 0x3C313539,
	241	/* Write Calibration: DQ/DM delay relative to DQS write access */
	242	.p0_mpwrdlctl = 0x36393C39,
	243	};
	244
	245	static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = {
	246	/* write leveling calibration determine */
	247	.p0_mpwldectrl0 = 0x00190017,
	248	/* Read DQS Gating calibration */
	249	.p0_mpdgctrl0 = 0x43380347,
	250	/* Read Calibration: DQS delay relative to DQ read access */
	251	.p0_mprddlctl = 0x3C313539,
	252	/* Write Calibration: DQ/DM delay relative to DQS write access */
	253	.p0_mpwrdlctl = 0x36393C39,
	254	};
	255
	256	static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
	257	/* write leveling calibration determine */
	258	.p0_mpwldectrl0 = 0x00190017,
	259	/* Read DQS Gating calibration */
	260	.p0_mpdgctrl0 = 0x43380347,
	261	/* Read Calibration: DQS delay relative to DQ read access */
	262	.p0_mprddlctl = 0x3C313539,
	263	/* Write Calibration: DQ/DM delay relative to DQS write access */
	264	.p0_mpwrdlctl = 0x36393C39,
	265	};
	266
c91e4b8b	267	static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
0cc11dea	268	/* write leveling calibration determine */
c91e4b8b TH	269	.p0_mpwldectrl0 = 0x00190017,
c91e4b8b TH	270	.p0_mpwldectrl1 = 0x00140026,
0cc11dea	271	/* Read DQS Gating calibration */
c91e4b8b TH	272	.p0_mpdgctrl0 = 0x43380347,
c91e4b8b TH	273	.p0_mpdgctrl1 = 0x433C034D,
0cc11dea TH	274	/* Read Calibration: DQS delay relative to DQ read access */
0cc11dea TH	275	.p0_mprddlctl = 0x3C313539,
0cc11dea	276	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b TH	277	.p0_mpwrdlctl = 0x36393C39,
	278	};
	279
	280	static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
	281	/* write leveling calibration determine */
	282	.p0_mpwldectrl0 = 0x003C003C,
	283	.p0_mpwldectrl1 = 0x001F002A,
	284	/* Read DQS Gating calibration */
	285	.p0_mpdgctrl0 = 0x42410244,
	286	.p0_mpdgctrl1 = 0x4234023A,
	287	/* Read Calibration: DQS delay relative to DQ read access */
	288	.p0_mprddlctl = 0x484A4C4B,
	289	/* Write Calibration: DQ/DM delay relative to DQS write access */
	290	.p0_mpwrdlctl = 0x33342B32,
0cc11dea TH	291	};
0cc11dea TH	292
c91e4b8b	293	static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
0cc11dea	294	/* write leveling calibration determine */
c91e4b8b TH	295	.p0_mpwldectrl0 = 0x00190017,
	296	.p0_mpwldectrl1 = 0x00140026,
	297	.p1_mpwldectrl0 = 0x0021001C,
	298	.p1_mpwldectrl1 = 0x0011001D,
0cc11dea	299	/* Read DQS Gating calibration */
c91e4b8b TH	300	.p0_mpdgctrl0 = 0x43380347,
	301	.p0_mpdgctrl1 = 0x433C034D,
	302	.p1_mpdgctrl0 = 0x032C0324,
	303	.p1_mpdgctrl1 = 0x03310232,
0cc11dea	304	/* Read Calibration: DQS delay relative to DQ read access */
c91e4b8b TH	305	.p0_mprddlctl = 0x3C313539,
c91e4b8b TH	306	.p1_mprddlctl = 0x37343141,
0cc11dea	307	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b TH	308	.p0_mpwrdlctl = 0x36393C39,
c91e4b8b TH	309	.p1_mpwrdlctl = 0x42344438,
0cc11dea	310	};
c91e4b8b TH	311
c91e4b8b TH	312	static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
0cc11dea TH	313	/* write leveling calibration determine */
0cc11dea TH	314	.p0_mpwldectrl0 = 0x003C003C,
c91e4b8b TH	315	.p0_mpwldectrl1 = 0x001F002A,
c91e4b8b TH	316	.p1_mpwldectrl0 = 0x00330038,
0cc11dea TH	317	.p1_mpwldectrl1 = 0x0022003F,
	318	/* Read DQS Gating calibration */
	319	.p0_mpdgctrl0 = 0x42410244,
c91e4b8b TH	320	.p0_mpdgctrl1 = 0x4234023A,
c91e4b8b TH	321	.p1_mpdgctrl0 = 0x022D022D,
0cc11dea TH	322	.p1_mpdgctrl1 = 0x021C0228,
	323	/* Read Calibration: DQS delay relative to DQ read access */
	324	.p0_mprddlctl = 0x484A4C4B,
	325	.p1_mprddlctl = 0x4B4D4E4B,
	326	/* Write Calibration: DQ/DM delay relative to DQS write access */
	327	.p0_mpwrdlctl = 0x33342B32,
	328	.p1_mpwrdlctl = 0x3933332B,
	329	};
	330
c91e4b8b	331	static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
0cc11dea	332	/* write leveling calibration determine */
c91e4b8b TH	333	.p0_mpwldectrl0 = 0x001E001A,
c91e4b8b TH	334	.p0_mpwldectrl1 = 0x0026001F,
0cc11dea	335	/* Read DQS Gating calibration */
c91e4b8b TH	336	.p0_mpdgctrl0 = 0x43370349,
c91e4b8b TH	337	.p0_mpdgctrl1 = 0x032D0327,
0cc11dea	338	/* Read Calibration: DQS delay relative to DQ read access */
c91e4b8b	339	.p0_mprddlctl = 0x3D303639,
0cc11dea	340	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b	341	.p0_mpwrdlctl = 0x32363934,
0cc11dea TH	342	};
0cc11dea TH	343
b0b83347 TH	344	static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
	345	/* write leveling calibration determine */
	346	.p0_mpwldectrl0 = 0X00480047,
	347	.p0_mpwldectrl1 = 0X003D003F,
	348	/* Read DQS Gating calibration */
	349	.p0_mpdgctrl0 = 0X423E0241,
	350	.p0_mpdgctrl1 = 0X022B022C,
	351	/* Read Calibration: DQS delay relative to DQ read access */
	352	.p0_mprddlctl = 0X49454A4A,
	353	/* Write Calibration: DQ/DM delay relative to DQS write access */
	354	.p0_mpwrdlctl = 0X2E372C32,
	355	};
	356
c91e4b8b	357	static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
0cc11dea	358	/* write leveling calibration determine */
c91e4b8b TH	359	.p0_mpwldectrl0 = 0X00220021,
	360	.p0_mpwldectrl1 = 0X00200030,
	361	.p1_mpwldectrl0 = 0X002D0027,
	362	.p1_mpwldectrl1 = 0X00150026,
0cc11dea	363	/* Read DQS Gating calibration */
c91e4b8b TH	364	.p0_mpdgctrl0 = 0x43330342,
	365	.p0_mpdgctrl1 = 0x0339034A,
	366	.p1_mpdgctrl0 = 0x032F0325,
	367	.p1_mpdgctrl1 = 0x032F022E,
0cc11dea	368	/* Read Calibration: DQS delay relative to DQ read access */
c91e4b8b TH	369	.p0_mprddlctl = 0X3A2E3437,
c91e4b8b TH	370	.p1_mprddlctl = 0X35312F3F,
0cc11dea	371	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b TH	372	.p0_mpwrdlctl = 0X33363B37,
c91e4b8b TH	373	.p1_mpwrdlctl = 0X40304239,
0cc11dea TH	374	};
0cc11dea TH	375
c91e4b8b	376	static void spl_dram_init(int width, int size_mb, int board_model)
0cc11dea	377	{
c91e4b8b TH	378	struct mx6_ddr3_cfg *mem = NULL;
c91e4b8b TH	379	struct mx6_mmdc_calibration *calib = NULL;
0cc11dea TH	380	struct mx6_ddr_sysinfo sysinfo = {
	381	/* width of data bus:0=16,1=32,2=64 */
	382	.dsize = width/32,
	383	/* config for full 4GB range so that get_mem_size() works */
	384	.cs_density = 32, /* 32Gb per CS */
	385	/* single chip select */
	386	.ncs = 1,
	387	.cs1_mirror = 0,
	388	.rtt_wr = 1 /DDR3_RTT_60_OHM/, /* RTT_Wr = RZQ/4 */
	389	#ifdef RTT_NOM_120OHM
	390	.rtt_nom = 2 /DDR3_RTT_120_OHM/, /* RTT_Nom = RZQ/2 */
	391	#else
	392	.rtt_nom = 1 /DDR3_RTT_60_OHM/, /* RTT_Nom = RZQ/4 */
	393	#endif
	394	.walat = 1, /* Write additional latency */
	395	.ralat = 5, /* Read additional latency */
	396	.mif3_mode = 3, /* Command prediction working mode */
	397	.bi_on = 1, /* Bank interleaving enabled */
	398	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
	399	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
29f0d6b1	400	.pd_fast_exit = 1, /* enable precharge power-down fast exit */
0cc11dea TH	401	};
	402
	403	/*
	404	* MMDC Calibration requires the following data:
	405	* mx6_mmdc_calibration - board-specific calibration (routing delays)
c91e4b8b	406	* these calibration values depend on board routing, SoC, and DDR
0cc11dea TH	407	* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
	408	* mx6_ddr_cfg - chip specific timing/layout details
	409	*/
75f21e31 TH	410	if (width == 16 && size_mb == 256) {
	411	mem = &mt41k128m16jt_125;
	412	if (is_cpu_type(MXC_CPU_MX6Q))
	413	calib = &mx6dq_128x16_mmdc_calib;
	414	else
	415	calib = &mx6sdl_128x16_mmdc_calib;
	416	debug("2gB density\n");
	417	} else if (width == 16 && size_mb == 512) {
	418	mem = &mt41k256m16ha_125;
	419	if (is_cpu_type(MXC_CPU_MX6Q))
	420	calib = &mx6dq_256x16_mmdc_calib;
	421	else
	422	calib = &mx6sdl_256x16_mmdc_calib;
	423	debug("4gB density\n");
	424	} else if (width == 32 && size_mb == 512) {
c91e4b8b	425	mem = &mt41k128m16jt_125;
0cc11dea	426	if (is_cpu_type(MXC_CPU_MX6Q))
c91e4b8b	427	calib = &mx6dq_128x32_mmdc_calib;
0cc11dea	428	else
c91e4b8b TH	429	calib = &mx6sdl_128x32_mmdc_calib;
	430	debug("2gB density\n");
	431	} else if (width == 64 && size_mb == 1024) {
	432	mem = &mt41k128m16jt_125;
0cc11dea	433	if (is_cpu_type(MXC_CPU_MX6Q))
c91e4b8b	434	calib = &mx6dq_128x64_mmdc_calib;
0cc11dea	435	else
c91e4b8b TH	436	calib = &mx6sdl_128x64_mmdc_calib;
	437	debug("2gB density\n");
	438	} else if (width == 32 && size_mb == 1024) {
	439	mem = &mt41k256m16ha_125;
	440	if (is_cpu_type(MXC_CPU_MX6Q))
	441	calib = &mx6dq_256x32_mmdc_calib;
b0b83347 TH	442	else
b0b83347 TH	443	calib = &mx6sdl_256x32_mmdc_calib;
c91e4b8b TH	444	debug("4gB density\n");
	445	} else if (width == 64 && size_mb == 2048) {
	446	mem = &mt41k256m16ha_125;
	447	if (is_cpu_type(MXC_CPU_MX6Q))
	448	calib = &mx6dq_256x64_mmdc_calib;
	449	debug("4gB density\n");
	450	}
	451
	452	if (!mem) {
	453	puts("Error: Invalid Memory Configuration\n");
	454	hang();
	455	}
	456	if (!calib) {
	457	puts("Error: Invalid Board Calibration Configuration\n");
	458	hang();
0cc11dea TH	459	}
	460
	461	if (is_cpu_type(MXC_CPU_MX6Q))
	462	mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
	463	&mx6dq_grp_ioregs);
	464	else
	465	mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
	466	&mx6sdl_grp_ioregs);
	467	mx6_dram_cfg(&sysinfo, calib, mem);
	468	}
	469
e25fbe3f FE	470	static void ccgr_init(void)
	471	{
	472	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	473
	474	writel(0x00C03F3F, &ccm->CCGR0);
	475	writel(0x0030FC03, &ccm->CCGR1);
	476	writel(0x0FFFC000, &ccm->CCGR2);
	477	writel(0x3FF00000, &ccm->CCGR3);
576cd6b3	478	writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
e25fbe3f FE	479	writel(0x0F0000C3, &ccm->CCGR5);
	480	writel(0x000003FF, &ccm->CCGR6);
	481	}
	482
	483	static void gpr_init(void)
	484	{
	485	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	486
	487	/* enable AXI cache for VDOA/VPU/IPU */
	488	writel(0xF00000CF, &iomux->gpr[4]);
	489	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	490	writel(0x007F007F, &iomux->gpr[6]);
	491	writel(0x007F007F, &iomux->gpr[7]);
	492	}
	493
0cc11dea TH	494	/*
	495	* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
	496	* - we have a stack and a place to store GD, both in SRAM
	497	* - no variable global data is available
	498	*/
	499	void board_init_f(ulong dummy)
	500	{
	501	struct ventana_board_info ventana_info;
	502	int board_model;
	503
0cc11dea TH	504	/* setup AIPS and disable watchdog */
	505	arch_cpu_init();
	506
e25fbe3f FE	507	ccgr_init();
	508	gpr_init();
	509
0cc11dea TH	510	/* iomux and setup of i2c */
	511	board_early_init_f();
	512	i2c_setup_iomux();
	513
	514	/* setup GP timer */
	515	timer_init();
	516
	517	/* UART clocks enabled and gd valid - init serial console */
	518	preloader_console_init();
	519
	520	/* read/validate EEPROM info to determine board model and SDRAM cfg */
	521	board_model = read_eeprom(I2C_GSC, &ventana_info);
	522
	523	/* provide some some default: 32bit 128MB */
	524	if (GW_UNKNOWN == board_model) {
	525	ventana_info.sdram_width = 2;
	526	ventana_info.sdram_size = 3;
	527	}
	528
	529	/* configure MMDC for SDRAM width/size and per-model calibration */
	530	spl_dram_init(8 << ventana_info.sdram_width,
	531	16 << ventana_info.sdram_size,
	532	board_model);
	533
	534	/* Clear the BSS. */
	535	memset(__bss_start, 0, __bss_end - __bss_start);
	536
	537	/* load/boot image from boot device */
	538	board_init_r(NULL, 0);
	539	}
	540
	541	void reset_cpu(ulong addr)
	542	{
	543	}