[people/ms/u-boot.git] / board / gateworks / gw_ventana / ventana_eeprom.h

/*
 * Copyright (C) 2013 Gateworks Corporation
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#ifndef _VENTANA_EEPROM_
#define _VENTANA_EEPROM_

struct ventana_board_info {
	u8 mac0[6];          /* 0x00: MAC1 */
	u8 mac1[6];          /* 0x06: MAC2 */
	u8 res0[12];         /* 0x0C: reserved */
	u32 serial;          /* 0x18: Serial Number (read only) */
	u8 res1[4];          /* 0x1C: reserved */
	u8 mfgdate[4];       /* 0x20: MFG date (read only) */
	u8 res2[7];          /* 0x24 */
	/* sdram config */
	u8 sdram_size;       /* 0x2B: (16 << n) MB */
	u8 sdram_speed;      /* 0x2C: (33.333 * n) MHz */
	u8 sdram_width;      /* 0x2D: (8 << n) bit */
	/* cpu config */
	u8 cpu_speed;        /* 0x2E: (33.333 * n) MHz */
	u8 cpu_type;         /* 0x2F: 7=imx6q, 8=imx6dl */
	u8 model[16];        /* 0x30: model string */
	/* FLASH config */
	u8 nand_flash_size;  /* 0x40: (8 << (n-1)) MB */
	u8 spi_flash_size;   /* 0x41: (4 << (n-1)) MB */

	/* Config1: SoC Peripherals */
	u8 config[8];        /* 0x42: loading options */

	u8 res3[4];          /* 0x4A */

	u8 chksum[2];        /* 0x4E */
};

/* config bits */
enum {
	EECONFIG_ETH0,
	EECONFIG_ETH1,
	EECONFIG_HDMI_OUT,
	EECONFIG_SATA,
	EECONFIG_PCIE,
	EECONFIG_SSI0,
	EECONFIG_SSI1,
	EECONFIG_LCD,
	EECONFIG_LVDS0,
	EECONFIG_LVDS1,
	EECONFIG_USB0,
	EECONFIG_USB1,
	EECONFIG_SD0,
	EECONFIG_SD1,
	EECONFIG_SD2,
	EECONFIG_SD3,
	EECONFIG_UART0,
	EECONFIG_UART1,
	EECONFIG_UART2,
	EECONFIG_UART3,
	EECONFIG_UART4,
	EECONFIG_IPU0,
	EECONFIG_IPU1,
	EECONFIG_FLEXCAN,
	EECONFIG_MIPI_DSI,
	EECONFIG_MIPI_CSI,
	EECONFIG_TZASC0,
	EECONFIG_TZASC1,
	EECONFIG_I2C0,
	EECONFIG_I2C1,
	EECONFIG_I2C2,
	EECONFIG_VPU,
	EECONFIG_CSI0,
	EECONFIG_CSI1,
	EECONFIG_CAAM,
	EECONFIG_MEZZ,
	EECONFIG_RES1,
	EECONFIG_RES2,
	EECONFIG_RES3,
	EECONFIG_RES4,
	EECONFIG_ESPCI0,
	EECONFIG_ESPCI1,
	EECONFIG_ESPCI2,
	EECONFIG_ESPCI3,
	EECONFIG_ESPCI4,
	EECONFIG_ESPCI5,
	EECONFIG_RES5,
	EECONFIG_RES6,
	EECONFIG_GPS,
	EECONFIG_SPIFL0,
	EECONFIG_SPIFL1,
	EECONFIG_GSPBATT,
	EECONFIG_HDMI_IN,
	EECONFIG_VID_OUT,
	EECONFIG_VID_IN,
	EECONFIG_NAND,
	EECONFIG_RES8,
	EECONFIG_RES9,
	EECONFIG_RES10,
	EECONFIG_RES11,
	EECONFIG_RES12,
	EECONFIG_RES13,
	EECONFIG_RES14,
	EECONFIG_RES15,
};

#endif
Commit	Line	Data
59189a8b TH	1	/*
	2	* Copyright (C) 2013 Gateworks Corporation
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _VENTANA_EEPROM_
	8	#define _VENTANA_EEPROM_
	9
	10	struct ventana_board_info {
	11	u8 mac0[6]; /* 0x00: MAC1 */
	12	u8 mac1[6]; /* 0x06: MAC2 */
	13	u8 res0[12]; /* 0x0C: reserved */
	14	u32 serial; /* 0x18: Serial Number (read only) */
	15	u8 res1[4]; /* 0x1C: reserved */
	16	u8 mfgdate[4]; /* 0x20: MFG date (read only) */
	17	u8 res2[7]; /* 0x24 */
	18	/* sdram config */
a594a6f1 TH	19	u8 sdram_size; /* 0x2B: (16 << n) MB */
	20	u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */
	21	u8 sdram_width; /* 0x2D: (8 << n) bit */
59189a8b	22	/* cpu config */
a594a6f1 TH	23	u8 cpu_speed; /* 0x2E: (33.333 * n) MHz */
a594a6f1 TH	24	u8 cpu_type; /* 0x2F: 7=imx6q, 8=imx6dl */
59189a8b TH	25	u8 model[16]; /* 0x30: model string */
59189a8b TH	26	/* FLASH config */
a594a6f1 TH	27	u8 nand_flash_size; /* 0x40: (8 << (n-1)) MB */
a594a6f1 TH	28	u8 spi_flash_size; /* 0x41: (4 << (n-1)) MB */
59189a8b TH	29
	30	/* Config1: SoC Peripherals */
	31	u8 config[8]; /* 0x42: loading options */
	32
	33	u8 res3[4]; /* 0x4A */
	34
	35	u8 chksum[2]; /* 0x4E */
	36	};
	37
	38	/* config bits */
	39	enum {
	40	EECONFIG_ETH0,
	41	EECONFIG_ETH1,
	42	EECONFIG_HDMI_OUT,
	43	EECONFIG_SATA,
	44	EECONFIG_PCIE,
	45	EECONFIG_SSI0,
	46	EECONFIG_SSI1,
	47	EECONFIG_LCD,
	48	EECONFIG_LVDS0,
	49	EECONFIG_LVDS1,
	50	EECONFIG_USB0,
	51	EECONFIG_USB1,
	52	EECONFIG_SD0,
	53	EECONFIG_SD1,
	54	EECONFIG_SD2,
	55	EECONFIG_SD3,
	56	EECONFIG_UART0,
	57	EECONFIG_UART1,
	58	EECONFIG_UART2,
	59	EECONFIG_UART3,
	60	EECONFIG_UART4,
	61	EECONFIG_IPU0,
	62	EECONFIG_IPU1,
	63	EECONFIG_FLEXCAN,
	64	EECONFIG_MIPI_DSI,
	65	EECONFIG_MIPI_CSI,
	66	EECONFIG_TZASC0,
	67	EECONFIG_TZASC1,
	68	EECONFIG_I2C0,
	69	EECONFIG_I2C1,
	70	EECONFIG_I2C2,
	71	EECONFIG_VPU,
	72	EECONFIG_CSI0,
	73	EECONFIG_CSI1,
	74	EECONFIG_CAAM,
	75	EECONFIG_MEZZ,
	76	EECONFIG_RES1,
	77	EECONFIG_RES2,
	78	EECONFIG_RES3,
	79	EECONFIG_RES4,
	80	EECONFIG_ESPCI0,
	81	EECONFIG_ESPCI1,
	82	EECONFIG_ESPCI2,
	83	EECONFIG_ESPCI3,
	84	EECONFIG_ESPCI4,
	85	EECONFIG_ESPCI5,
	86	EECONFIG_RES5,
	87	EECONFIG_RES6,
	88	EECONFIG_GPS,
	89	EECONFIG_SPIFL0,
	90	EECONFIG_SPIFL1,
	91	EECONFIG_GSPBATT,
	92	EECONFIG_HDMI_IN,
93	EECONFIG_VID_OUT,
94	EECONFIG_VID_IN,
95	EECONFIG_NAND,
96	EECONFIG_RES8,
97	EECONFIG_RES9,
98	EECONFIG_RES10,
99	EECONFIG_RES11,
100	EECONFIG_RES12,
101	EECONFIG_RES13,
102	EECONFIG_RES14,
103	EECONFIG_RES15,
104	};
105
106	#endif