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Commit | Line | Data |
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a605ea7e DE |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
a605ea7e DE |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <command.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/ppc4xx-gpio.h> | |
2da0fc0d | 13 | #include <asm/global_data.h> |
a605ea7e | 14 | |
6e9e6c36 | 15 | #include "405ep.h" |
2da0fc0d | 16 | #include <gdsys_fpga.h> |
a605ea7e | 17 | |
a605ea7e DE |
18 | #define REFLECTION_TESTPATTERN 0xdede |
19 | #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) | |
20 | ||
aba27acf DE |
21 | #ifdef CONFIG_SYS_FPGA_NO_RFL_HI |
22 | #define REFLECTION_TESTREG reflection_low | |
23 | #else | |
24 | #define REFLECTION_TESTREG reflection_high | |
25 | #endif | |
26 | ||
2da0fc0d DE |
27 | DECLARE_GLOBAL_DATA_PTR; |
28 | ||
29 | int get_fpga_state(unsigned dev) | |
30 | { | |
923a662f | 31 | return gd->arch.fpga_state[dev]; |
2da0fc0d DE |
32 | } |
33 | ||
a605ea7e DE |
34 | int board_early_init_f(void) |
35 | { | |
2da0fc0d | 36 | unsigned k; |
2da0fc0d DE |
37 | |
38 | for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) | |
923a662f | 39 | gd->arch.fpga_state[k] = 0; |
2da0fc0d | 40 | |
a605ea7e DE |
41 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
42 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ | |
43 | mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ | |
44 | mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ | |
45 | mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ | |
46 | mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ | |
47 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
48 | ||
49 | /* | |
50 | * EBC Configuration Register: set ready timeout to 512 ebc-clks | |
51 | * -> ca. 15 us | |
52 | */ | |
53 | mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ | |
6e9e6c36 DE |
54 | return 0; |
55 | } | |
a605ea7e | 56 | |
6e9e6c36 DE |
57 | int board_early_init_r(void) |
58 | { | |
59 | unsigned k; | |
60 | unsigned ctr; | |
a605ea7e | 61 | |
6e9e6c36 | 62 | for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) |
923a662f | 63 | gd->arch.fpga_state[k] = 0; |
a605ea7e DE |
64 | |
65 | /* | |
6e9e6c36 | 66 | * reset FPGA |
a605ea7e | 67 | */ |
6e9e6c36 DE |
68 | gd405ep_init(); |
69 | ||
70 | gd405ep_set_fpga_reset(1); | |
71 | ||
72 | gd405ep_setup_hw(); | |
73 | ||
2da0fc0d DE |
74 | for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { |
75 | ctr = 0; | |
6e9e6c36 | 76 | while (!gd405ep_get_fpga_done(k)) { |
2da0fc0d DE |
77 | udelay(100000); |
78 | if (ctr++ > 5) { | |
923a662f SG |
79 | gd->arch.fpga_state[k] |= |
80 | FPGA_STATE_DONE_FAILED; | |
2da0fc0d DE |
81 | break; |
82 | } | |
83 | } | |
84 | } | |
a605ea7e | 85 | |
a605ea7e | 86 | udelay(10); |
6e9e6c36 DE |
87 | |
88 | gd405ep_set_fpga_reset(0); | |
a605ea7e | 89 | |
2da0fc0d | 90 | for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { |
2da0fc0d DE |
91 | /* |
92 | * wait for fpga out of reset | |
93 | */ | |
94 | ctr = 0; | |
95 | while (1) { | |
aba27acf DE |
96 | u16 val; |
97 | ||
98 | FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); | |
5cb4100f | 99 | |
aba27acf DE |
100 | FPGA_GET_REG(k, REFLECTION_TESTREG, &val); |
101 | if (val == REFLECTION_TESTPATTERN_INV) | |
2da0fc0d | 102 | break; |
5cb4100f | 103 | |
2da0fc0d DE |
104 | udelay(100000); |
105 | if (ctr++ > 5) { | |
923a662f | 106 | gd->arch.fpga_state[k] |= |
2da0fc0d DE |
107 | FPGA_STATE_REFLECTION_FAILED; |
108 | break; | |
109 | } | |
110 | } | |
a605ea7e DE |
111 | } |
112 | ||
113 | return 0; | |
114 | } |