[people/ms/u-boot.git] / board / gdsys / 405ep / iocon.c

/*
 * (C) Copyright 2010
 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <errno.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>

#include "405ep.h"
#include <gdsys_fpga.h>

#include "../common/osd.h"
#include "../common/mclink.h"
#include "../common/phy.h"

#include <i2c.h>
#include <pca953x.h>
#include <pca9698.h>

#include <miiphy.h>

DECLARE_GLOBAL_DATA_PTR;

#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)

#define MAX_MUX_CHANNELS 2

enum {
	UNITTYPE_MAIN_SERVER = 0,
	UNITTYPE_MAIN_USER = 1,
	UNITTYPE_VIDEO_SERVER = 2,
	UNITTYPE_VIDEO_USER = 3,
};

enum {
	HWVER_100 = 0,
	HWVER_104 = 1,
	HWVER_110 = 2,
	HWVER_120 = 3,
	HWVER_200 = 4,
	HWVER_210 = 5,
	HWVER_220 = 6,
	HWVER_230 = 7,
};

enum {
	FPGA_HWVER_200 = 0,
	FPGA_HWVER_210 = 1,
};

enum {
	COMPRESSION_NONE = 0,
	COMPRESSION_TYPE1_DELTA = 1,
	COMPRESSION_TYPE1_TYPE2_DELTA = 3,
};

enum {
	AUDIO_NONE = 0,
	AUDIO_TX = 1,
	AUDIO_RX = 2,
	AUDIO_RXTX = 3,
};

enum {
	SYSCLK_147456 = 0,
};

enum {
	RAM_DDR2_32 = 0,
	RAM_DDR3_32 = 1,
};

enum {
	CARRIER_SPEED_1G = 0,
	CARRIER_SPEED_2_5G = 1,
};

enum {
	MCFPGA_DONE = 1 << 0,
	MCFPGA_INIT_N = 1 << 1,
	MCFPGA_PROGRAM_N = 1 << 2,
	MCFPGA_UPDATE_ENABLE_N = 1 << 3,
	MCFPGA_RESET_N = 1 << 4,
};

enum {
	GPIO_MDC = 1 << 14,
	GPIO_MDIO = 1 << 15,
};

unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;

int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
{
	int res;

	switch (fpga) {
	case 0:
		out_le16(reg, data);
		break;
	default:
		res = mclink_send(fpga - 1, regoff, data);
		if (res < 0) {
			printf("mclink_send reg %02lx data %04x returned %d\n",
			       regoff, data, res);
			return res;
		}
		break;
	}

	return 0;
}

int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
{
	int res;

	switch (fpga) {
	case 0:
		*data = in_le16(reg);
		break;
	default:
		if (fpga > mclink_fpgacount)
			return -EINVAL;
		res = mclink_receive(fpga - 1, regoff, data);
		if (res < 0) {
			printf("mclink_receive reg %02lx returned %d\n",
			       regoff, res);
			return res;
		}
	}

	return 0;
}

/*
 * Check Board Identity:
 */
int checkboard(void)
{
	char *s = getenv("serial#");

	puts("Board: ");

	puts("IoCon");

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}

	puts("\n");

	return 0;
}

static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
{
	u16 versions;
	u16 fpga_version;
	u16 fpga_features;
	unsigned unit_type;
	unsigned hardware_version;
	unsigned feature_compression;
	unsigned feature_osd;
	unsigned feature_audio;
	unsigned feature_sysclock;
	unsigned feature_ramconfig;
	unsigned feature_carrier_speed;
	unsigned feature_carriers;
	unsigned feature_video_channels;

	int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM;

	FPGA_GET_REG(fpga, versions, &versions);
	FPGA_GET_REG(fpga, fpga_version, &fpga_version);
	FPGA_GET_REG(fpga, fpga_features, &fpga_features);

	unit_type = (versions & 0xf000) >> 12;
	feature_compression = (fpga_features & 0xe000) >> 13;
	feature_osd = fpga_features & (1<<11);
	feature_audio = (fpga_features & 0x0600) >> 9;
	feature_sysclock = (fpga_features & 0x0180) >> 7;
	feature_ramconfig = (fpga_features & 0x0060) >> 5;
	feature_carrier_speed = fpga_features & (1<<4);
	feature_carriers = (fpga_features & 0x000c) >> 2;
	feature_video_channels = fpga_features & 0x0003;

	if (legacy)
		printf("legacy ");

	switch (unit_type) {
	case UNITTYPE_MAIN_USER:
		printf("Mainchannel");
		break;

	case UNITTYPE_VIDEO_USER:
		printf("Videochannel");
		break;

	default:
		printf("UnitType %d(not supported)", unit_type);
		break;
	}

	if (unit_type == UNITTYPE_MAIN_USER) {
		if (legacy)
			hardware_version =
				(in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
		else
			hardware_version =
				  (!!pca9698_get_value(0x20, 24) << 0)
				| (!!pca9698_get_value(0x20, 25) << 1)
				| (!!pca9698_get_value(0x20, 26) << 2)
				| (!!pca9698_get_value(0x20, 27) << 3);
		switch (hardware_version) {
		case HWVER_100:
			printf(" HW-Ver 1.00,");
			break;

		case HWVER_104:
			printf(" HW-Ver 1.04,");
			break;

		case HWVER_110:
			printf(" HW-Ver 1.10,");
			break;

		case HWVER_120:
			printf(" HW-Ver 1.20-1.21,");
			break;

		case HWVER_200:
			printf(" HW-Ver 2.00,");
			break;

		case HWVER_210:
			printf(" HW-Ver 2.10,");
			break;

		case HWVER_220:
			printf(" HW-Ver 2.20,");
			break;

		case HWVER_230:
			printf(" HW-Ver 2.30,");
			break;

		default:
			printf(" HW-Ver %d(not supported),",
			       hardware_version);
			break;
		}
		if (rgmii2_present)
			printf(" RGMII2,");
	}

	if (unit_type == UNITTYPE_VIDEO_USER) {
		hardware_version = versions & 0x000f;
		switch (hardware_version) {
		case FPGA_HWVER_200:
			printf(" HW-Ver 2.00,");
			break;

		case FPGA_HWVER_210:
			printf(" HW-Ver 2.10,");
			break;

		default:
			printf(" HW-Ver %d(not supported),",
			       hardware_version);
			break;
		}
	}

	printf(" FPGA V %d.%02d\n       features:",
	       fpga_version / 100, fpga_version % 100);


	switch (feature_compression) {
	case COMPRESSION_NONE:
		printf(" no compression");
		break;

	case COMPRESSION_TYPE1_DELTA:
		printf(" type1-deltacompression");
		break;

	case COMPRESSION_TYPE1_TYPE2_DELTA:
		printf(" type1-deltacompression, type2-inlinecompression");
		break;

	default:
		printf(" compression %d(not supported)", feature_compression);
		break;
	}

	printf(", %sosd", feature_osd ? "" : "no ");

	switch (feature_audio) {
	case AUDIO_NONE:
		printf(", no audio");
		break;

	case AUDIO_TX:
		printf(", audio tx");
		break;

	case AUDIO_RX:
		printf(", audio rx");
		break;

	case AUDIO_RXTX:
		printf(", audio rx+tx");
		break;

	default:
		printf(", audio %d(not supported)", feature_audio);
		break;
	}

	puts(",\n       ");

	switch (feature_sysclock) {
	case SYSCLK_147456:
		printf("clock 147.456 MHz");
		break;

	default:
		printf("clock %d(not supported)", feature_sysclock);
		break;
	}

	switch (feature_ramconfig) {
	case RAM_DDR2_32:
		printf(", RAM 32 bit DDR2");
		break;

	case RAM_DDR3_32:
		printf(", RAM 32 bit DDR3");
		break;

	default:
		printf(", RAM %d(not supported)", feature_ramconfig);
		break;
	}

	printf(", %d carrier(s) %s", feature_carriers,
	       feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");

	printf(", %d video channel(s)\n", feature_video_channels);
}

int last_stage_init(void)
{
	int slaves;
	unsigned int k;
	unsigned int mux_ch;
	unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
	u16 fpga_features;
	int feature_carrier_speed;
	bool ch0_rgmii2_present = false;

	FPGA_GET_REG(0, fpga_features, &fpga_features);
	feature_carrier_speed = fpga_features & (1<<4);

	if (!legacy) {
		/* Turn on Parade DP501 */
		pca9698_direction_output(0x20, 9, 1);

		ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
	}

	/* wait for FPGA done; then reset FPGA */
	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
		unsigned int ctr = 0;

		if (i2c_probe(mclink_controllers[k]))
			continue;

		while (!(pca953x_get_val(mclink_controllers[k])
		       & MCFPGA_DONE)) {
			udelay(100000);
			if (ctr++ > 5) {
				printf("no done for mclink_controller %d\n", k);
				break;
			}
		}

		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
		udelay(10);
		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
				MCFPGA_RESET_N);
	}

	if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
		int retval;
		struct mii_dev *mdiodev = mdio_alloc();
		if (!mdiodev)
			return -ENOMEM;
		strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
		mdiodev->read = bb_miiphy_read;
		mdiodev->write = bb_miiphy_write;

		retval = mdio_register(mdiodev);
		if (retval < 0)
			return retval;
		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
			if ((mux_ch == 1) && !ch0_rgmii2_present)
				continue;

			setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
		}
	}

	/* give slave-PLLs and Parade DP501 some time to be up and running */
	udelay(500000);

	mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
	slaves = mclink_probe();
	mclink_fpgacount = 0;

	print_fpga_info(0, ch0_rgmii2_present);
	osd_probe(0);

	if (slaves <= 0)
		return 0;

	mclink_fpgacount = slaves;

	for (k = 1; k <= slaves; ++k) {
		FPGA_GET_REG(k, fpga_features, &fpga_features);
		feature_carrier_speed = fpga_features & (1<<4);

		print_fpga_info(k, false);
		osd_probe(k);
		if (feature_carrier_speed == CARRIER_SPEED_1G) {
			int retval;
			struct mii_dev *mdiodev = mdio_alloc();
			if (!mdiodev)
				return -ENOMEM;
			strncpy(mdiodev->name, bb_miiphy_buses[k].name,
				MDIO_NAME_LEN);
			mdiodev->read = bb_miiphy_read;
			mdiodev->write = bb_miiphy_write;

			retval = mdio_register(mdiodev);
			if (retval < 0)
				return retval;
			setup_88e1518(bb_miiphy_buses[k].name, 0);
		}
	}

	return 0;
}

/*
 * provide access to fpga gpios (for I2C bitbang)
 * (these may look all too simple but make iocon.h much more readable)
 */
void fpga_gpio_set(unsigned int bus, int pin)
{
	FPGA_SET_REG(bus, gpio.set, pin);
}

void fpga_gpio_clear(unsigned int bus, int pin)
{
	FPGA_SET_REG(bus, gpio.clear, pin);
}

int fpga_gpio_get(unsigned int bus, int pin)
{
	u16 val;

	FPGA_GET_REG(bus, gpio.read, &val);

	return val & pin;
}

void gd405ep_init(void)
{
	unsigned int k;

	if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
		for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
			gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
	} else {
		pca9698_direction_output(0x20, 4, 1);
	}
}

void gd405ep_set_fpga_reset(unsigned state)
{
	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;

	if (legacy) {
		if (state) {
			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
		} else {
			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
		}
	} else {
		pca9698_set_value(0x20, 4, state ? 0 : 1);
	}
}

void gd405ep_setup_hw(void)
{
	/*
	 * set "startup-finished"-gpios
	 */
	gpio_write_bit(21, 0);
	gpio_write_bit(22, 1);
}

int gd405ep_get_fpga_done(unsigned fpga)
{
	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;

	if (legacy)
		return in_le16((void *)LATCH2_BASE)
		       & CONFIG_SYS_FPGA_DONE(fpga);
	else
		return pca9698_get_value(0x20, 20);
}

/*
 * FPGA MII bitbang implementation
 */

struct fpga_mii {
	unsigned fpga;
	int mdio;
} fpga_mii[] = {
	{ 0, 1},
	{ 1, 1},
	{ 2, 1},
	{ 3, 1},
};

static int mii_dummy_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

static int mii_mdio_active(struct bb_miiphy_bus *bus)
{
	struct fpga_mii *fpga_mii = bus->priv;

	if (fpga_mii->mdio)
		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
	else
		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);

	return 0;
}

static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct fpga_mii *fpga_mii = bus->priv;

	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);

	return 0;
}

static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct fpga_mii *fpga_mii = bus->priv;

	if (v)
		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
	else
		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);

	fpga_mii->mdio = v;

	return 0;
}

static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	u16 gpio;
	struct fpga_mii *fpga_mii = bus->priv;

	FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);

	*v = ((gpio & GPIO_MDIO) != 0);

	return 0;
}

static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct fpga_mii *fpga_mii = bus->priv;

	if (v)
		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
	else
		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);

	return 0;
}

static int mii_delay(struct bb_miiphy_bus *bus)
{
	udelay(1);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name = "board0",
		.init = mii_dummy_init,
		.mdio_active = mii_mdio_active,
		.mdio_tristate = mii_mdio_tristate,
		.set_mdio = mii_set_mdio,
		.get_mdio = mii_get_mdio,
		.set_mdc = mii_set_mdc,
		.delay = mii_delay,
		.priv = &fpga_mii[0],
	},
	{
		.name = "board1",
		.init = mii_dummy_init,
		.mdio_active = mii_mdio_active,
		.mdio_tristate = mii_mdio_tristate,
		.set_mdio = mii_set_mdio,
		.get_mdio = mii_get_mdio,
		.set_mdc = mii_set_mdc,
		.delay = mii_delay,
		.priv = &fpga_mii[1],
	},
	{
		.name = "board2",
		.init = mii_dummy_init,
		.mdio_active = mii_mdio_active,
		.mdio_tristate = mii_mdio_tristate,
		.set_mdio = mii_set_mdio,
		.get_mdio = mii_get_mdio,
		.set_mdc = mii_set_mdc,
		.delay = mii_delay,
		.priv = &fpga_mii[2],
	},
	{
		.name = "board3",
		.init = mii_dummy_init,
		.mdio_active = mii_mdio_active,
		.mdio_tristate = mii_mdio_tristate,
		.set_mdio = mii_set_mdio,
		.get_mdio = mii_get_mdio,
		.set_mdc = mii_set_mdc,
		.delay = mii_delay,
		.priv = &fpga_mii[3],
	},
};

int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
			  sizeof(bb_miiphy_buses[0]);
Commit	Line	Data
a605ea7e DE	1	/*
	2	* (C) Copyright 2010
	3	* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
a605ea7e DE	6	*/
	7
	8	#include <common.h>
	9	#include <command.h>
e50e8968	10	#include <errno.h>
a605ea7e DE	11	#include <asm/processor.h>
	12	#include <asm/io.h>
	13	#include <asm/ppc4xx-gpio.h>
	14
6e9e6c36	15	#include "405ep.h"
2da0fc0d	16	#include <gdsys_fpga.h>
a605ea7e	17
2da0fc0d	18	#include "../common/osd.h"
e50e8968	19	#include "../common/mclink.h"
50dcf89d	20	#include "../common/phy.h"
e50e8968 DE	21
	22	#include <i2c.h>
	23	#include <pca953x.h>
	24	#include <pca9698.h>
	25
	26	#include <miiphy.h>
	27
	28	DECLARE_GLOBAL_DATA_PTR;
a605ea7e	29
6e9e6c36 DE	30	#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
	31	#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
	32	#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
	33
d78951db DE	34	#define MAX_MUX_CHANNELS 2
d78951db DE	35
a605ea7e DE	36	enum {
	37	UNITTYPE_MAIN_SERVER = 0,
	38	UNITTYPE_MAIN_USER = 1,
	39	UNITTYPE_VIDEO_SERVER = 2,
	40	UNITTYPE_VIDEO_USER = 3,
	41	};
	42
	43	enum {
	44	HWVER_100 = 0,
	45	HWVER_104 = 1,
	46	HWVER_110 = 2,
e50e8968 DE	47	HWVER_120 = 3,
	48	HWVER_200 = 4,
	49	HWVER_210 = 5,
a8089701 DE	50	HWVER_220 = 6,
a8089701 DE	51	HWVER_230 = 7,
e50e8968 DE	52	};
	53
	54	enum {
	55	FPGA_HWVER_200 = 0,
	56	FPGA_HWVER_210 = 1,
a605ea7e DE	57	};
	58
	59	enum {
	60	COMPRESSION_NONE = 0,
e50e8968 DE	61	COMPRESSION_TYPE1_DELTA = 1,
e50e8968 DE	62	COMPRESSION_TYPE1_TYPE2_DELTA = 3,
a605ea7e DE	63	};
	64
	65	enum {
	66	AUDIO_NONE = 0,
	67	AUDIO_TX = 1,
	68	AUDIO_RX = 2,
	69	AUDIO_RXTX = 3,
	70	};
	71
	72	enum {
	73	SYSCLK_147456 = 0,
	74	};
	75
	76	enum {
	77	RAM_DDR2_32 = 0,
e50e8968 DE	78	RAM_DDR3_32 = 1,
	79	};
	80
a8089701 DE	81	enum {
	82	CARRIER_SPEED_1G = 0,
	83	CARRIER_SPEED_2_5G = 1,
	84	};
	85
e50e8968 DE	86	enum {
	87	MCFPGA_DONE = 1 << 0,
	88	MCFPGA_INIT_N = 1 << 1,
	89	MCFPGA_PROGRAM_N = 1 << 2,
	90	MCFPGA_UPDATE_ENABLE_N = 1 << 3,
	91	MCFPGA_RESET_N = 1 << 4,
	92	};
	93
	94	enum {
	95	GPIO_MDC = 1 << 14,
	96	GPIO_MDIO = 1 << 15,
a605ea7e DE	97	};
a605ea7e DE	98
e50e8968	99	unsigned int mclink_fpgacount;
aba27acf DE	100	struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
aba27acf DE	101
e50e8968 DE	102	int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
	103	{
	104	int res;
	105
	106	switch (fpga) {
	107	case 0:
	108	out_le16(reg, data);
	109	break;
	110	default:
	111	res = mclink_send(fpga - 1, regoff, data);
	112	if (res < 0) {
	113	printf("mclink_send reg %02lx data %04x returned %d\n",
	114	regoff, data, res);
	115	return res;
	116	}
	117	break;
	118	}
	119
	120	return 0;
	121	}
	122
	123	int fpga_get_reg(u32 fpga, u16 reg, off_t regoff, u16 data)
	124	{
	125	int res;
	126
	127	switch (fpga) {
	128	case 0:
	129	*data = in_le16(reg);
	130	break;
	131	default:
	132	if (fpga > mclink_fpgacount)
	133	return -EINVAL;
	134	res = mclink_receive(fpga - 1, regoff, data);
	135	if (res < 0) {
	136	printf("mclink_receive reg %02lx returned %d\n",
	137	regoff, res);
	138	return res;
	139	}
	140	}
	141
	142	return 0;
	143	}
	144
a605ea7e DE	145	/*
	146	* Check Board Identity:
	147	*/
	148	int checkboard(void)
	149	{
b19bf834 DE	150	char *s = getenv("serial#");
	151
	152	puts("Board: ");
	153
	154	puts("IoCon");
	155
	156	if (s != NULL) {
	157	puts(", serial# ");
	158	puts(s);
	159	}
	160
	161	puts("\n");
	162
	163	return 0;
	164	}
	165
d78951db	166	static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
b19bf834	167	{
aba27acf DE	168	u16 versions;
	169	u16 fpga_version;
	170	u16 fpga_features;
a605ea7e DE	171	unsigned unit_type;
	172	unsigned hardware_version;
	173	unsigned feature_compression;
	174	unsigned feature_osd;
	175	unsigned feature_audio;
	176	unsigned feature_sysclock;
	177	unsigned feature_ramconfig;
a8089701	178	unsigned feature_carrier_speed;
a605ea7e DE	179	unsigned feature_carriers;
a605ea7e DE	180	unsigned feature_video_channels;
a8089701	181
8272baa9	182	int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM;
a605ea7e	183
8272baa9 DE	184	FPGA_GET_REG(fpga, versions, &versions);
	185	FPGA_GET_REG(fpga, fpga_version, &fpga_version);
	186	FPGA_GET_REG(fpga, fpga_features, &fpga_features);
aba27acf	187
a605ea7e	188	unit_type = (versions & 0xf000) >> 12;
a605ea7e DE	189	feature_compression = (fpga_features & 0xe000) >> 13;
	190	feature_osd = fpga_features & (1<<11);
	191	feature_audio = (fpga_features & 0x0600) >> 9;
	192	feature_sysclock = (fpga_features & 0x0180) >> 7;
	193	feature_ramconfig = (fpga_features & 0x0060) >> 5;
a8089701	194	feature_carrier_speed = fpga_features & (1<<4);
a605ea7e DE	195	feature_carriers = (fpga_features & 0x000c) >> 2;
	196	feature_video_channels = fpga_features & 0x0003;
	197
e50e8968 DE	198	if (legacy)
	199	printf("legacy ");
	200
a605ea7e DE	201	switch (unit_type) {
	202	case UNITTYPE_MAIN_USER:
	203	printf("Mainchannel");
	204	break;
	205
	206	case UNITTYPE_VIDEO_USER:
	207	printf("Videochannel");
	208	break;
	209
	210	default:
	211	printf("UnitType %d(not supported)", unit_type);
	212	break;
	213	}
	214
e50e8968 DE	215	if (unit_type == UNITTYPE_MAIN_USER) {
	216	if (legacy)
	217	hardware_version =
	218	(in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
	219	else
	220	hardware_version =
	221	(!!pca9698_get_value(0x20, 24) << 0)
	222	\| (!!pca9698_get_value(0x20, 25) << 1)
	223	\| (!!pca9698_get_value(0x20, 26) << 2)
	224	\| (!!pca9698_get_value(0x20, 27) << 3);
	225	switch (hardware_version) {
	226	case HWVER_100:
	227	printf(" HW-Ver 1.00,");
	228	break;
	229
	230	case HWVER_104:
	231	printf(" HW-Ver 1.04,");
	232	break;
	233
	234	case HWVER_110:
	235	printf(" HW-Ver 1.10,");
	236	break;
	237
	238	case HWVER_120:
	239	printf(" HW-Ver 1.20-1.21,");
	240	break;
	241
	242	case HWVER_200:
	243	printf(" HW-Ver 2.00,");
	244	break;
	245
	246	case HWVER_210:
	247	printf(" HW-Ver 2.10,");
	248	break;
	249
a8089701 DE	250	case HWVER_220:
	251	printf(" HW-Ver 2.20,");
	252	break;
	253
	254	case HWVER_230:
	255	printf(" HW-Ver 2.30,");
	256	break;
	257
e50e8968 DE	258	default:
	259	printf(" HW-Ver %d(not supported),",
	260	hardware_version);
	261	break;
	262	}
d78951db DE	263	if (rgmii2_present)
d78951db DE	264	printf(" RGMII2,");
e50e8968	265	}
a605ea7e	266
e50e8968 DE	267	if (unit_type == UNITTYPE_VIDEO_USER) {
	268	hardware_version = versions & 0x000f;
	269	switch (hardware_version) {
	270	case FPGA_HWVER_200:
	271	printf(" HW-Ver 2.00,");
	272	break;
	273
	274	case FPGA_HWVER_210:
	275	printf(" HW-Ver 2.10,");
	276	break;
	277
	278	default:
	279	printf(" HW-Ver %d(not supported),",
	280	hardware_version);
	281	break;
	282	}
a605ea7e DE	283	}
a605ea7e DE	284
e50e8968 DE	285	printf(" FPGA V %d.%02d\n features:",
e50e8968 DE	286	fpga_version / 100, fpga_version % 100);
a605ea7e DE	287
	288
	289	switch (feature_compression) {
	290	case COMPRESSION_NONE:
	291	printf(" no compression");
	292	break;
	293
	294	case COMPRESSION_TYPE1_DELTA:
	295	printf(" type1-deltacompression");
	296	break;
	297
e50e8968 DE	298	case COMPRESSION_TYPE1_TYPE2_DELTA:
	299	printf(" type1-deltacompression, type2-inlinecompression");
	300	break;
	301
a605ea7e DE	302	default:
	303	printf(" compression %d(not supported)", feature_compression);
	304	break;
	305	}
	306
	307	printf(", %sosd", feature_osd ? "" : "no ");
	308
	309	switch (feature_audio) {
	310	case AUDIO_NONE:
	311	printf(", no audio");
	312	break;
	313
	314	case AUDIO_TX:
	315	printf(", audio tx");
	316	break;
	317
	318	case AUDIO_RX:
	319	printf(", audio rx");
	320	break;
	321
	322	case AUDIO_RXTX:
	323	printf(", audio rx+tx");
	324	break;
	325
	326	default:
	327	printf(", audio %d(not supported)", feature_audio);
	328	break;
	329	}
	330
	331	puts(",\n ");
	332
	333	switch (feature_sysclock) {
	334	case SYSCLK_147456:
	335	printf("clock 147.456 MHz");
	336	break;
	337
	338	default:
	339	printf("clock %d(not supported)", feature_sysclock);
	340	break;
	341	}
	342
	343	switch (feature_ramconfig) {
	344	case RAM_DDR2_32:
	345	printf(", RAM 32 bit DDR2");
	346	break;
	347
e50e8968 DE	348	case RAM_DDR3_32:
	349	printf(", RAM 32 bit DDR3");
	350	break;
	351
a605ea7e DE	352	default:
	353	printf(", RAM %d(not supported)", feature_ramconfig);
	354	break;
	355	}
	356
a8089701 DE	357	printf(", %d carrier(s) %s", feature_carriers,
a8089701 DE	358	feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
a605ea7e DE	359
a605ea7e DE	360	printf(", %d video channel(s)\n", feature_video_channels);
a605ea7e DE	361	}
	362
	363	int last_stage_init(void)
	364	{
e50e8968 DE	365	int slaves;
e50e8968 DE	366	unsigned int k;
d78951db	367	unsigned int mux_ch;
e50e8968 DE	368	unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
e50e8968 DE	369	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
a8089701	370	u16 fpga_features;
a8cb9d0b	371	int feature_carrier_speed;
d78951db	372	bool ch0_rgmii2_present = false;
a8089701 DE	373
a8089701 DE	374	FPGA_GET_REG(0, fpga_features, &fpga_features);
a8cb9d0b	375	feature_carrier_speed = fpga_features & (1<<4);
e50e8968	376
3a990bfa DE	377	if (!legacy) {
	378	/* Turn on Parade DP501 */
	379	pca9698_direction_output(0x20, 9, 1);
edfe9fea	380
d78951db	381	ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
3a990bfa	382	}
d78951db	383
57b84a0d	384	/* wait for FPGA done; then reset FPGA */
e50e8968 DE	385	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
	386	unsigned int ctr = 0;
	387
	388	if (i2c_probe(mclink_controllers[k]))
	389	continue;
	390
	391	while (!(pca953x_get_val(mclink_controllers[k])
	392	& MCFPGA_DONE)) {
	393	udelay(100000);
	394	if (ctr++ > 5) {
	395	printf("no done for mclink_controller %d\n", k);
	396	break;
	397	}
	398	}
57b84a0d RP	399
	400	pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
	401	pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
	402	udelay(10);
	403	pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
	404	MCFPGA_RESET_N);
e50e8968 DE	405	}
e50e8968 DE	406
a8089701	407	if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
5a49f174 JH	408	int retval;
	409	struct mii_dev *mdiodev = mdio_alloc();
	410	if (!mdiodev)
	411	return -ENOMEM;
	412	strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
	413	mdiodev->read = bb_miiphy_read;
	414	mdiodev->write = bb_miiphy_write;
	415
	416	retval = mdio_register(mdiodev);
	417	if (retval < 0)
	418	return retval;
d78951db DE	419	for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
	420	if ((mux_ch == 1) && !ch0_rgmii2_present)
	421	continue;
	422
f24c8e8d	423	setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
e50e8968 DE	424	}
e50e8968 DE	425	}
b19bf834	426
5d1a4bf3	427	/* give slave-PLLs and Parade DP501 some time to be up and running */
e50e8968 DE	428	udelay(500000);
	429
	430	mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
	431	slaves = mclink_probe();
	432	mclink_fpgacount = 0;
	433
5d1a4bf3 DE	434	print_fpga_info(0, ch0_rgmii2_present);
	435	osd_probe(0);
	436
e50e8968 DE	437	if (slaves <= 0)
	438	return 0;
	439
	440	mclink_fpgacount = slaves;
	441
	442	for (k = 1; k <= slaves; ++k) {
a8089701 DE	443	FPGA_GET_REG(k, fpga_features, &fpga_features);
	444	feature_carrier_speed = fpga_features & (1<<4);
	445
d78951db	446	print_fpga_info(k, false);
e50e8968	447	osd_probe(k);
a8089701	448	if (feature_carrier_speed == CARRIER_SPEED_1G) {
5a49f174 JH	449	int retval;
	450	struct mii_dev *mdiodev = mdio_alloc();
	451	if (!mdiodev)
	452	return -ENOMEM;
	453	strncpy(mdiodev->name, bb_miiphy_buses[k].name,
	454	MDIO_NAME_LEN);
	455	mdiodev->read = bb_miiphy_read;
	456	mdiodev->write = bb_miiphy_write;
	457
	458	retval = mdio_register(mdiodev);
	459	if (retval < 0)
	460	return retval;
f24c8e8d	461	setup_88e1518(bb_miiphy_buses[k].name, 0);
e50e8968 DE	462	}
	463	}
	464
	465	return 0;
a605ea7e DE	466	}
	467
	468	/*
	469	* provide access to fpga gpios (for I2C bitbang)
aba27acf	470	* (these may look all too simple but make iocon.h much more readable)
a605ea7e	471	*/
e50e8968	472	void fpga_gpio_set(unsigned int bus, int pin)
a605ea7e	473	{
e50e8968	474	FPGA_SET_REG(bus, gpio.set, pin);
a605ea7e DE	475	}
a605ea7e DE	476
e50e8968	477	void fpga_gpio_clear(unsigned int bus, int pin)
a605ea7e	478	{
e50e8968	479	FPGA_SET_REG(bus, gpio.clear, pin);
a605ea7e DE	480	}
a605ea7e DE	481
e50e8968	482	int fpga_gpio_get(unsigned int bus, int pin)
a605ea7e	483	{
aba27acf DE	484	u16 val;
aba27acf DE	485
e50e8968	486	FPGA_GET_REG(bus, gpio.read, &val);
aba27acf DE	487
aba27acf DE	488	return val & pin;
a605ea7e	489	}
6e9e6c36 DE	490
	491	void gd405ep_init(void)
	492	{
e50e8968 DE	493	unsigned int k;
	494
	495	if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
	496	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
	497	gd->arch.fpga_state[k] \|= FPGA_STATE_PLATFORM;
	498	} else {
	499	pca9698_direction_output(0x20, 4, 1);
	500	}
6e9e6c36 DE	501	}
	502
	503	void gd405ep_set_fpga_reset(unsigned state)
	504	{
e50e8968 DE	505	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
	506
	507	if (legacy) {
	508	if (state) {
	509	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
	510	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
	511	} else {
	512	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
	513	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
	514	}
6e9e6c36	515	} else {
e50e8968	516	pca9698_set_value(0x20, 4, state ? 0 : 1);
6e9e6c36 DE	517	}
	518	}
	519
	520	void gd405ep_setup_hw(void)
	521	{
	522	/*
	523	* set "startup-finished"-gpios
	524	*/
	525	gpio_write_bit(21, 0);
	526	gpio_write_bit(22, 1);
	527	}
	528
	529	int gd405ep_get_fpga_done(unsigned fpga)
	530	{
e50e8968 DE	531	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
	532
	533	if (legacy)
	534	return in_le16((void *)LATCH2_BASE)
	535	& CONFIG_SYS_FPGA_DONE(fpga);
	536	else
	537	return pca9698_get_value(0x20, 20);
	538	}
	539
	540	/*
	541	* FPGA MII bitbang implementation
	542	*/
	543
	544	struct fpga_mii {
	545	unsigned fpga;
	546	int mdio;
	547	} fpga_mii[] = {
	548	{ 0, 1},
	549	{ 1, 1},
	550	{ 2, 1},
	551	{ 3, 1},
	552	};
	553
	554	static int mii_dummy_init(struct bb_miiphy_bus *bus)
	555	{
	556	return 0;
	557	}
	558
	559	static int mii_mdio_active(struct bb_miiphy_bus *bus)
	560	{
	561	struct fpga_mii *fpga_mii = bus->priv;
	562
	563	if (fpga_mii->mdio)
	564	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
	565	else
	566	FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
	567
	568	return 0;
	569	}
	570
	571	static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
	572	{
	573	struct fpga_mii *fpga_mii = bus->priv;
	574
	575	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
	576
	577	return 0;
	578	}
	579
	580	static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
	581	{
	582	struct fpga_mii *fpga_mii = bus->priv;
	583
	584	if (v)
	585	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
	586	else
	587	FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
	588
	589	fpga_mii->mdio = v;
	590
	591	return 0;
	592	}
	593
	594	static int mii_get_mdio(struct bb_miiphy_bus bus, int v)
595	{
596	u16 gpio;
597	struct fpga_mii *fpga_mii = bus->priv;
598
599	FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
600
601	*v = ((gpio & GPIO_MDIO) != 0);
602
603	return 0;
604	}
605
606	static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
607	{
608	struct fpga_mii *fpga_mii = bus->priv;
609
610	if (v)
611	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
612	else
613	FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
614
615	return 0;
616	}
617
618	static int mii_delay(struct bb_miiphy_bus *bus)
619	{
620	udelay(1);
621
622	return 0;
623	}
624
625	struct bb_miiphy_bus bb_miiphy_buses[] = {
626	{
d78951db	627	.name = "board0",
e50e8968 DE	628	.init = mii_dummy_init,
	629	.mdio_active = mii_mdio_active,
	630	.mdio_tristate = mii_mdio_tristate,
	631	.set_mdio = mii_set_mdio,
	632	.get_mdio = mii_get_mdio,
	633	.set_mdc = mii_set_mdc,
	634	.delay = mii_delay,
	635	.priv = &fpga_mii[0],
	636	},
	637	{
d78951db	638	.name = "board1",
e50e8968 DE	639	.init = mii_dummy_init,
	640	.mdio_active = mii_mdio_active,
	641	.mdio_tristate = mii_mdio_tristate,
	642	.set_mdio = mii_set_mdio,
	643	.get_mdio = mii_get_mdio,
	644	.set_mdc = mii_set_mdc,
	645	.delay = mii_delay,
	646	.priv = &fpga_mii[1],
	647	},
	648	{
d78951db	649	.name = "board2",
e50e8968 DE	650	.init = mii_dummy_init,
	651	.mdio_active = mii_mdio_active,
	652	.mdio_tristate = mii_mdio_tristate,
	653	.set_mdio = mii_set_mdio,
	654	.get_mdio = mii_get_mdio,
	655	.set_mdc = mii_set_mdc,
	656	.delay = mii_delay,
	657	.priv = &fpga_mii[2],
	658	},
	659	{
d78951db	660	.name = "board3",
e50e8968 DE	661	.init = mii_dummy_init,
	662	.mdio_active = mii_mdio_active,
	663	.mdio_tristate = mii_mdio_tristate,
	664	.set_mdio = mii_set_mdio,
	665	.get_mdio = mii_get_mdio,
	666	.set_mdc = mii_set_mdc,
	667	.delay = mii_delay,
	668	.priv = &fpga_mii[3],
	669	},
	670	};
	671
	672	int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
	673	sizeof(bb_miiphy_buses[0]);