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f9162b15 AB |
1 | /* |
2 | * Copyright 2015 Timesys Corporation | |
3 | * Copyright 2015 General Electric Company | |
4 | * Copyright 2012 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <asm/arch/clock.h> | |
10 | #include <asm/arch/imx-regs.h> | |
11 | #include <asm/arch/iomux.h> | |
12 | #include <asm/arch/mx6-pins.h> | |
1221ce45 | 13 | #include <linux/errno.h> |
f9162b15 | 14 | #include <asm/gpio.h> |
552a848e SB |
15 | #include <asm/mach-imx/mxc_i2c.h> |
16 | #include <asm/mach-imx/iomux-v3.h> | |
17 | #include <asm/mach-imx/boot_mode.h> | |
18 | #include <asm/mach-imx/video.h> | |
f9162b15 AB |
19 | #include <mmc.h> |
20 | #include <fsl_esdhc.h> | |
21 | #include <miiphy.h> | |
22 | #include <netdev.h> | |
23 | #include <asm/arch/mxc_hdmi.h> | |
24 | #include <asm/arch/crm_regs.h> | |
25 | #include <asm/io.h> | |
26 | #include <asm/arch/sys_proto.h> | |
27 | #include <i2c.h> | |
7594c51a | 28 | #include <input.h> |
54971ac6 | 29 | #include <pwm.h> |
be2808c3 | 30 | #include <stdlib.h> |
b418dfe1 | 31 | #include "../common/vpd_reader.h" |
f9162b15 AB |
32 | DECLARE_GLOBAL_DATA_PTR; |
33 | ||
be2808c3 IR |
34 | #ifndef CONFIG_SYS_I2C_EEPROM_ADDR |
35 | # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
36 | # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
37 | #endif | |
38 | ||
39 | #ifndef CONFIG_SYS_I2C_EEPROM_BUS | |
40 | #define CONFIG_SYS_I2C_EEPROM_BUS 2 | |
41 | #endif | |
42 | ||
7d0b8cfe JW |
43 | #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
44 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ | |
45 | PAD_CTL_HYS) | |
46 | ||
f9162b15 AB |
47 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
48 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ | |
49 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
50 | ||
51 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ | |
52 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ | |
53 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
54 | ||
55 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ | |
56 | PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) | |
57 | ||
58 | #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ | |
59 | PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) | |
60 | ||
61 | #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
62 | PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) | |
63 | ||
64 | #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ | |
65 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | |
66 | ||
67 | #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
68 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | |
69 | PAD_CTL_ODE | PAD_CTL_SRE_FAST) | |
70 | ||
71 | #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) | |
72 | ||
73 | int dram_init(void) | |
74 | { | |
c6a51bab | 75 | gd->ram_size = imx_ddr_size(); |
f9162b15 AB |
76 | |
77 | return 0; | |
78 | } | |
79 | ||
80 | static iomux_v3_cfg_t const uart3_pads[] = { | |
81 | MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
82 | MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
83 | MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
84 | MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
85 | }; | |
86 | ||
87 | static iomux_v3_cfg_t const uart4_pads[] = { | |
88 | MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
89 | MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
90 | }; | |
91 | ||
92 | static iomux_v3_cfg_t const enet_pads[] = { | |
93 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
94 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
95 | MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
96 | MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
97 | MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
98 | MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
99 | MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
100 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
101 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), | |
102 | MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), | |
103 | MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), | |
104 | MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), | |
105 | MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), | |
106 | MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), | |
107 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), | |
108 | /* AR8033 PHY Reset */ | |
109 | MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
110 | }; | |
111 | ||
112 | static void setup_iomux_enet(void) | |
113 | { | |
114 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); | |
115 | ||
116 | /* Reset AR8033 PHY */ | |
117 | gpio_direction_output(IMX_GPIO_NR(1, 28), 0); | |
d42db168 | 118 | mdelay(10); |
f9162b15 | 119 | gpio_set_value(IMX_GPIO_NR(1, 28), 1); |
d42db168 | 120 | mdelay(1); |
f9162b15 AB |
121 | } |
122 | ||
123 | static iomux_v3_cfg_t const usdhc2_pads[] = { | |
124 | MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
125 | MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
126 | MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
127 | MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
128 | MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
129 | MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
130 | MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
131 | }; | |
132 | ||
133 | static iomux_v3_cfg_t const usdhc3_pads[] = { | |
134 | MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
135 | MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
136 | MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
137 | MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
138 | MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
139 | MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
140 | MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
141 | MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
142 | MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
143 | MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
144 | MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
145 | }; | |
146 | ||
147 | static iomux_v3_cfg_t const usdhc4_pads[] = { | |
148 | MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
149 | MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
150 | MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
151 | MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
152 | MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
153 | MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
154 | MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
155 | MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
156 | MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
157 | MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
158 | MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
159 | MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
160 | }; | |
161 | ||
162 | static iomux_v3_cfg_t const ecspi1_pads[] = { | |
163 | MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
164 | MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
165 | MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
166 | MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
167 | }; | |
168 | ||
169 | static struct i2c_pads_info i2c_pad_info1 = { | |
170 | .scl = { | |
171 | .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, | |
172 | .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, | |
173 | .gp = IMX_GPIO_NR(5, 27) | |
174 | }, | |
175 | .sda = { | |
176 | .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, | |
177 | .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, | |
178 | .gp = IMX_GPIO_NR(5, 26) | |
179 | } | |
180 | }; | |
181 | ||
182 | static struct i2c_pads_info i2c_pad_info2 = { | |
183 | .scl = { | |
184 | .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, | |
185 | .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, | |
186 | .gp = IMX_GPIO_NR(4, 12) | |
187 | }, | |
188 | .sda = { | |
189 | .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, | |
190 | .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, | |
191 | .gp = IMX_GPIO_NR(4, 13) | |
192 | } | |
193 | }; | |
194 | ||
195 | static struct i2c_pads_info i2c_pad_info3 = { | |
196 | .scl = { | |
197 | .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, | |
198 | .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, | |
199 | .gp = IMX_GPIO_NR(1, 3) | |
200 | }, | |
201 | .sda = { | |
202 | .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, | |
203 | .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, | |
204 | .gp = IMX_GPIO_NR(1, 6) | |
205 | } | |
206 | }; | |
207 | ||
208 | #ifdef CONFIG_MXC_SPI | |
209 | int board_spi_cs_gpio(unsigned bus, unsigned cs) | |
210 | { | |
211 | return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; | |
212 | } | |
213 | ||
214 | static void setup_spi(void) | |
215 | { | |
216 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); | |
217 | } | |
218 | #endif | |
219 | ||
220 | static iomux_v3_cfg_t const pcie_pads[] = { | |
221 | MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
222 | MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
223 | }; | |
224 | ||
225 | static void setup_pcie(void) | |
226 | { | |
227 | imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); | |
228 | } | |
229 | ||
230 | static void setup_iomux_uart(void) | |
231 | { | |
232 | imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); | |
233 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); | |
234 | } | |
235 | ||
236 | #ifdef CONFIG_FSL_ESDHC | |
237 | struct fsl_esdhc_cfg usdhc_cfg[3] = { | |
238 | {USDHC2_BASE_ADDR}, | |
239 | {USDHC3_BASE_ADDR}, | |
240 | {USDHC4_BASE_ADDR}, | |
241 | }; | |
242 | ||
243 | #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) | |
244 | #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11) | |
245 | ||
246 | int board_mmc_getcd(struct mmc *mmc) | |
247 | { | |
248 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
249 | int ret = 0; | |
250 | ||
251 | switch (cfg->esdhc_base) { | |
252 | case USDHC2_BASE_ADDR: | |
253 | ret = !gpio_get_value(USDHC2_CD_GPIO); | |
254 | break; | |
255 | case USDHC3_BASE_ADDR: | |
256 | ret = 1; /* eMMC is always present */ | |
257 | break; | |
258 | case USDHC4_BASE_ADDR: | |
259 | ret = !gpio_get_value(USDHC4_CD_GPIO); | |
260 | break; | |
261 | } | |
262 | ||
263 | return ret; | |
264 | } | |
265 | ||
266 | int board_mmc_init(bd_t *bis) | |
267 | { | |
268 | int ret; | |
269 | int i; | |
270 | ||
271 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | |
272 | switch (i) { | |
273 | case 0: | |
274 | imx_iomux_v3_setup_multiple_pads( | |
275 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); | |
276 | gpio_direction_input(USDHC2_CD_GPIO); | |
277 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | |
278 | break; | |
279 | case 1: | |
280 | imx_iomux_v3_setup_multiple_pads( | |
281 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); | |
282 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
283 | break; | |
284 | case 2: | |
285 | imx_iomux_v3_setup_multiple_pads( | |
286 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); | |
287 | gpio_direction_input(USDHC4_CD_GPIO); | |
288 | usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); | |
289 | break; | |
290 | default: | |
291 | printf("Warning: you configured more USDHC controllers\n" | |
292 | "(%d) then supported by the board (%d)\n", | |
293 | i + 1, CONFIG_SYS_FSL_USDHC_NUM); | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | |
298 | if (ret) | |
299 | return ret; | |
300 | } | |
301 | ||
302 | return 0; | |
303 | } | |
304 | #endif | |
305 | ||
306 | static int mx6_rgmii_rework(struct phy_device *phydev) | |
307 | { | |
308 | /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ | |
309 | /* set device address 0x7 */ | |
310 | phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); | |
311 | /* offset 0x8016: CLK_25M Clock Select */ | |
312 | phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); | |
313 | /* enable register write, no post increment, address 0x7 */ | |
314 | phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); | |
315 | /* set to 125 MHz from local PLL source */ | |
316 | phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18); | |
317 | ||
318 | /* rgmii tx clock delay enable */ | |
319 | /* set debug port address: SerDes Test and System Mode Control */ | |
320 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); | |
321 | /* enable rgmii tx clock delay */ | |
ec7aa8fd YCL |
322 | /* set the reserved bits to avoid board specific voltage peak issue*/ |
323 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); | |
f9162b15 AB |
324 | |
325 | return 0; | |
326 | } | |
327 | ||
328 | int board_phy_config(struct phy_device *phydev) | |
329 | { | |
330 | mx6_rgmii_rework(phydev); | |
331 | ||
332 | if (phydev->drv->config) | |
333 | phydev->drv->config(phydev); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | #if defined(CONFIG_VIDEO_IPUV3) | |
339 | static iomux_v3_cfg_t const backlight_pads[] = { | |
340 | /* Power for LVDS Display */ | |
341 | MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
342 | #define LVDS_POWER_GP IMX_GPIO_NR(3, 22) | |
343 | /* Backlight enable for LVDS display */ | |
344 | MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
345 | #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0) | |
54971ac6 AB |
346 | /* backlight PWM brightness control */ |
347 | MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), | |
f9162b15 AB |
348 | }; |
349 | ||
350 | static void do_enable_hdmi(struct display_info_t const *dev) | |
351 | { | |
352 | imx_enable_hdmi_phy(); | |
353 | } | |
354 | ||
355 | int board_cfb_skip(void) | |
356 | { | |
357 | gpio_direction_output(LVDS_POWER_GP, 1); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static int detect_baseboard(struct display_info_t const *dev) | |
363 | { | |
364 | if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) || | |
365 | IS_ENABLED(CONFIG_TARGET_GE_B650V3)) | |
366 | return 1; | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
371 | struct display_info_t const displays[] = {{ | |
372 | .bus = -1, | |
373 | .addr = -1, | |
374 | .pixfmt = IPU_PIX_FMT_RGB24, | |
375 | .detect = detect_baseboard, | |
376 | .enable = NULL, | |
377 | .mode = { | |
378 | .name = "G121X1-L03", | |
379 | .refresh = 60, | |
380 | .xres = 1024, | |
381 | .yres = 768, | |
382 | .pixclock = 15385, | |
383 | .left_margin = 20, | |
384 | .right_margin = 300, | |
385 | .upper_margin = 30, | |
386 | .lower_margin = 8, | |
387 | .hsync_len = 1, | |
388 | .vsync_len = 1, | |
389 | .sync = FB_SYNC_EXT, | |
390 | .vmode = FB_VMODE_NONINTERLACED | |
391 | } }, { | |
392 | .bus = -1, | |
393 | .addr = 3, | |
394 | .pixfmt = IPU_PIX_FMT_RGB24, | |
395 | .detect = detect_hdmi, | |
396 | .enable = do_enable_hdmi, | |
397 | .mode = { | |
398 | .name = "HDMI", | |
399 | .refresh = 60, | |
400 | .xres = 1024, | |
401 | .yres = 768, | |
402 | .pixclock = 15385, | |
403 | .left_margin = 220, | |
404 | .right_margin = 40, | |
405 | .upper_margin = 21, | |
406 | .lower_margin = 7, | |
407 | .hsync_len = 60, | |
408 | .vsync_len = 10, | |
409 | .sync = FB_SYNC_EXT, | |
410 | .vmode = FB_VMODE_NONINTERLACED | |
411 | } } }; | |
412 | size_t display_count = ARRAY_SIZE(displays); | |
413 | ||
494d43ec AB |
414 | static void enable_videopll(void) |
415 | { | |
416 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
417 | s32 timeout = 100000; | |
418 | ||
419 | setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); | |
420 | ||
421 | /* set video pll to 910MHz (24MHz * (37+11/12)) | |
422 | * video pll post div to 910/4 = 227.5MHz | |
423 | */ | |
424 | clrsetbits_le32(&ccm->analog_pll_video, | |
425 | BM_ANADIG_PLL_VIDEO_DIV_SELECT | | |
426 | BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, | |
427 | BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | | |
428 | BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0)); | |
429 | ||
430 | writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); | |
431 | writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); | |
432 | ||
433 | clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); | |
434 | ||
435 | while (timeout--) | |
436 | if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) | |
437 | break; | |
438 | ||
439 | if (timeout < 0) | |
440 | printf("Warning: video pll lock timeout!\n"); | |
441 | ||
442 | clrsetbits_le32(&ccm->analog_pll_video, | |
443 | BM_ANADIG_PLL_VIDEO_BYPASS, | |
444 | BM_ANADIG_PLL_VIDEO_ENABLE); | |
445 | } | |
446 | ||
de708da0 | 447 | static void setup_display_b850v3(void) |
f9162b15 AB |
448 | { |
449 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
450 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
f9162b15 | 451 | |
494d43ec AB |
452 | enable_videopll(); |
453 | ||
de708da0 AB |
454 | /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */ |
455 | clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); | |
456 | ||
f9162b15 AB |
457 | imx_setup_hdmi(); |
458 | ||
de708da0 AB |
459 | /* Set LDB_DI0 as clock source for IPU_DI0 */ |
460 | clrsetbits_le32(&mxc_ccm->chsccdr, | |
461 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, | |
462 | (CHSCCDR_CLK_SEL_LDB_DI0 << | |
463 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); | |
464 | ||
465 | /* Turn on IPU LDB DI0 clocks */ | |
466 | setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); | |
467 | ||
468 | enable_ipu_clock(); | |
469 | ||
470 | writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | | |
471 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | | |
472 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | | |
473 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | | |
474 | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | | |
475 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | | |
476 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | | |
477 | IOMUXC_GPR2_SPLIT_MODE_EN_MASK | | |
478 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | | |
479 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0, | |
480 | &iomux->gpr[2]); | |
481 | ||
482 | clrbits_le32(&iomux->gpr[3], | |
483 | IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | | |
484 | IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | | |
485 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK); | |
486 | } | |
487 | ||
488 | static void setup_display_bx50v3(void) | |
489 | { | |
490 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
491 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
492 | ||
8d293f49 AB |
493 | /* When a reset/reboot is performed the display power needs to be turned |
494 | * off for atleast 500ms. The boot time is ~300ms, we need to wait for | |
495 | * an additional 200ms here. Unfortunately we use external PMIC for | |
496 | * doing the reset, so can not differentiate between POR vs soft reset | |
497 | */ | |
498 | mdelay(200); | |
499 | ||
de708da0 AB |
500 | /* IPU1 DI0 clock is 480/7 = 68.5 MHz */ |
501 | setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); | |
502 | ||
503 | /* Set LDB_DI0 as clock source for IPU_DI0 */ | |
504 | clrsetbits_le32(&mxc_ccm->chsccdr, | |
505 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, | |
506 | (CHSCCDR_CLK_SEL_LDB_DI0 << | |
507 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); | |
508 | ||
509 | /* Turn on IPU LDB DI0 clocks */ | |
510 | setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); | |
511 | ||
512 | enable_ipu_clock(); | |
513 | ||
514 | writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | | |
515 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | | |
516 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | | |
517 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | | |
518 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, | |
519 | &iomux->gpr[2]); | |
520 | ||
521 | clrsetbits_le32(&iomux->gpr[3], | |
522 | IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, | |
523 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << | |
524 | IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)); | |
f9162b15 AB |
525 | |
526 | /* backlights off until needed */ | |
527 | imx_iomux_v3_setup_multiple_pads(backlight_pads, | |
528 | ARRAY_SIZE(backlight_pads)); | |
529 | gpio_direction_input(LVDS_POWER_GP); | |
530 | gpio_direction_input(LVDS_BACKLIGHT_GP); | |
531 | } | |
532 | #endif /* CONFIG_VIDEO_IPUV3 */ | |
533 | ||
534 | /* | |
535 | * Do not overwrite the console | |
536 | * Use always serial for U-Boot console | |
537 | */ | |
538 | int overwrite_console(void) | |
539 | { | |
540 | return 1; | |
541 | } | |
542 | ||
be2808c3 IR |
543 | #define VPD_TYPE_INVALID 0x00 |
544 | #define VPD_BLOCK_NETWORK 0x20 | |
545 | #define VPD_BLOCK_HWID 0x44 | |
546 | #define VPD_PRODUCT_B850 1 | |
547 | #define VPD_PRODUCT_B650 2 | |
548 | #define VPD_PRODUCT_B450 3 | |
549 | ||
550 | struct vpd_cache { | |
551 | uint8_t product_id; | |
552 | uint8_t macbits; | |
553 | unsigned char mac1[6]; | |
554 | }; | |
555 | ||
556 | /* | |
557 | * Extracts MAC and product information from the VPD. | |
558 | */ | |
559 | static int vpd_callback( | |
560 | void *userdata, | |
561 | uint8_t id, | |
562 | uint8_t version, | |
563 | uint8_t type, | |
564 | size_t size, | |
565 | uint8_t const *data) | |
566 | { | |
567 | struct vpd_cache *vpd = (struct vpd_cache *)userdata; | |
568 | ||
569 | if ( id == VPD_BLOCK_HWID | |
570 | && version == 1 | |
571 | && type != VPD_TYPE_INVALID | |
572 | && size >= 1) { | |
573 | vpd->product_id = data[0]; | |
574 | ||
575 | } else if ( id == VPD_BLOCK_NETWORK | |
576 | && version == 1 | |
577 | && type != VPD_TYPE_INVALID | |
578 | && size >= 6) { | |
579 | vpd->macbits |= 1; | |
580 | memcpy(vpd->mac1, data, 6); | |
581 | } | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | static void set_eth0_mac_address(unsigned char * mac) | |
587 | { | |
588 | uint32_t *ENET_TCR = (uint32_t*)0x21880c4; | |
589 | uint32_t *ENET_PALR = (uint32_t*)0x21880e4; | |
590 | uint32_t *ENET_PAUR = (uint32_t*)0x21880e8; | |
591 | ||
592 | *ENET_TCR |= 0x100; /* ADDINS */ | |
593 | *ENET_PALR |= (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; | |
594 | *ENET_PAUR |= (mac[4] << 24) | (mac[5] << 16); | |
595 | } | |
596 | ||
597 | static void process_vpd(struct vpd_cache *vpd) | |
598 | { | |
599 | if ( vpd->product_id == VPD_PRODUCT_B850 | |
600 | || vpd->product_id == VPD_PRODUCT_B650 | |
601 | || vpd->product_id == VPD_PRODUCT_B450) { | |
602 | if (vpd->macbits & 1) { | |
603 | set_eth0_mac_address(vpd->mac1); | |
604 | } | |
605 | } | |
606 | } | |
607 | ||
608 | static int read_vpd(uint eeprom_bus) | |
609 | { | |
610 | struct vpd_cache vpd; | |
611 | int res; | |
612 | int size = 1024; | |
613 | uint8_t *data; | |
614 | unsigned int current_i2c_bus = i2c_get_bus_num(); | |
615 | ||
616 | res = i2c_set_bus_num(eeprom_bus); | |
617 | if (res < 0) | |
618 | return res; | |
619 | ||
620 | data = (uint8_t *)malloc(size); | |
621 | if (!data) | |
622 | return -ENOMEM; | |
623 | ||
624 | res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, | |
625 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size); | |
626 | ||
627 | if (res == 0) { | |
628 | memset(&vpd, 0, sizeof(vpd)); | |
629 | vpd_reader(size, data, &vpd, vpd_callback); | |
630 | process_vpd(&vpd); | |
631 | } | |
632 | ||
633 | free(data); | |
634 | ||
635 | i2c_set_bus_num(current_i2c_bus); | |
636 | return res; | |
637 | } | |
638 | ||
f9162b15 AB |
639 | int board_eth_init(bd_t *bis) |
640 | { | |
641 | setup_iomux_enet(); | |
642 | setup_pcie(); | |
643 | ||
644 | return cpu_eth_init(bis); | |
645 | } | |
646 | ||
647 | static iomux_v3_cfg_t const misc_pads[] = { | |
648 | MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
7d0b8cfe JW |
649 | MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL), |
650 | MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL), | |
651 | MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL), | |
652 | MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL), | |
653 | MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL), | |
654 | MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL), | |
f9162b15 AB |
655 | }; |
656 | #define SUS_S3_OUT IMX_GPIO_NR(4, 11) | |
657 | #define WIFI_EN IMX_GPIO_NR(6, 14) | |
658 | ||
659 | int board_early_init_f(void) | |
660 | { | |
661 | imx_iomux_v3_setup_multiple_pads(misc_pads, | |
662 | ARRAY_SIZE(misc_pads)); | |
663 | ||
664 | setup_iomux_uart(); | |
665 | ||
494d43ec AB |
666 | #if defined(CONFIG_VIDEO_IPUV3) |
667 | if (IS_ENABLED(CONFIG_TARGET_GE_B850V3)) | |
668 | /* Set LDB clock to Video PLL */ | |
669 | select_ldb_di_clock_source(MXC_PLL5_CLK); | |
670 | else | |
671 | /* Set LDB clock to USB PLL */ | |
672 | select_ldb_di_clock_source(MXC_PLL3_SW_CLK); | |
673 | #endif | |
f9162b15 AB |
674 | return 0; |
675 | } | |
676 | ||
677 | int board_init(void) | |
678 | { | |
679 | gpio_direction_output(SUS_S3_OUT, 1); | |
680 | gpio_direction_output(WIFI_EN, 1); | |
681 | #if defined(CONFIG_VIDEO_IPUV3) | |
de708da0 AB |
682 | if (IS_ENABLED(CONFIG_TARGET_GE_B850V3)) |
683 | setup_display_b850v3(); | |
684 | else | |
685 | setup_display_bx50v3(); | |
f9162b15 AB |
686 | #endif |
687 | /* address of boot parameters */ | |
688 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
689 | ||
690 | #ifdef CONFIG_MXC_SPI | |
691 | setup_spi(); | |
692 | #endif | |
693 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); | |
694 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); | |
695 | setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); | |
696 | ||
be2808c3 IR |
697 | read_vpd(CONFIG_SYS_I2C_EEPROM_BUS); |
698 | ||
f9162b15 AB |
699 | return 0; |
700 | } | |
701 | ||
702 | #ifdef CONFIG_CMD_BMODE | |
703 | static const struct boot_mode board_boot_modes[] = { | |
704 | /* 4 bit bus width */ | |
705 | {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | |
706 | {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | |
707 | {NULL, 0}, | |
708 | }; | |
709 | #endif | |
710 | ||
22d358da KL |
711 | void pmic_init(void) |
712 | { | |
713 | #define I2C_PMIC 0x2 | |
714 | #define DA9063_I2C_ADDR 0x58 | |
715 | #define DA9063_REG_BCORE2_CFG 0x9D | |
716 | #define DA9063_REG_BCORE1_CFG 0x9E | |
717 | #define DA9063_REG_BPRO_CFG 0x9F | |
718 | #define DA9063_REG_BIO_CFG 0xA0 | |
719 | #define DA9063_REG_BMEM_CFG 0xA1 | |
720 | #define DA9063_REG_BPERI_CFG 0xA2 | |
721 | #define DA9063_BUCK_MODE_MASK 0xC0 | |
722 | #define DA9063_BUCK_MODE_MANUAL 0x00 | |
723 | #define DA9063_BUCK_MODE_SLEEP 0x40 | |
724 | #define DA9063_BUCK_MODE_SYNC 0x80 | |
725 | #define DA9063_BUCK_MODE_AUTO 0xC0 | |
726 | ||
727 | uchar val; | |
728 | ||
729 | i2c_set_bus_num(I2C_PMIC); | |
730 | ||
731 | i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1); | |
732 | val &= ~DA9063_BUCK_MODE_MASK; | |
733 | val |= DA9063_BUCK_MODE_SYNC; | |
734 | i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1); | |
735 | ||
736 | i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1); | |
737 | val &= ~DA9063_BUCK_MODE_MASK; | |
738 | val |= DA9063_BUCK_MODE_SYNC; | |
739 | i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1); | |
740 | ||
741 | i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1); | |
742 | val &= ~DA9063_BUCK_MODE_MASK; | |
743 | val |= DA9063_BUCK_MODE_SYNC; | |
744 | i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1); | |
745 | ||
746 | i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1); | |
747 | val &= ~DA9063_BUCK_MODE_MASK; | |
748 | val |= DA9063_BUCK_MODE_SYNC; | |
749 | i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1); | |
750 | ||
751 | i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1); | |
752 | val &= ~DA9063_BUCK_MODE_MASK; | |
753 | val |= DA9063_BUCK_MODE_SYNC; | |
754 | i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1); | |
755 | ||
756 | i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1); | |
757 | val &= ~DA9063_BUCK_MODE_MASK; | |
758 | val |= DA9063_BUCK_MODE_SYNC; | |
759 | i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1); | |
760 | } | |
761 | ||
f9162b15 AB |
762 | int board_late_init(void) |
763 | { | |
764 | #ifdef CONFIG_CMD_BMODE | |
765 | add_board_boot_modes(board_boot_modes); | |
766 | #endif | |
0c344e6e AS |
767 | |
768 | #ifdef CONFIG_VIDEO_IPUV3 | |
f9162b15 AB |
769 | /* We need at least 200ms between power on and backlight on |
770 | * as per specifications from CHI MEI */ | |
771 | mdelay(250); | |
772 | ||
54971ac6 AB |
773 | /* enable backlight PWM 1 */ |
774 | pwm_init(0, 0, 0); | |
775 | ||
776 | /* duty cycle 5000000ns, period: 5000000ns */ | |
777 | pwm_config(0, 5000000, 5000000); | |
778 | ||
f9162b15 AB |
779 | /* Backlight Power */ |
780 | gpio_direction_output(LVDS_BACKLIGHT_GP, 1); | |
781 | ||
54971ac6 | 782 | pwm_enable(0); |
0c344e6e | 783 | #endif |
54971ac6 | 784 | |
22d358da KL |
785 | /* board specific pmic init */ |
786 | pmic_init(); | |
787 | ||
f9162b15 AB |
788 | return 0; |
789 | } | |
790 | ||
791 | int checkboard(void) | |
792 | { | |
793 | printf("BOARD: %s\n", CONFIG_BOARD_NAME); | |
794 | return 0; | |
795 | } |