[people/ms/u-boot.git] / board / grinn / liteboard / board.c

/*
 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
 * Copyright (C) 2016 Grinn
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/clock.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/litesom.h>
#include <asm/arch/mx6ul_pins.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <linux/sizes.h>
#include <linux/fb.h>
#include <miiphy.h>
#include <mmc.h>
#include <netdev.h>
#include <spl.h>
#include <usb.h>
#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
	PAD_CTL_SPEED_HIGH   |                                   \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)

#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)

#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)

static iomux_v3_cfg_t const uart1_pads[] = {
	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const sd_pads[] = {
	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

	/* CD */
	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec1_pads[] = {
	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};

static void setup_iomux_fec(void)
{
	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
}
#endif

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}

#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};

#define SD_CD_GPIO	IMX_GPIO_NR(1, 19)

static int mmc_get_env_devno(void)
{
	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
	int dev_no;
	u32 bootsel;

	bootsel = (soc_sbmr & 0x000000FF) >> 6;

	/* If not boot from sd/mmc, use default value */
	if (bootsel != 1)
		return CONFIG_SYS_MMC_ENV_DEV;

	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
	dev_no = (soc_sbmr & 0x00001800) >> 11;

	return dev_no;
}

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		ret = !gpio_get_value(SD_CD_GPIO);
		break;
	case USDHC2_BASE_ADDR:
		ret = 1;
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int ret;

	/* SD */
	imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
	gpio_direction_input(SD_CD_GPIO);
	sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

	ret = fsl_esdhc_initialize(bis, &sd_cfg);
	if (ret) {
		printf("Warning: failed to initialize mmc dev 0 (SD)\n");
		return ret;
	}

	return litesom_mmc_init(bis);
}

static int check_mmc_autodetect(void)
{
	char *autodetect_str = getenv("mmcautodetect");

	if ((autodetect_str != NULL) &&
	    (strcmp(autodetect_str, "yes") == 0)) {
		return 1;
	}

	return 0;
}

void board_late_mmc_init(void)
{
	char cmd[32];
	char mmcblk[32];
	u32 dev_no = mmc_get_env_devno();

	if (!check_mmc_autodetect())
		return;

	env_set_ulong("mmcdev", dev_no);

	/* Set mmcblk env */
	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
		dev_no);
	env_set("mmcroot", mmcblk);

	sprintf(cmd, "mmc dev %d", dev_no);
	run_command(cmd, 0);
}
#endif

#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
	setup_iomux_fec();

	return fecmxc_initialize(bis);
}

static int setup_fec(void)
{
	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	int ret;

	/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
	   set gpr1[17]*/
	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);

	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
	if (ret)
		return ret;

	enable_enet_clk(1);

	return 0;
}
#endif

#ifdef CONFIG_USB_EHCI_MX6
int board_usb_phy_mode(int port)
{
	return USB_INIT_HOST;
}
#endif

int board_early_init_f(void)
{
	setup_iomux_uart();

	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef	CONFIG_FEC_MXC
	setup_fec();
#endif

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"sd",   MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
	{NULL,	 0},
};
#endif

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

#ifdef CONFIG_ENV_IS_IN_MMC
	board_late_mmc_init();
#endif

	return 0;
}

int checkboard(void)
{
	puts("Board: Grinn liteBoard\n");

	return 0;
}

#ifdef CONFIG_SPL_BUILD
void board_boot_order(u32 *spl_boot_list)
{
	struct src *psrc = (struct src *)SRC_BASE_ADDR;
	unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
	unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
	unsigned port = (reg >> 11) & 0x1;

	if (port == 0) {
		spl_boot_list[0] = BOOT_DEVICE_MMC1;
		spl_boot_list[1] = BOOT_DEVICE_MMC2;
	} else {
		spl_boot_list[0] = BOOT_DEVICE_MMC2;
		spl_boot_list[1] = BOOT_DEVICE_MMC1;
	}
}

void board_init_f(ulong dummy)
{
	litesom_init_f();
}
#endif
Commit	Line	Data
c9e40e65 MN	1	/*
	2	* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
	3	* Copyright (C) 2016 Grinn
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <asm/arch/clock.h>
	9	#include <asm/arch/iomux.h>
	10	#include <asm/arch/imx-regs.h>
	11	#include <asm/arch/crm_regs.h>
d4b1b527	12	#include <asm/arch/litesom.h>
c9e40e65 MN	13	#include <asm/arch/mx6ul_pins.h>
	14	#include <asm/arch/mx6-pins.h>
	15	#include <asm/arch/sys_proto.h>
	16	#include <asm/gpio.h>
552a848e SB	17	#include <asm/mach-imx/iomux-v3.h>
552a848e SB	18	#include <asm/mach-imx/boot_mode.h>
c9e40e65 MN	19	#include <asm/io.h>
	20	#include <common.h>
	21	#include <fsl_esdhc.h>
	22	#include <linux/sizes.h>
	23	#include <linux/fb.h>
c9e40e65 MN	24	#include <miiphy.h>
	25	#include <mmc.h>
	26	#include <netdev.h>
	27	#include <spl.h>
	28	#include <usb.h>
	29	#include <usb/ehci-ci.h>
	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	34	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	35	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	36
	37	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	38	PAD_CTL_PUS_22K_UP \| PAD_CTL_SPEED_LOW \| \
	39	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	40
	41	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
	42	PAD_CTL_SPEED_HIGH \| \
	43	PAD_CTL_DSE_48ohm \| PAD_CTL_SRE_FAST)
	44
	45	#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
	46	PAD_CTL_DSE_48ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_ODE)
	47
	48	#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	49
	50	static iomux_v3_cfg_t const uart1_pads[] = {
	51	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	52	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	53	};
	54
	55	static iomux_v3_cfg_t const sd_pads[] = {
	56	MX6_PAD_SD1_CLK__USDHC1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	57	MX6_PAD_SD1_CMD__USDHC1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	58	MX6_PAD_SD1_DATA0__USDHC1_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	59	MX6_PAD_SD1_DATA1__USDHC1_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	60	MX6_PAD_SD1_DATA2__USDHC1_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	61	MX6_PAD_SD1_DATA3__USDHC1_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	62
	63	/* CD */
	64	MX6_PAD_UART1_RTS_B__GPIO1_IO19 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	65	};
	66
	67	#ifdef CONFIG_FEC_MXC
	68	static iomux_v3_cfg_t const fec1_pads[] = {
	69	MX6_PAD_GPIO1_IO06__ENET1_MDIO \| MUX_PAD_CTRL(MDIO_PAD_CTRL),
	70	MX6_PAD_GPIO1_IO07__ENET1_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	71	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	72	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	73	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	74	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 \| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
	75	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	76	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	77	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	78	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	79	};
	80
	81	static void setup_iomux_fec(void)
	82	{
	83	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
	84	}
	85	#endif
	86
	87	static void setup_iomux_uart(void)
88	{
89	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
90	}
91
92	#ifdef CONFIG_FSL_ESDHC
93	static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
94
95	#define SD_CD_GPIO IMX_GPIO_NR(1, 19)
96
97	static int mmc_get_env_devno(void)
98	{
99	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
100	int dev_no;
101	u32 bootsel;
102
103	bootsel = (soc_sbmr & 0x000000FF) >> 6;
104
105	/* If not boot from sd/mmc, use default value */
106	if (bootsel != 1)
107	return CONFIG_SYS_MMC_ENV_DEV;
108
109	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
110	dev_no = (soc_sbmr & 0x00001800) >> 11;
111
112	return dev_no;
113	}
114
115	int board_mmc_getcd(struct mmc *mmc)
116	{
117	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
118	int ret = 0;
119
120	switch (cfg->esdhc_base) {
121	case USDHC1_BASE_ADDR:
122	ret = !gpio_get_value(SD_CD_GPIO);
123	break;
124	case USDHC2_BASE_ADDR:
125	ret = 1;
126	break;
127	}
128
129	return ret;
130	}
131
132	int board_mmc_init(bd_t *bis)
133	{
134	int ret;
135
136	/* SD */
137	imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
138	gpio_direction_input(SD_CD_GPIO);
139	sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
140
141	ret = fsl_esdhc_initialize(bis, &sd_cfg);
142	if (ret) {
143	printf("Warning: failed to initialize mmc dev 0 (SD)\n");
144	return ret;
145	}
146
147	return litesom_mmc_init(bis);
148	}
149
150	static int check_mmc_autodetect(void)
151	{
152	char *autodetect_str = getenv("mmcautodetect");
153
154	if ((autodetect_str != NULL) &&
155	(strcmp(autodetect_str, "yes") == 0)) {
156	return 1;
157	}
158
159	return 0;
160	}
161
162	void board_late_mmc_init(void)
163	{
164	char cmd[32];
165	char mmcblk[32];
166	u32 dev_no = mmc_get_env_devno();
167
168	if (!check_mmc_autodetect())
169	return;
170
018f5303	171	env_set_ulong("mmcdev", dev_no);
c9e40e65 MN	172
	173	/* Set mmcblk env */
	174	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
	175	dev_no);
382bee57	176	env_set("mmcroot", mmcblk);
c9e40e65 MN	177
	178	sprintf(cmd, "mmc dev %d", dev_no);
	179	run_command(cmd, 0);
	180	}
	181	#endif
	182
	183	#ifdef CONFIG_FEC_MXC
	184	int board_eth_init(bd_t *bis)
	185	{
	186	setup_iomux_fec();
	187
	188	return fecmxc_initialize(bis);
	189	}
	190
	191	static int setup_fec(void)
	192	{
	193	struct iomuxc const iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	194	int ret;
	195
	196	/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
	197	set gpr1[17]*/
	198	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
	199	IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
	200
	201	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
	202	if (ret)
	203	return ret;
	204
	205	enable_enet_clk(1);
	206
	207	return 0;
	208	}
	209	#endif
	210
	211	#ifdef CONFIG_USB_EHCI_MX6
	212	int board_usb_phy_mode(int port)
	213	{
	214	return USB_INIT_HOST;
	215	}
	216	#endif
	217
	218	int board_early_init_f(void)
	219	{
	220	setup_iomux_uart();
	221
	222	return 0;
	223	}
	224
	225	int board_init(void)
	226	{
	227	/* Address of boot parameters */
	228	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	229
	230	#ifdef CONFIG_FEC_MXC
	231	setup_fec();
	232	#endif
	233
	234	return 0;
	235	}
	236
	237	#ifdef CONFIG_CMD_BMODE
	238	static const struct boot_mode board_boot_modes[] = {
	239	/* 4 bit bus width */
	240	{"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
241	{"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
242	{NULL, 0},
243	};
244	#endif
245
246	int board_late_init(void)
247	{
248	#ifdef CONFIG_CMD_BMODE
249	add_board_boot_modes(board_boot_modes);
250	#endif
251
252	#ifdef CONFIG_ENV_IS_IN_MMC
253	board_late_mmc_init();
254	#endif
255
256	return 0;
257	}
258
259	int checkboard(void)
260	{
261	puts("Board: Grinn liteBoard\n");
262
263	return 0;
264	}
265
266	#ifdef CONFIG_SPL_BUILD
267	void board_boot_order(u32 *spl_boot_list)
268	{
269	struct src psrc = (struct src )SRC_BASE_ADDR;
270	unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
271	unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
272	unsigned port = (reg >> 11) & 0x1;
273
274	if (port == 0) {
275	spl_boot_list[0] = BOOT_DEVICE_MMC1;
276	spl_boot_list[1] = BOOT_DEVICE_MMC2;
277	} else {
278	spl_boot_list[0] = BOOT_DEVICE_MMC2;
279	spl_boot_list[1] = BOOT_DEVICE_MMC1;
280	}
281	}
282
283	void board_init_f(ulong dummy)
284	{
285	litesom_init_f();
286	}
287	#endif