[people/ms/u-boot.git] / board / hale / tt01 / tt01.c

/*
 * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
 * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <netdev.h>
#include <command.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <mc13783.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <errno.h>

DECLARE_GLOBAL_DATA_PTR;

#define BOARD_STRING	"Board: HALE TT-01"

/* Clock configuration */
#define CCM_CCMR_SETUP		0x074B0BF5

static void board_setup_clocks(void)
{
	struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
	volatile int wait = 0x10000;

	writel(CCM_CCMR_SETUP, &ccm->ccmr);
	while (wait--)
		;

	writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
	writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);

	/* Set up clock to 532MHz */
	writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
			PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
			PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
			PDR0_MCU_PODF(0), &ccm->pdr0);
	writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
			&ccm->mpctl);
	writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
			&ccm->spctl);
}

/* DRAM configuration */

#define ESDMISC_MDDR_SETUP	0x00000004
#define ESDMISC_MDDR_RESET_DL	0x0000000c
/*
 * decoding magic 0x6ac73a = 0b 0110 1010   1100 0111   0011 1010 below:
 *   tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
 *   tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
 *   tRCD = 011, tRC = 010
 *  note: all but tWTR (1), tRC (111) are reset defaults,
 *     the same values work in the jtag configuration
 *
 *  Bluetechnix setup has 0x75e73a (for 128MB) =
 *			0b 0111 0101   1110 0111   0011 1010
 *   tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
 *   tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
 *   tRCD = 011, tRC = 010
 */
#define ESDCFG0_MDDR_SETUP	0x006ac73a
#define ESDCTL_ROW_COL		(ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
#define ESDCTL_SETTINGS		(ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
				 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
#define ESDCTL_PRECHARGE	(ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
#define ESDCTL_AUTOREFRESH	(ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
#define ESDCTL_LOADMODEREG	(ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
#define ESDCTL_RW		ESDCTL_SETTINGS

static void board_setup_sdram(void)
{
	u32 *pad;
	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;

	/*
	 * setup pad control for the controller pins
	 * no loopback, no pull, no keeper, no open drain,
	 * standard input, standard drive, slow slew rate
	 */
	for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
			pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
		*pad = 0;

	/* set up MX31 DDR Memory Controller */
	writel(ESDMISC_MDDR_SETUP, &esdc->misc);
	writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);

	/* perform DDR init sequence for CSD0 */
	writel(ESDCTL_PRECHARGE, &esdc->ctl0);
	writel(0x12344321, CSD0_BASE+0x0f00);
	writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
	writel(0x12344321, CSD0_BASE);
	writel(0x12344321, CSD0_BASE);
	writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
	writeb(0xda, CSD0_BASE+0x33);
	writeb(0xff, CSD0_BASE+0x1000000);
	writel(ESDCTL_RW, &esdc->ctl0);
	writel(0xDEADBEEF, CSD0_BASE);
	writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
}

static void tt01_spi3_hw_init(void)
{
	/* CSPI3 */
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
	/* CSPI3, SS0 = Atlas */
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));

	/* start CSPI3 clock (3 = always on except if PLL off) */
	setbits_le32(CCM_CGR0, 3 << 16);
}

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
			PHYS_SDRAM_1_SIZE);
	return 0;
}

int board_early_init_f(void)
{
	/* CS4: FPGA incl. network controller */
	struct mxc_weimcs cs4 = {
		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 28, 1,  7,  6),
		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
		CSCR_L(4,  4,   4,  10,  4,  0,  5,  4,  0,  0,   0,   1),
		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
		CSCR_A(4,   4,  4,  4,  0,  1,  4,  3,  0,  0,  0,  0,  1,   0)
	};

	/* this seems essential, won't start without, but why? */
	writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);

	board_setup_clocks();
	board_setup_sdram();
	mxc_setup_weimcs(4, &cs4);

	/* Setup UART2 and SPI3 pins */
	mx31_uart2_hw_init();
	tt01_spi3_hw_init();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	return 0;
}

int board_late_init(void)
{
#ifdef CONFIG_HW_WATCHDOG
	hw_watchdog_init();
#endif

	return 0;
}

int checkboard(void)
{
	puts(BOARD_STRING "\n");
	return 0;
}

#ifdef CONFIG_MXC_MMC
int board_mmc_init(bd_t *bis)
{
	u32 val;
	struct pmic *p;
	int ret;

	/*
	* this is the first driver to use the pmic, so call
	* pmic_init() here. board_late_init() is too late for
	* the MMC driver.
	*/

	ret = pmic_init(I2C_PMIC);
	if (ret)
		return ret;

	p = pmic_get("FSL_PMIC");
	if (!p)
		return -ENODEV;

	/* configure pins for SDHC1 only */
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));

	/* turn on power V_MMC1 */
	if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
		pmic_reg_write(p, REG_MODE_1, val | VMMC1EN);

	return mxc_mmc_init(bis);
}
#endif

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_SMC911X
	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
	return rc;
}

#ifdef CONFIG_CONSOLE_EXTRA_INFO
void video_get_info_str(int line_number, char *info)
{
	u32 srev = get_cpu_rev();

	switch (line_number) {
	case 2:
		sprintf(info, " CPU  : Freescale i.MX31 rev %d.%d%s at %d MHz",
			(srev & 0xF0) >> 4, (srev & 0x0F),
			((srev & 0x8000) ? " unknown" : ""),
		mxc_get_clock(MXC_ARM_CLK) / 1000000);
		break;
	case 3:
		strcpy(info, " " BOARD_STRING);
		break;
	default:
		info[0] = 0;
	}
}
#endif
Commit	Line	Data
4d86dd02 HR	1	/*
	2	* (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
	3	* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
	4	* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
4d86dd02 HR	7	*/
	8
	9	#include <common.h>
	10	#include <netdev.h>
	11	#include <command.h>
c7336815	12	#include <power/pmic.h>
f353518f HR	13	#include <fsl_pmic.h>
f353518f HR	14	#include <mc13783.h>
4d86dd02 HR	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/sys_proto.h>
	17	#include <asm/io.h>
c7336815	18	#include <errno.h>
4d86dd02 HR	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	#define BOARD_STRING "Board: HALE TT-01"
	23
	24	/* Clock configuration */
	25	#define CCM_CCMR_SETUP 0x074B0BF5
	26
	27	static void board_setup_clocks(void)
	28	{
	29	struct clock_control_regs ccm = (struct clock_control_regs ) CCM_BASE;
	30	volatile int wait = 0x10000;
	31
	32	writel(CCM_CCMR_SETUP, &ccm->ccmr);
	33	while (wait--)
	34	;
	35
	36	writel(CCM_CCMR_SETUP \| CCMR_MPE, &ccm->ccmr);
	37	writel((CCM_CCMR_SETUP \| CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
	38
	39	/* Set up clock to 532MHz */
9e0081d5	40	writel(PDR0_CSI_PODF(0x3f) \| PDR0_CSI_PRDF(7) \| PDR0_PER_PODF(7) \|
4d86dd02 HR	41	PDR0_HSP_PODF(3) \| PDR0_NFC_PODF(5) \|
	42	PDR0_IPG_PODF(1) \| PDR0_MAX_PODF(3) \|
	43	PDR0_MCU_PODF(0), &ccm->pdr0);
	44	writel(PLL_PD(0) \| PLL_MFD(51) \| PLL_MFI(10) \| PLL_MFN(12),
	45	&ccm->mpctl);
	46	writel(PLL_PD(1) \| PLL_MFD(4) \| PLL_MFI(12) \| PLL_MFN(1),
	47	&ccm->spctl);
	48	}
	49
	50	/* DRAM configuration */
	51
	52	#define ESDMISC_MDDR_SETUP 0x00000004
	53	#define ESDMISC_MDDR_RESET_DL 0x0000000c
	54	/*
	55	* decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
	56	* tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
	57	* tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
	58	* tRCD = 011, tRC = 010
	59	* note: all but tWTR (1), tRC (111) are reset defaults,
	60	* the same values work in the jtag configuration
	61	*
	62	* Bluetechnix setup has 0x75e73a (for 128MB) =
	63	* 0b 0111 0101 1110 0111 0011 1010
	64	* tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
	65	* tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
	66	* tRCD = 011, tRC = 010
	67	*/
	68	#define ESDCFG0_MDDR_SETUP 0x006ac73a
	69	#define ESDCTL_ROW_COL (ESDCTL_SDE \| ESDCTL_ROW(2) \| ESDCTL_COL(2))
	70	#define ESDCTL_SETTINGS (ESDCTL_ROW_COL \| ESDCTL_SREFR(3) \| \
	71	ESDCTL_DSIZ(2) \| ESDCTL_BL(1))
	72	#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL \| ESDCTL_CMD_PRECHARGE)
	73	#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL \| ESDCTL_CMD_AUTOREFRESH)
	74	#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL \| ESDCTL_CMD_LOADMODEREG)
	75	#define ESDCTL_RW ESDCTL_SETTINGS
	76
	77	static void board_setup_sdram(void)
	78	{
	79	u32 *pad;
	80	struct esdc_regs esdc = (struct esdc_regs )ESDCTL_BASE_ADDR;
	81
	82	/*
	83	* setup pad control for the controller pins
	84	* no loopback, no pull, no keeper, no open drain,
	85	* standard input, standard drive, slow slew rate
	86	*/
	87	for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
	88	pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
	89	*pad = 0;
	90
	91	/* set up MX31 DDR Memory Controller */
	92	writel(ESDMISC_MDDR_SETUP, &esdc->misc);
	93	writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
	94
	95	/* perform DDR init sequence for CSD0 */
	96	writel(ESDCTL_PRECHARGE, &esdc->ctl0);
	97	writel(0x12344321, CSD0_BASE+0x0f00);
	98	writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
	99	writel(0x12344321, CSD0_BASE);
	100	writel(0x12344321, CSD0_BASE);
	101	writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
	102	writeb(0xda, CSD0_BASE+0x33);
	103	writeb(0xff, CSD0_BASE+0x1000000);
	104	writel(ESDCTL_RW, &esdc->ctl0);
105	writel(0xDEADBEEF, CSD0_BASE);
106	writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
107	}
108
109	static void tt01_spi3_hw_init(void)
110	{
111	/* CSPI3 */
112	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
113	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
114	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
115	/* CSPI3, SS0 = Atlas */
116	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
117
118	/* start CSPI3 clock (3 = always on except if PLL off) */
119	setbits_le32(CCM_CGR0, 3 << 16);
120	}
121
122	int dram_init(void)
123	{
124	/* dram_init must store complete ramsize in gd->ram_size */
125	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
126	PHYS_SDRAM_1_SIZE);
127	return 0;
128	}
129
130	int board_early_init_f(void)
131	{
132	/* CS4: FPGA incl. network controller */
133	struct mxc_weimcs cs4 = {
134	/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
135	CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
136	/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
137	CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
138	/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
139	CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
140	};
141
142	/* this seems essential, won't start without, but why? */
143	writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
144
145	board_setup_clocks();
146	board_setup_sdram();
147	mxc_setup_weimcs(4, &cs4);
148
149	/* Setup UART2 and SPI3 pins */
150	mx31_uart2_hw_init();
151	tt01_spi3_hw_init();
152
153	return 0;
154	}
155
156	int board_init(void)
157	{
158	/* address of boot parameters */
159	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
160	return 0;
161	}
162
163	int board_late_init(void)
164	{
4d86dd02	165	#ifdef CONFIG_HW_WATCHDOG
abbab703	166	hw_watchdog_init();
4d86dd02 HR	167	#endif
	168
	169	return 0;
	170	}
	171
	172	int checkboard(void)
	173	{
	174	puts(BOARD_STRING "\n");
	175	return 0;
	176	}
	177
f353518f HR	178	#ifdef CONFIG_MXC_MMC
	179	int board_mmc_init(bd_t *bis)
	180	{
	181	u32 val;
	182	struct pmic *p;
c7336815	183	int ret;
f353518f HR	184
	185	/*
	186	* this is the first driver to use the pmic, so call
	187	* pmic_init() here. board_late_init() is too late for
	188	* the MMC driver.
	189	*/
c7336815 ŁM	190
	191	ret = pmic_init(I2C_PMIC);
	192	if (ret)
	193	return ret;
	194
	195	p = pmic_get("FSL_PMIC");
	196	if (!p)
	197	return -ENODEV;
f353518f HR	198
	199	/* configure pins for SDHC1 only */
	200	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
	201	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
	202	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
	203	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
	204	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
	205	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
	206
	207	/* turn on power V_MMC1 */
	208	if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
	209	pmic_reg_write(p, REG_MODE_1, val \| VMMC1EN);
	210
	211	return mxc_mmc_init(bis);
	212	}
	213	#endif
	214
4d86dd02 HR	215	int board_eth_init(bd_t *bis)
	216	{
	217	int rc = 0;
	218	#ifdef CONFIG_SMC911X
	219	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
	220	#endif
	221	return rc;
	222	}
d1300f76 HR	223
	224	#ifdef CONFIG_CONSOLE_EXTRA_INFO
	225	void video_get_info_str(int line_number, char *info)
	226	{
	227	u32 srev = get_cpu_rev();
	228
	229	switch (line_number) {
	230	case 2:
	231	sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz",
	232	(srev & 0xF0) >> 4, (srev & 0x0F),
	233	((srev & 0x8000) ? " unknown" : ""),
	234	mxc_get_clock(MXC_ARM_CLK) / 1000000);
	235	break;
	236	case 3:
	237	strcpy(info, " " BOARD_STRING);
	238	break;
	239	default:
	240	info[0] = 0;
	241	}
	242	}
	243	#endif