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Commit | Line | Data |
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5a4dcfac GJ |
1 | /* |
2 | * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> | |
baf37f06 | 3 | * Copyright (C) 2013 Imagination Technologies |
5a4dcfac | 4 | * |
0b17998e | 5 | * SPDX-License-Identifier: GPL-2.0 |
5a4dcfac GJ |
6 | */ |
7 | ||
8 | #include <common.h> | |
ba21a453 | 9 | #include <ide.h> |
f1957499 | 10 | #include <netdev.h> |
81f98bbd | 11 | #include <pci.h> |
baf37f06 PB |
12 | #include <pci_gt64120.h> |
13 | #include <pci_msc01.h> | |
3ced12a0 | 14 | #include <rtc.h> |
5a4dcfac | 15 | |
feaa6066 | 16 | #include <asm/addrspace.h> |
01564315 GJ |
17 | #include <asm/io.h> |
18 | #include <asm/malta.h> | |
19 | ||
a257f626 PB |
20 | #include "superio.h" |
21 | ||
088454cd SG |
22 | DECLARE_GLOBAL_DATA_PTR; |
23 | ||
baf37f06 PB |
24 | enum core_card { |
25 | CORE_UNKNOWN, | |
26 | CORE_LV, | |
27 | CORE_FPGA6, | |
28 | }; | |
29 | ||
30 | enum sys_con { | |
31 | SYSCON_UNKNOWN, | |
32 | SYSCON_GT64120, | |
33 | SYSCON_MSC01, | |
34 | }; | |
35 | ||
e0ada631 PB |
36 | static void malta_lcd_puts(const char *str) |
37 | { | |
38 | int i; | |
39 | void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); | |
40 | ||
41 | /* print up to 8 characters of the string */ | |
b4141195 | 42 | for (i = 0; i < min((int)strlen(str), 8); i++) { |
e0ada631 PB |
43 | __raw_writel(str[i], reg); |
44 | reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; | |
45 | } | |
46 | ||
47 | /* fill the rest of the display with spaces */ | |
48 | for (; i < 8; i++) { | |
49 | __raw_writel(' ', reg); | |
50 | reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; | |
51 | } | |
52 | } | |
53 | ||
baf37f06 PB |
54 | static enum core_card malta_core_card(void) |
55 | { | |
56 | u32 corid, rev; | |
8061cfc9 | 57 | const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); |
baf37f06 | 58 | |
8061cfc9 | 59 | rev = __raw_readl(reg); |
baf37f06 PB |
60 | corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; |
61 | ||
62 | switch (corid) { | |
63 | case MALTA_REVISION_CORID_CORE_LV: | |
64 | return CORE_LV; | |
65 | ||
66 | case MALTA_REVISION_CORID_CORE_FPGA6: | |
67 | return CORE_FPGA6; | |
68 | ||
69 | default: | |
70 | return CORE_UNKNOWN; | |
71 | } | |
72 | } | |
73 | ||
74 | static enum sys_con malta_sys_con(void) | |
75 | { | |
76 | switch (malta_core_card()) { | |
77 | case CORE_LV: | |
78 | return SYSCON_GT64120; | |
79 | ||
80 | case CORE_FPGA6: | |
81 | return SYSCON_MSC01; | |
82 | ||
83 | default: | |
84 | return SYSCON_UNKNOWN; | |
85 | } | |
86 | } | |
87 | ||
088454cd | 88 | int initdram(void) |
5a4dcfac | 89 | { |
088454cd SG |
90 | gd->ram_size = CONFIG_SYS_MEM_SIZE; |
91 | ||
92 | return 0; | |
5a4dcfac GJ |
93 | } |
94 | ||
95 | int checkboard(void) | |
96 | { | |
baf37f06 PB |
97 | enum core_card core; |
98 | ||
a187559e | 99 | malta_lcd_puts("U-Boot"); |
baf37f06 PB |
100 | puts("Board: MIPS Malta"); |
101 | ||
102 | core = malta_core_card(); | |
103 | switch (core) { | |
104 | case CORE_LV: | |
105 | puts(" CoreLV"); | |
106 | break; | |
107 | ||
108 | case CORE_FPGA6: | |
109 | puts(" CoreFPGA6"); | |
110 | break; | |
111 | ||
112 | default: | |
113 | puts(" CoreUnknown"); | |
114 | } | |
115 | ||
116 | putc('\n'); | |
5a4dcfac GJ |
117 | return 0; |
118 | } | |
01564315 | 119 | |
f1957499 GJ |
120 | int board_eth_init(bd_t *bis) |
121 | { | |
122 | return pci_eth_init(bis); | |
123 | } | |
124 | ||
01564315 GJ |
125 | void _machine_restart(void) |
126 | { | |
127 | void __iomem *reset_base; | |
128 | ||
129 | reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); | |
130 | __raw_writel(GORESET, reset_base); | |
28c8c3d4 | 131 | mdelay(1000); |
01564315 | 132 | } |
feaa6066 | 133 | |
a257f626 PB |
134 | int board_early_init_f(void) |
135 | { | |
91ec615e | 136 | ulong io_base; |
baf37f06 PB |
137 | |
138 | /* choose correct PCI I/O base */ | |
139 | switch (malta_sys_con()) { | |
140 | case SYSCON_GT64120: | |
91ec615e | 141 | io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); |
baf37f06 PB |
142 | break; |
143 | ||
144 | case SYSCON_MSC01: | |
91ec615e | 145 | io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); |
baf37f06 PB |
146 | break; |
147 | ||
148 | default: | |
149 | return -1; | |
150 | } | |
151 | ||
91ec615e | 152 | set_io_port_base(io_base); |
19a5ef60 | 153 | |
a257f626 | 154 | /* setup FDC37M817 super I/O controller */ |
91ec615e | 155 | malta_superio_init(); |
a257f626 PB |
156 | |
157 | return 0; | |
158 | } | |
159 | ||
3ced12a0 PB |
160 | int misc_init_r(void) |
161 | { | |
162 | rtc_reset(); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
feaa6066 GJ |
167 | void pci_init_board(void) |
168 | { | |
81f98bbd | 169 | pci_dev_t bdf; |
bea12b78 PB |
170 | u32 val32; |
171 | u8 val8; | |
81f98bbd | 172 | |
baf37f06 PB |
173 | switch (malta_sys_con()) { |
174 | case SYSCON_GT64120: | |
baf37f06 PB |
175 | gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), |
176 | 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, | |
177 | 0x10000000, 0x10000000, 128 * 1024 * 1024, | |
178 | 0x00000000, 0x00000000, 0x20000); | |
179 | break; | |
180 | ||
181 | default: | |
182 | case SYSCON_MSC01: | |
baf37f06 PB |
183 | msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), |
184 | 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, | |
185 | MALTA_MSC01_PCIMEM_MAP, | |
186 | CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), | |
187 | MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, | |
188 | 0x00000000, MALTA_MSC01_PCIIO_SIZE); | |
189 | break; | |
190 | } | |
81f98bbd PB |
191 | |
192 | bdf = pci_find_device(PCI_VENDOR_ID_INTEL, | |
193 | PCI_DEVICE_ID_INTEL_82371AB_0, 0); | |
194 | if (bdf == -1) | |
195 | panic("Failed to find PIIX4 PCI bridge\n"); | |
196 | ||
197 | /* setup PCI interrupt routing */ | |
198 | pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); | |
199 | pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); | |
200 | pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); | |
201 | pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); | |
bea12b78 PB |
202 | |
203 | /* mux SERIRQ onto SERIRQ pin */ | |
204 | pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32); | |
205 | val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ; | |
206 | pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32); | |
207 | ||
208 | /* enable SERIRQ - Linux currently depends upon this */ | |
209 | pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); | |
210 | val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; | |
211 | pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); | |
ba21a453 PB |
212 | |
213 | bdf = pci_find_device(PCI_VENDOR_ID_INTEL, | |
214 | PCI_DEVICE_ID_INTEL_82371AB, 0); | |
215 | if (bdf == -1) | |
216 | panic("Failed to find PIIX4 IDE controller\n"); | |
217 | ||
218 | /* enable bus master & IO access */ | |
219 | val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; | |
220 | pci_write_config_dword(bdf, PCI_COMMAND, val32); | |
221 | ||
222 | /* set latency */ | |
223 | pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40); | |
224 | ||
225 | /* enable IDE/ATA */ | |
226 | pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI, | |
227 | PCI_CFG_PIIX4_IDETIM_IDE); | |
228 | pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC, | |
229 | PCI_CFG_PIIX4_IDETIM_IDE); | |
feaa6066 | 230 | } |