[people/ms/u-boot.git] / board / incaip / lowlevel_init.S

/*
 *  Memory sub-system initialization code for INCA-IP development board.
 *
 *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#include <config.h>
#include <asm/regdef.h>


#define EBU_MODUL_BASE		0xB8000200
#define EBU_CLC(value)		0x0000(value)
#define EBU_CON(value)		0x0010(value)
#define EBU_ADDSEL0(value)	0x0020(value)
#define EBU_ADDSEL1(value)	0x0024(value)
#define EBU_ADDSEL2(value)	0x0028(value)
#define EBU_BUSCON0(value)	0x0060(value)
#define EBU_BUSCON1(value)	0x0064(value)
#define EBU_BUSCON2(value)	0x0068(value)

#define MC_MODUL_BASE		0xBF800000
#define MC_ERRCAUSE(value)	0x0100(value)
#define MC_ERRADDR(value)	0x0108(value)
#define MC_IOGP(value)		0x0800(value)
#define MC_SELFRFSH(value)	0x0A00(value)
#define MC_CTRLENA(value)	0x1000(value)
#define MC_MRSCODE(value)	0x1008(value)
#define MC_CFGDW(value)		0x1010(value)
#define MC_CFGPB0(value)	0x1018(value)
#define MC_LATENCY(value)	0x1038(value)
#define MC_TREFRESH(value)	0x1040(value)

#define CGU_MODUL_BASE		0xBF107000
#define CGU_PLL1CR(value)	0x0008(value)
#define CGU_DIVCR(value)	0x0010(value)
#define CGU_MUXCR(value)	0x0014(value)
#define CGU_PLL1SR(value)	0x000C(value)

	.set	noreorder


/*
 * void ebu_init(long)
 *
 * a0 has the clock value we are going to run at
 */
	.globl	ebu_init
	.ent	ebu_init
ebu_init:
__ebu_init:

	li	t1, EBU_MODUL_BASE
	li	t2, 0xA0000041
	sw	t2, EBU_ADDSEL0(t1)
	li	t2, 0xA0800041
	sw	t2, EBU_ADDSEL2(t1)
	li	t2, 0xBE0000F1
	sw	t2, EBU_ADDSEL1(t1)

	li	t3, 100000000
	beq	a0, t3, 1f
	nop
	li	t3, 133000000
	beq	a0, t3, 2f
	nop
	li	t3, 150000000
	beq	a0, t3, 2f
	nop
	b	3f
	nop

	/* 100 MHz */
1:
	li	t2, 0x8841417D
	sw	t2, EBU_BUSCON0(t1)
	sw	t2, EBU_BUSCON2(t1)
	li	t2, 0x684142BD
	b	3f
	sw	t2, EBU_BUSCON1(t1)	/* delay slot */

	/* 133 or 150 MHz */
2:
	li	t2, 0x8841417E
	sw	t2, EBU_BUSCON0(t1)
	sw	t2, EBU_BUSCON2(t1)
	li	t2, 0x684143FD
	sw	t2, EBU_BUSCON1(t1)
3:
	jr	ra
	nop

	.end	ebu_init


/*
 * void cgu_init(long)
 *
 * a0 has the clock value
 */
	.globl	cgu_init
	.ent	cgu_init
cgu_init:
__cgu_init:

	li	t1, CGU_MODUL_BASE

	li	t3, 100000000
	beq	a0, t3, 1f
	nop
	li	t3, 133000000
	beq	a0, t3, 2f
	nop
	li	t3, 150000000
	beq	a0, t3, 3f
	nop
	b	5f
	nop

	/* 100 MHz clock */
1:
	li	t2, 0x80000014
	sw	t2, CGU_DIVCR(t1)
	li	t2, 0x80000000
	sw	t2, CGU_MUXCR(t1)
	li	t2, 0x800B0001
	b	5f
	sw	t2, CGU_PLL1CR(t1)	/* delay slot */

	/* 133 MHz clock */
2:
	li	t2, 0x80000054
	sw	t2, CGU_DIVCR(t1)
	li	t2, 0x80000000
	sw	t2, CGU_MUXCR(t1)
	li	t2, 0x800B0001
	b	5f
	sw	t2, CGU_PLL1CR(t1)	/* delay slot */

	/* 150 MHz clock */
3:
	li	t2, 0x80000017
	sw	t2, CGU_DIVCR(t1)
	li	t2, 0xC00B0001
	sw	t2, CGU_PLL1CR(t1)
	li	t3, 0x80000000
4:
	lw	t2, CGU_PLL1SR(t1)
	and	t2, t2, t3
	beq	t2, zero, 4b
	nop
	li	t2, 0x80000001
	sw	t2, CGU_MUXCR(t1)
5:
	jr	ra
	nop

	.end	cgu_init


/*
 * void sdram_init(long)
 *
 * a0 has the clock value
 */
	.globl	sdram_init
	.ent	sdram_init
sdram_init:
__sdram_init:

	li	t1, MC_MODUL_BASE

#if 0
	/* Disable memory controller before changing any of its registers */
	sw	zero, MC_CTRLENA(t1)
#endif

	li	t2, 100000000
	beq	a0, t2, 1f
	nop
	li	t2, 133000000
	beq	a0, t2, 2f
	nop
	li	t2, 150000000
	beq	a0, t2, 3f
	nop
	b	5f
	nop

	/* 100 MHz clock */
1:
	/* Set clock ratio (clkrat=1:1, rddel=3) */
	li	t2, 0x00000003
	sw	t2, MC_IOGP(t1)

	/* Set sdram refresh rate (4K/64ms @ 100MHz) */
	li	t2, 0x0000061A
	b	4f
	sw	t2, MC_TREFRESH(t1)

	/* 133 MHz clock */
2:
	/* Set clock ratio (clkrat=1:1, rddel=3) */
	li	t2, 0x00000003
	sw	t2, MC_IOGP(t1)

	/* Set sdram refresh rate (4K/64ms @ 133MHz) */
	li	t2, 0x00000822
	b	4f
	sw	t2, MC_TREFRESH(t1)

	/* 150 MHz clock */
3:
	/* Set clock ratio (clkrat=3:2, rddel=4) */
	li	t2, 0x00000014
	sw	t2, MC_IOGP(t1)

	/* Set sdram refresh rate (4K/64ms @ 150MHz) */
	li	t2, 0x00000927
	sw	t2, MC_TREFRESH(t1)

4:
	/* Clear Error log registers */
	sw	zero, MC_ERRCAUSE(t1)
	sw	zero, MC_ERRADDR(t1)

	/* Clear Power-down registers */
	sw	zero, MC_SELFRFSH(t1)

	/* Set CAS Latency */
	li	t2, 0x00000020		/* CL = 2 */
	sw	t2, MC_MRSCODE(t1)

	/* Set word width to 16 bit */
	li	t2, 0x2
	sw	t2, MC_CFGDW(t1)

	/* Set CS0 to SDRAM parameters */
	li	t2, 0x000014C9
	sw	t2, MC_CFGPB0(t1)

	/* Set SDRAM latency parameters */
	li	t2, 0x00026325		/* BC PC100 */
	sw	t2, MC_LATENCY(t1)

5:
	/* Finally enable the controller */
	li	t2, 0x00000001
	sw	t2, MC_CTRLENA(t1)

	jr	ra
	nop

	.end	sdram_init


	.globl	lowlevel_init
	.ent	lowlevel_init
lowlevel_init:

	/* Disable Watchdog.
	 */
	la	t9, disable_incaip_wdt
	jalr	t9
	nop

	/* EBU, CGU and SDRAM Initialization.
	 */
	li	a0, CONFIG_CPU_CLOCK_RATE
	move	t0, ra

	/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
	 * modify t0 and a0.
	 */
	bal	__cgu_init
	nop
	bal	__ebu_init
	nop
	bal	__sdram_init
	nop
	move	ra, t0

	jr	ra
	nop

	.end	lowlevel_init
Commit	Line	Data
c021880a WD	1	/*
	2	* Memory sub-system initialization code for INCA-IP development board.
	3	*
	4	* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
c021880a WD	7	*/
	8
	9	#include <config.h>
c021880a WD	10	#include <asm/regdef.h>
	11
	12
d4ca31c4 WD	13	#define EBU_MODUL_BASE 0xB8000200
	14	#define EBU_CLC(value) 0x0000(value)
	15	#define EBU_CON(value) 0x0010(value)
	16	#define EBU_ADDSEL0(value) 0x0020(value)
	17	#define EBU_ADDSEL1(value) 0x0024(value)
	18	#define EBU_ADDSEL2(value) 0x0028(value)
	19	#define EBU_BUSCON0(value) 0x0060(value)
	20	#define EBU_BUSCON1(value) 0x0064(value)
	21	#define EBU_BUSCON2(value) 0x0068(value)
	22
	23	#define MC_MODUL_BASE 0xBF800000
	24	#define MC_ERRCAUSE(value) 0x0100(value)
	25	#define MC_ERRADDR(value) 0x0108(value)
	26	#define MC_IOGP(value) 0x0800(value)
	27	#define MC_SELFRFSH(value) 0x0A00(value)
	28	#define MC_CTRLENA(value) 0x1000(value)
	29	#define MC_MRSCODE(value) 0x1008(value)
	30	#define MC_CFGDW(value) 0x1010(value)
	31	#define MC_CFGPB0(value) 0x1018(value)
	32	#define MC_LATENCY(value) 0x1038(value)
	33	#define MC_TREFRESH(value) 0x1040(value)
	34
	35	#define CGU_MODUL_BASE 0xBF107000
	36	#define CGU_PLL1CR(value) 0x0008(value)
	37	#define CGU_DIVCR(value) 0x0010(value)
	38	#define CGU_MUXCR(value) 0x0014(value)
	39	#define CGU_PLL1SR(value) 0x000C(value)
	40
	41	.set noreorder
c021880a	42
c021880a	43
7cb22f97 WD	44	/*
	45	* void ebu_init(long)
	46	*
	47	* a0 has the clock value we are going to run at
	48	*/
	49	.globl ebu_init
	50	.ent ebu_init
	51	ebu_init:
f013dacf	52	__ebu_init:
7cb22f97 WD	53
	54	li t1, EBU_MODUL_BASE
	55	li t2, 0xA0000041
	56	sw t2, EBU_ADDSEL0(t1)
	57	li t2, 0xA0800041
	58	sw t2, EBU_ADDSEL2(t1)
	59	li t2, 0xBE0000F1
	60	sw t2, EBU_ADDSEL1(t1)
	61
	62	li t3, 100000000
	63	beq a0, t3, 1f
	64	nop
	65	li t3, 133000000
	66	beq a0, t3, 2f
	67	nop
	68	li t3, 150000000
	69	beq a0, t3, 2f
	70	nop
	71	b 3f
	72	nop
c021880a	73
7cb22f97 WD	74	/* 100 MHz */
	75	1:
	76	li t2, 0x8841417D
	77	sw t2, EBU_BUSCON0(t1)
	78	sw t2, EBU_BUSCON2(t1)
	79	li t2, 0x684142BD
	80	b 3f
	81	sw t2, EBU_BUSCON1(t1) /* delay slot */
	82
	83	/* 133 or 150 MHz */
	84	2:
	85	li t2, 0x8841417E
	86	sw t2, EBU_BUSCON0(t1)
	87	sw t2, EBU_BUSCON2(t1)
	88	li t2, 0x684143FD
	89	sw t2, EBU_BUSCON1(t1)
	90	3:
43c50925	91	jr ra
7cb22f97 WD	92	nop
	93
	94	.end ebu_init
c021880a	95
c021880a	96
7cb22f97 WD	97	/*
	98	* void cgu_init(long)
	99	*
	100	* a0 has the clock value
	101	*/
	102	.globl cgu_init
	103	.ent cgu_init
	104	cgu_init:
f013dacf	105	__cgu_init:
7cb22f97 WD	106
	107	li t1, CGU_MODUL_BASE
	108
	109	li t3, 100000000
	110	beq a0, t3, 1f
	111	nop
	112	li t3, 133000000
	113	beq a0, t3, 2f
	114	nop
	115	li t3, 150000000
	116	beq a0, t3, 3f
	117	nop
	118	b 5f
	119	nop
	120
	121	/* 100 MHz clock */
	122	1:
	123	li t2, 0x80000014
	124	sw t2, CGU_DIVCR(t1)
	125	li t2, 0x80000000
	126	sw t2, CGU_MUXCR(t1)
	127	li t2, 0x800B0001
	128	b 5f
	129	sw t2, CGU_PLL1CR(t1) /* delay slot */
	130
	131	/* 133 MHz clock */
	132	2:
	133	li t2, 0x80000054
	134	sw t2, CGU_DIVCR(t1)
	135	li t2, 0x80000000
	136	sw t2, CGU_MUXCR(t1)
	137	li t2, 0x800B0001
	138	b 5f
	139	sw t2, CGU_PLL1CR(t1) /* delay slot */
	140
	141	/* 150 MHz clock */
	142	3:
	143	li t2, 0x80000017
	144	sw t2, CGU_DIVCR(t1)
	145	li t2, 0xC00B0001
	146	sw t2, CGU_PLL1CR(t1)
	147	li t3, 0x80000000
	148	4:
	149	lw t2, CGU_PLL1SR(t1)
	150	and t2, t2, t3
	151	beq t2, zero, 4b
	152	nop
	153	li t2, 0x80000001
	154	sw t2, CGU_MUXCR(t1)
	155	5:
43c50925	156	jr ra
7cb22f97 WD	157	nop
	158
	159	.end cgu_init
	160
	161
68766094 WD	162	/*
	163	* void sdram_init(long)
	164	*
	165	* a0 has the clock value
	166	*/
	167	.globl sdram_init
	168	.ent sdram_init
	169	sdram_init:
f013dacf	170	__sdram_init:
7cb22f97	171
68766094	172	li t1, MC_MODUL_BASE
7cb22f97	173
cf56e110	174	#if 0
68766094 WD	175	/* Disable memory controller before changing any of its registers */
68766094 WD	176	sw zero, MC_CTRLENA(t1)
cf56e110	177	#endif
68766094 WD	178
	179	li t2, 100000000
	180	beq a0, t2, 1f
7cb22f97	181	nop
68766094 WD	182	li t2, 133000000
	183	beq a0, t2, 2f
	184	nop
	185	li t2, 150000000
	186	beq a0, t2, 3f
	187	nop
	188	b 5f
7cb22f97	189	nop
c021880a	190
68766094 WD	191	/* 100 MHz clock */
	192	1:
	193	/* Set clock ratio (clkrat=1:1, rddel=3) */
	194	li t2, 0x00000003
	195	sw t2, MC_IOGP(t1)
c021880a	196
68766094 WD	197	/* Set sdram refresh rate (4K/64ms @ 100MHz) */
	198	li t2, 0x0000061A
	199	b 4f
	200	sw t2, MC_TREFRESH(t1)
	201
	202	/* 133 MHz clock */
	203	2:
	204	/* Set clock ratio (clkrat=1:1, rddel=3) */
	205	li t2, 0x00000003
	206	sw t2, MC_IOGP(t1)
	207
	208	/* Set sdram refresh rate (4K/64ms @ 133MHz) */
	209	li t2, 0x00000822
	210	b 4f
	211	sw t2, MC_TREFRESH(t1)
	212
	213	/* 150 MHz clock */
	214	3:
	215	/* Set clock ratio (clkrat=3:2, rddel=4) */
	216	li t2, 0x00000014
	217	sw t2, MC_IOGP(t1)
	218
	219	/* Set sdram refresh rate (4K/64ms @ 150MHz) */
	220	li t2, 0x00000927
	221	sw t2, MC_TREFRESH(t1)
c021880a	222
68766094 WD	223	4:
	224	/* Clear Error log registers */
	225	sw zero, MC_ERRCAUSE(t1)
	226	sw zero, MC_ERRADDR(t1)
c021880a WD	227
c021880a WD	228	/* Clear Power-down registers */
68766094	229	sw zero, MC_SELFRFSH(t1)
c021880a WD	230
c021880a WD	231	/* Set CAS Latency */
68766094 WD	232	li t2, 0x00000020 /* CL = 2 */
68766094 WD	233	sw t2, MC_MRSCODE(t1)
c021880a WD	234
c021880a WD	235	/* Set word width to 16 bit */
68766094 WD	236	li t2, 0x2
68766094 WD	237	sw t2, MC_CFGDW(t1)
c021880a WD	238
c021880a WD	239	/* Set CS0 to SDRAM parameters */
68766094 WD	240	li t2, 0x000014C9
68766094 WD	241	sw t2, MC_CFGPB0(t1)
c021880a WD	242
c021880a WD	243	/* Set SDRAM latency parameters */
68766094 WD	244	li t2, 0x00026325 /* BC PC100 */
68766094 WD	245	sw t2, MC_LATENCY(t1)
c021880a	246
68766094	247	5:
c021880a	248	/* Finally enable the controller */
68766094 WD	249	li t2, 0x00000001
68766094 WD	250	sw t2, MC_CTRLENA(t1)
c021880a	251
43c50925	252	jr ra
c021880a	253	nop
68766094 WD	254
	255	.end sdram_init
	256
	257
400558b5 WD	258	.globl lowlevel_init
	259	.ent lowlevel_init
	260	lowlevel_init:
68766094	261
26138623 SK	262	/* Disable Watchdog.
	263	*/
	264	la t9, disable_incaip_wdt
	265	jalr t9
	266	nop
	267
68766094 WD	268	/* EBU, CGU and SDRAM Initialization.
68766094 WD	269	*/
536884f9	270	li a0, CONFIG_CPU_CLOCK_RATE
68766094 WD	271	move t0, ra
	272
	273	/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
	274	* modify t0 and a0.
	275	*/
f013dacf	276	bal __cgu_init
68766094	277	nop
f013dacf	278	bal __ebu_init
68766094	279	nop
f013dacf	280	bal __sdram_init
68766094 WD	281	nop
	282	move ra, t0
	283
43c50925	284	jr ra
68766094 WD	285	nop
68766094 WD	286
400558b5	287	.end lowlevel_init