[people/ms/u-boot.git] / board / intercontrol / digsy_mtc / digsy_mtc.c

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * (C) Copyright 2005-2009
 * Modified for InterControl digsyMTC MPC5200 board by
 * Frank Bodammer, GCD Hard- & Software GmbH,
 *                 frank.bodammer@gcd-solutions.de
 *
 * (C) Copyright 2009
 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc5xxx.h>
#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/io.h>
#include "eeprom.h"
#if defined(CONFIG_DIGSY_REV5)
#include "is45s16800a2.h"
#include <mtd/cfi_flash.h>
#include <flash.h>
#else
#include "is42s16800a-7t.h"
#endif
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <mb862xx.h>

DECLARE_GLOBAL_DATA_PTR;

extern int usb_cpu_init(void);

#if defined(CONFIG_DIGSY_REV5)
/*
 * The M29W128GH needs a special reset command function,
 * details see the doc/README.cfi file
 */
void flash_cmd_reset(flash_info_t *info)
{
	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
}
#endif

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start(int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	long control = SDRAM_CONTROL | hi_addr_bit;

	/* unlock mode register */
	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);

	/* precharge all banks */
	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);

	/* auto refresh */
	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);

	/* set mode register */
	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);

	/* normal operation */
	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
}
#endif

/*
 * ATTENTION: Although partially referenced dram_init does NOT make real use
 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
 *            CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
 */

int dram_init(void)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
	uint svr, pvr;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */

	/* setup config registers */
	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20))
		dramsize = 0;

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
	} else {
		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);

	/* find RAM size using SDRAM CS1 only */
	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
			0x08000000);
		dramsize2 = test1;

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20))
		dramsize2 = 0;

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
			(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
	} else {
		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
	}

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
	if (dramsize >= 0x13)
		dramsize = (1 << (dramsize - 0x13)) << 20;
	else
		dramsize = 0;

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
	if (dramsize2 >= 0x13)
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	else
		dramsize2 = 0;

#endif /* CONFIG_SYS_RAMBOOT */

	/*
	 * On MPC5200B we need to set the special configuration delay in the
	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	 *
	 * "The SDelay should be written to a value of 0x00000004. It is
	 * required to account for changes caused by normal wafer processing
	 * parameters."
	 */
	svr = get_svr();
	pvr = get_pvr();
	if ((SVR_MJREV(svr) >= 2) &&
	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);

	gd->ram_size = dramsize + dramsize2;

	return 0;
}

int checkboard(void)
{
	char buf[64];
	int i = getenv_f("serial#", buf, sizeof(buf));

	puts ("Board: InterControl digsyMTC");
#if defined(CONFIG_DIGSY_REV5)
	puts (" rev5");
#endif
	if (i > 0) {
		puts(", ");
		puts(buf);
	}
	putc('\n');

	return 0;
}

#if defined(CONFIG_VIDEO)

#define GPIO_USB1_0		0x00010000	/* Power-On pin */
#define GPIO_USB1_9		0x08		/* PX_~EN pin */

#define GPIO_EE_DO		0x10		/* PSC6_0 (DO) pin */
#define GPIO_EE_CTS		0x20		/* PSC6_1 (CTS) pin */
#define GPIO_EE_DI		0x10000000	/* PSC6_2 (DI) pin */
#define GPIO_EE_CLK		0x20000000	/* PSC6_3 (CLK) pin */

#define GPT_GPIO_ON		0x00000034	/* GPT as simple GPIO, high */

static void exbo_hw_init(void)
{
	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
	struct mpc5xxx_wu_gpio *wu_gpio =
				(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;

	/* configure IrDA pins (PSC6 port) as gpios */
	gpio->port_config &= 0xFF8FFFFF;

	/* Init for USB1_0, EE_CLK and EE_DI - Low */
	setbits_be32(&gpio->simple_ddr,
			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
	clrbits_be32(&gpio->simple_ode,
			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
	clrbits_be32(&gpio->simple_dvo,
			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
	setbits_be32(&gpio->simple_gpioe,
			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);

	/* Init for EE_DO, EE_CTS - Input */
	clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
	setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);

	/* Init for PX_~EN (USB1_9) - High */
	clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
	setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
	clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
	setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
	setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);

	/* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
	out_be32(&gpt[0].emsr, GPT_GPIO_ON);
	/* Init for S Switch (GPIO4) - Timer_1 GPIO High */
	out_be32(&gpt[1].emsr, GPT_GPIO_ON);

	/* Power-On camera supply */
	setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
}
#else
static inline void exbo_hw_init(void) {}
#endif /* CONFIG_VIDEO */

int board_early_init_r(void)
{
	/*
	 * Now, when we are in RAM, enable flash write access for detection
	 * process.  Note that CS_BOOT cannot be cleared when executing in
	 * flash.
	 */
	/* disable CS_BOOT */
	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
	/* enable CS1 */
	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
	/* enable CS0 */
	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));

#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
	/* Low level USB init, required for proper kernel operation */
	usb_cpu_init();
#endif

	return (0);
}

void board_get_enetaddr (uchar * enet)
{
	ushort read = 0;
	ushort addr_of_eth_addr = 0;
	ushort len_sys = 0;
	ushort len_sys_cfg = 0;

	/* check identification word */
	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
	if (read != EEPROM_IDENT)
		return;

	/* calculate offset of config area */
	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
		(uchar *)&len_sys_cfg, 2);
	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
	if (addr_of_eth_addr >= EEPROM_LEN)
		return;

	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
}

int misc_init_r(void)
{
	pci_dev_t devbusfn;
	uchar enetaddr[6];

	/* check if graphic extension board is present */
	devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
				   PCI_DEVICE_ID_CORAL_PA, 0);
	if (devbusfn != -1)
		exbo_hw_init();

	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
		board_get_enetaddr(enetaddr);
		eth_setenv_enetaddr("ethaddr", enetaddr);
	}

	return 0;
}

#ifdef CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#ifdef CONFIG_IDE

#ifdef CONFIG_IDE_RESET

void init_ide_reset(void)
{
	debug ("init_ide_reset\n");

	/* set gpio output value to 1 */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	/* open drain output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	/* direction output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	/* enable gpio */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));

}

void ide_set_reset(int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

	/* set gpio output value to 0 */
	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	/* open drain output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	/* direction output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	/* enable gpio */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));

	udelay(10000);

	/* set gpio output value to 1 */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	/* open drain output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	/* direction output */
	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	/* enable gpio */
	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
}
#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_IDE */

#ifdef CONFIG_OF_BOARD_SETUP
static void ft_delete_node(void *fdt, const char *compat)
{
	int off = -1;
	int ret;

	off = fdt_node_offset_by_compatible(fdt, -1, compat);
	if (off < 0) {
		printf("Could not find %s node.\n", compat);
		return;
	}

	ret = fdt_del_node(fdt, off);
	if (ret < 0)
		printf("Could not delete %s node.\n", compat);
}
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
static void ft_adapt_flash_base(void *blob)
{
	flash_info_t	*dev = &flash_info[0];
	int off;
	struct fdt_property *prop;
	int len;
	u32 *reg, *reg2;

	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
	if (off < 0) {
		printf("Could not find fsl,mpc5200b-lpb node.\n");
		return;
	}

	/* found compatible property */
	prop = fdt_get_property_w(blob, off, "ranges", &len);
	if (prop) {
		reg = reg2 = (u32 *)&prop->data[0];

		reg[2] = dev->start[0];
		reg[3] = dev->size;
		fdt_setprop(blob, off, "ranges", reg2, len);
	} else
		printf("Could not find ranges\n");
}

extern ulong flash_get_size (phys_addr_t base, int banknum);

/* Update the Flash Baseaddr settings */
int update_flash_size (int flash_size)
{
	volatile struct mpc5xxx_mmap_ctl *mm =
		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	flash_info_t	*dev;
	int	i;
	int size = 0;
	unsigned long base = 0x0;
	u32 *cs_reg = (u32 *)&mm->cs0_start;

	for (i = 0; i < 2; i++) {
		dev = &flash_info[i];

		if (dev->size) {
			/* calculate new base addr for this chipselect */
			base -= dev->size;
			out_be32(cs_reg, START_REG(base));
			cs_reg++;
			out_be32(cs_reg, STOP_REG(base, dev->size));
			cs_reg++;
			/* recalculate the sectoraddr in the cfi driver */
			size += flash_get_size(base, i);
		}
	}
	flash_protect_default();
	gd->bd->bi_flashstart = base;
	return 0;
}
#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */

int ft_board_setup(void *blob, bd_t *bd)
{
	int phy_addr = CONFIG_PHY_ADDR;
	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";

	ft_cpu_setup(blob, bd);
	/*
	 * There are 2 RTC nodes in the DTS, so remove
	 * the unneeded node here.
	 */
#if defined(CONFIG_DIGSY_REV5)
	ft_delete_node(blob, "dallas,ds1339");
#else
	ft_delete_node(blob, "mc,rv3029c2");
#endif
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
	/* Update reg property in all nor flash nodes too */
	fdt_fixup_nor_flash_size(blob);
#endif
	ft_adapt_flash_base(blob);
#endif
	/* fix up the phy address */
	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);

	return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
Commit	Line	Data
5c4fa9b4 GB	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* (C) Copyright 2005-2009
	9	* Modified for InterControl digsyMTC MPC5200 board by
	10	* Frank Bodammer, GCD Hard- & Software GmbH,
	11	* frank.bodammer@gcd-solutions.de
	12	*
	13	* (C) Copyright 2009
	14	* Grzegorz Bernacki, Semihalf, gjb@semihalf.com
	15	*
1a459660	16	* SPDX-License-Identifier: GPL-2.0+
5c4fa9b4 GB	17	*/
	18
	19	#include <common.h>
	20	#include <mpc5xxx.h>
	21	#include <net.h>
	22	#include <pci.h>
	23	#include <asm/processor.h>
	24	#include <asm/io.h>
	25	#include "eeprom.h"
466f0137 HS	26	#if defined(CONFIG_DIGSY_REV5)
	27	#include "is45s16800a2.h"
	28	#include <mtd/cfi_flash.h>
f3143134	29	#include <flash.h>
466f0137	30	#else
5c4fa9b4	31	#include "is42s16800a-7t.h"
466f0137 HS	32	#endif
466f0137 HS	33	#include <libfdt.h>
927d2cea	34	#include <fdt_support.h>
a59996e3	35	#include <i2c.h>
02ab0970	36	#include <mb862xx.h>
5c4fa9b4 GB	37
	38	DECLARE_GLOBAL_DATA_PTR;
	39
	40	extern int usb_cpu_init(void);
	41
466f0137 HS	42	#if defined(CONFIG_DIGSY_REV5)
466f0137 HS	43	/*
b3525488	44	* The M29W128GH needs a special reset command function,
466f0137 HS	45	* details see the doc/README.cfi file
	46	*/
	47	void flash_cmd_reset(flash_info_t *info)
	48	{
	49	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
	50	}
	51	#endif
	52
5c4fa9b4 GB	53	#ifndef CONFIG_SYS_RAMBOOT
	54	static void sdram_start(int hi_addr)
	55	{
	56	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	57	long control = SDRAM_CONTROL \| hi_addr_bit;
	58
	59	/* unlock mode register */
	60	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000000);
	61
	62	/* precharge all banks */
	63	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000002);
	64
	65	/* auto refresh */
	66	out_be32((void *)MPC5XXX_SDRAM_CTRL, control \| 0x80000004);
	67
	68	/* set mode register */
	69	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
	70
	71	/* normal operation */
	72	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
	73	}
	74	#endif
	75
	76	/*
f1683aa7	77	* ATTENTION: Although partially referenced dram_init does NOT make real use
5c4fa9b4	78	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
b3525488	79	* CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
5c4fa9b4 GB	80	*/
5c4fa9b4 GB	81
f1683aa7	82	int dram_init(void)
5c4fa9b4 GB	83	{
	84	ulong dramsize = 0;
	85	ulong dramsize2 = 0;
	86	uint svr, pvr;
	87	#ifndef CONFIG_SYS_RAMBOOT
	88	ulong test1, test2;
	89
	90	/* setup SDRAM chip selects */
	91	out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0x0000001C); / 512MB at 0x0 */
	92	out_be32((void )MPC5XXX_SDRAM_CS1CFG, 0x80000000); / disabled */
	93
	94	/* setup config registers */
	95	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
	96	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
	97
	98	/* find RAM size using SDRAM CS0 only */
	99	sdram_start(0);
	100	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
	101	sdram_start(1);
	102	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
	103	if (test1 > test2) {
	104	sdram_start(0);
	105	dramsize = test1;
	106	} else {
	107	dramsize = test2;
	108	}
	109
	110	/* memory smaller than 1MB is impossible */
	111	if (dramsize < (1 << 20))
	112	dramsize = 0;
	113
	114	/* set SDRAM CS0 size according to the amount of RAM found */
	115	if (dramsize > 0) {
	116	out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
	117	(0x13 + __builtin_ffs(dramsize >> 20) - 1));
	118	} else {
	119	out_be32((void )MPC5XXX_SDRAM_CS0CFG, 0); / disabled */
	120	}
	121
	122	/* let SDRAM CS1 start right after CS0 */
	123	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
	124
	125	/* find RAM size using SDRAM CS1 only */
	126	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
	127	0x08000000);
	128	dramsize2 = test1;
	129
	130	/* memory smaller than 1MB is impossible */
	131	if (dramsize2 < (1 << 20))
	132	dramsize2 = 0;
	133
	134	/* set SDRAM CS1 size according to the amount of RAM found */
	135	if (dramsize2 > 0) {
	136	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize \|
	137	(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
	138	} else {
	139	out_be32((void )MPC5XXX_SDRAM_CS1CFG, dramsize); / disabled */
	140	}
	141
	142	#else /* CONFIG_SYS_RAMBOOT */
	143
	144	/* retrieve size of memory connected to SDRAM CS0 */
	145	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
	146	if (dramsize >= 0x13)
147	dramsize = (1 << (dramsize - 0x13)) << 20;
148	else
149	dramsize = 0;
150
151	/* retrieve size of memory connected to SDRAM CS1 */
152	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
153	if (dramsize2 >= 0x13)
154	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
155	else
156	dramsize2 = 0;
157
158	#endif /* CONFIG_SYS_RAMBOOT */
159
160	/*
161	* On MPC5200B we need to set the special configuration delay in the
162	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
163	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
164	*
165	* "The SDelay should be written to a value of 0x00000004. It is
166	* required to account for changes caused by normal wafer processing
167	* parameters."
168	*/
169	svr = get_svr();
170	pvr = get_pvr();
171	if ((SVR_MJREV(svr) >= 2) &&
172	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
173	out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
174
088454cd SG	175	gd->ram_size = dramsize + dramsize2;
	176
	177	return 0;
5c4fa9b4 GB	178	}
	179
	180	int checkboard(void)
	181	{
f0c0b3a9 WD	182	char buf[64];
f0c0b3a9 WD	183	int i = getenv_f("serial#", buf, sizeof(buf));
5c4fa9b4 GB	184
5c4fa9b4 GB	185	puts ("Board: InterControl digsyMTC");
466f0137 HS	186	#if defined(CONFIG_DIGSY_REV5)
	187	puts (" rev5");
	188	#endif
f0c0b3a9	189	if (i > 0) {
5c4fa9b4	190	puts(", ");
f0c0b3a9	191	puts(buf);
5c4fa9b4 GB	192	}
	193	putc('\n');
	194
	195	return 0;
	196	}
	197
a59996e3 AG	198	#if defined(CONFIG_VIDEO)
	199
	200	#define GPIO_USB1_0 0x00010000 /* Power-On pin */
	201	#define GPIO_USB1_9 0x08 /* PX_~EN pin */
	202
	203	#define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */
	204	#define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */
	205	#define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */
	206	#define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */
	207
	208	#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
	209
a59996e3 AG	210	static void exbo_hw_init(void)
	211	{
	212	struct mpc5xxx_gpt gpt = (struct mpc5xxx_gpt )MPC5XXX_GPT;
	213	struct mpc5xxx_gpio gpio = (struct mpc5xxx_gpio )MPC5XXX_GPIO;
	214	struct mpc5xxx_wu_gpio *wu_gpio =
	215	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
a59996e3 AG	216
	217	/* configure IrDA pins (PSC6 port) as gpios */
	218	gpio->port_config &= 0xFF8FFFFF;
	219
	220	/* Init for USB1_0, EE_CLK and EE_DI - Low */
	221	setbits_be32(&gpio->simple_ddr,
	222	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);
	223	clrbits_be32(&gpio->simple_ode,
	224	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);
	225	clrbits_be32(&gpio->simple_dvo,
	226	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);
	227	setbits_be32(&gpio->simple_gpioe,
	228	GPIO_USB1_0 \| GPIO_EE_CLK \| GPIO_EE_DI);
	229
	230	/* Init for EE_DO, EE_CTS - Input */
	231	clrbits_8(&wu_gpio->ddr, GPIO_EE_DO \| GPIO_EE_CTS);
	232	setbits_8(&wu_gpio->enable, GPIO_EE_DO \| GPIO_EE_CTS);
	233
	234	/* Init for PX_~EN (USB1_9) - High */
	235	clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
	236	setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
	237	clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
	238	setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
	239	setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
	240
	241	/* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
	242	out_be32(&gpt[0].emsr, GPT_GPIO_ON);
	243	/* Init for S Switch (GPIO4) - Timer_1 GPIO High */
	244	out_be32(&gpt[1].emsr, GPT_GPIO_ON);
	245
	246	/* Power-On camera supply */
	247	setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
	248	}
	249	#else
	250	static inline void exbo_hw_init(void) {}
	251	#endif /* CONFIG_VIDEO */
	252
5c4fa9b4 GB	253	int board_early_init_r(void)
	254	{
	255	/*
	256	* Now, when we are in RAM, enable flash write access for detection
	257	* process. Note that CS_BOOT cannot be cleared when executing in
	258	* flash.
	259	*/
	260	/* disable CS_BOOT */
	261	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
	262	/* enable CS1 */
	263	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
	264	/* enable CS0 */
	265	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
	266
	267	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
	268	/* Low level USB init, required for proper kernel operation */
	269	usb_cpu_init();
	270	#endif
f1f66edf	271
5c4fa9b4 GB	272	return (0);
	273	}
	274
	275	void board_get_enetaddr (uchar * enet)
	276	{
	277	ushort read = 0;
	278	ushort addr_of_eth_addr = 0;
	279	ushort len_sys = 0;
	280	ushort len_sys_cfg = 0;
	281
	282	/* check identification word */
	283	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
	284	if (read != EEPROM_IDENT)
	285	return;
	286
	287	/* calculate offset of config area */
	288	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
	289	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
	290	(uchar *)&len_sys_cfg, 2);
	291	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
	292	if (addr_of_eth_addr >= EEPROM_LEN)
	293	return;
	294
	295	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
	296	}
	297
	298	int misc_init_r(void)
	299	{
02ab0970	300	pci_dev_t devbusfn;
5c4fa9b4 GB	301	uchar enetaddr[6];
5c4fa9b4 GB	302
02ab0970 AG	303	/* check if graphic extension board is present */
	304	devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
	305	PCI_DEVICE_ID_CORAL_PA, 0);
	306	if (devbusfn != -1)
	307	exbo_hw_init();
	308
5c4fa9b4 GB	309	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
	310	board_get_enetaddr(enetaddr);
	311	eth_setenv_enetaddr("ethaddr", enetaddr);
	312	}
	313
	314	return 0;
	315	}
	316
	317	#ifdef CONFIG_PCI
	318	static struct pci_controller hose;
	319
	320	extern void pci_mpc5xxx_init(struct pci_controller *);
	321
	322	void pci_init_board(void)
	323	{
	324	pci_mpc5xxx_init(&hose);
	325	}
	326	#endif
	327
fc843a02	328	#ifdef CONFIG_IDE
5c4fa9b4 GB	329
	330	#ifdef CONFIG_IDE_RESET
	331
	332	void init_ide_reset(void)
	333	{
	334	debug ("init_ide_reset\n");
	335
	336	/* set gpio output value to 1 */
	337	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	338	/* open drain output */
	339	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	340	/* direction output */
	341	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	342	/* enable gpio */
	343	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
	344
	345	}
	346
	347	void ide_set_reset(int idereset)
	348	{
	349	debug ("ide_reset(%d)\n", idereset);
	350
	351	/* set gpio output value to 0 */
	352	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	353	/* open drain output */
	354	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	355	/* direction output */
	356	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	357	/* enable gpio */
	358	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
	359
	360	udelay(10000);
	361
	362	/* set gpio output value to 1 */
	363	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
	364	/* open drain output */
	365	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
	366	/* direction output */
	367	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
	368	/* enable gpio */
	369	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
	370	}
	371	#endif /* CONFIG_IDE_RESET */
fc843a02	372	#endif /* CONFIG_IDE */
5c4fa9b4	373
7ffe3cd6	374	#ifdef CONFIG_OF_BOARD_SETUP
466f0137 HS	375	static void ft_delete_node(void fdt, const char compat)
	376	{
	377	int off = -1;
	378	int ret;
	379
	380	off = fdt_node_offset_by_compatible(fdt, -1, compat);
	381	if (off < 0) {
	382	printf("Could not find %s node.\n", compat);
	383	return;
	384	}
	385
	386	ret = fdt_del_node(fdt, off);
	387	if (ret < 0)
	388	printf("Could not delete %s node.\n", compat);
	389	}
	390	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
	391	static void ft_adapt_flash_base(void *blob)
	392	{
	393	flash_info_t *dev = &flash_info[0];
	394	int off;
	395	struct fdt_property *prop;
	396	int len;
	397	u32 reg, reg2;
	398
	399	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
	400	if (off < 0) {
	401	printf("Could not find fsl,mpc5200b-lpb node.\n");
	402	return;
	403	}
	404
	405	/* found compatible property */
	406	prop = fdt_get_property_w(blob, off, "ranges", &len);
	407	if (prop) {
	408	reg = reg2 = (u32 *)&prop->data[0];
	409
	410	reg[2] = dev->start[0];
	411	reg[3] = dev->size;
	412	fdt_setprop(blob, off, "ranges", reg2, len);
	413	} else
	414	printf("Could not find ranges\n");
	415	}
	416
	417	extern ulong flash_get_size (phys_addr_t base, int banknum);
	418
	419	/* Update the Flash Baseaddr settings */
	420	int update_flash_size (int flash_size)
	421	{
	422	volatile struct mpc5xxx_mmap_ctl *mm =
	423	(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	424	flash_info_t *dev;
	425	int i;
	426	int size = 0;
	427	unsigned long base = 0x0;
	428	u32 cs_reg = (u32 )&mm->cs0_start;
	429
	430	for (i = 0; i < 2; i++) {
	431	dev = &flash_info[i];
	432
	433	if (dev->size) {
	434	/* calculate new base addr for this chipselect */
	435	base -= dev->size;
	436	out_be32(cs_reg, START_REG(base));
	437	cs_reg++;
	438	out_be32(cs_reg, STOP_REG(base, dev->size));
439	cs_reg++;
440	/* recalculate the sectoraddr in the cfi driver */
441	size += flash_get_size(base, i);
442	}
443	}
f3143134	444	flash_protect_default();
466f0137 HS	445	gd->bd->bi_flashstart = base;
	446	return 0;
	447	}
	448	#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
	449
e895a4b0	450	int ft_board_setup(void blob, bd_t bd)
5c4fa9b4	451	{
1b41493d HS	452	int phy_addr = CONFIG_PHY_ADDR;
	453	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
	454
5c4fa9b4	455	ft_cpu_setup(blob, bd);
466f0137 HS	456	/*
	457	* There are 2 RTC nodes in the DTS, so remove
	458	* the unneeded node here.
	459	*/
	460	#if defined(CONFIG_DIGSY_REV5)
	461	ft_delete_node(blob, "dallas,ds1339");
	462	#else
	463	ft_delete_node(blob, "mc,rv3029c2");
	464	#endif
	465	#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
927d2cea HS	466	#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
	467	/* Update reg property in all nor flash nodes too */
	468	fdt_fixup_nor_flash_size(blob);
	469	#endif
466f0137 HS	470	ft_adapt_flash_base(blob);
466f0137 HS	471	#endif
1b41493d HS	472	/* fix up the phy address */
1b41493d HS	473	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
e895a4b0 SG	474
e895a4b0 SG	475	return 0;
5c4fa9b4	476	}
7ffe3cd6	477	#endif /* CONFIG_OF_BOARD_SETUP */