[people/ms/u-boot.git] / board / ipek01 / ipek01.c

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * (C) Copyright 2006
 * MicroSys GmbH
 *
 * (C) Copyright 2009
 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <netdev.h>
#include <miiphy.h>
#include <libfdt.h>
#include <mb862xx.h>
#include <video_fb.h>
#include <asm/processor.h>
#include <asm/io.h>

#ifdef CONFIG_OF_LIBFDT
#include <fdt_support.h>
#endif /* CONFIG_OF_LIBFDT */

/* mt46v16m16-75 */
#ifdef CONFIG_MPC5200_DDR
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE	0x018D0000
#define SDRAM_EMODE	0x40090000
#define SDRAM_CONTROL	0x714f0f00
#define SDRAM_CONFIG1	0x73722930
#define SDRAM_CONFIG2	0x47770000
#define SDRAM_TAPDELAY	0x10000000
#else
#error SDRAM is not supported on this board
#endif

DECLARE_GLOBAL_DATA_PTR;

static void sdram_start (int hi_addr)
{
	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);

	/* precharge all banks */
	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);

	/* set mode register: extended mode */
	out_be32 (&sdram->mode, SDRAM_EMODE);

	/* set mode register: reset DLL */
	out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);

	/* precharge all banks */
	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);

	/* auto refresh */
	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);

	/* set mode register */
	out_be32 (&sdram->mode, SDRAM_MODE);

	/* normal operation */
	out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
}

/*
 * ATTENTION: Although partially referenced initdram does NOT make real
 *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if
 *	      CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
 */

int initdram(void)
{
	struct mpc5xxx_mmap_ctl *mmap_ctl =
		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
	struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
	ulong dramsize = 0;
	ulong dramsize2 = 0;
	ulong test1, test2;

	/* setup SDRAM chip selects */
	out_be32 (&mmap_ctl->sdram0, 0x0000001e);	/* 2G at 0x0 */
	out_be32 (&mmap_ctl->sdram1, 0x00000000);	/* disabled */

	/* setup config registers */
	out_be32 (&sdram->config1, SDRAM_CONFIG1);
	out_be32 (&sdram->config2, SDRAM_CONFIG2);

	/* set tap delay */
	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);

	/* find RAM size using SDRAM CS0 only */
	sdram_start (0);
	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start (1);
	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start (0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20))
		dramsize = 0;

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0)
		out_be32 (&mmap_ctl->sdram0,
			  0x13 + __builtin_ffs (dramsize >> 20) - 1);
	else
		out_be32 (&mmap_ctl->sdram1, 0);	/* disabled */

	/*
	 * On MPC5200B we need to set the special configuration delay in the
	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	 *
	 * "The SDelay should be written to a value of 0x00000004. It is
	 * required to account for changes caused by normal wafer processing
	 * parameters."
	 */
	out_be32 (&sdram->sdelay, 0x04);

	gd->ram_size = dramsize + dramsize2;

	return 0;
}

int checkboard (void)
{
	puts ("Board: IPEK01 \n");
	return 0;
}

void flash_preinit (void)
{
	struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;

	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
	clrbits_be32 (&lpb->cs0_cfg, 0x1);	/* clear RO */
}

void flash_afterinit (ulong start, ulong size)
{
	struct mpc5xxx_mmap_ctl *mmap_ctl =
		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;

#if defined(CONFIG_BOOT_ROM)
	/* adjust mapping */
	out_be32 (&mmap_ctl->cs1_start, START_REG (start));
	out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
#else
	/* adjust mapping */
	out_be32 (&mmap_ctl->boot_start, START_REG (start));
	out_be32 (&mmap_ctl->cs0_start, START_REG (start));
	out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
	out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
#endif
}

extern flash_info_t flash_info[];	/* info for FLASH chips */

int misc_init_r (void)
{
	/* adjust flash start */
	gd->bd->bi_flashstart = flash_info[0].start[0];
	return (0);
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init (struct pci_controller *);

void pci_init_board (void)
{
	pci_mpc5xxx_init (&hose);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup (blob, bd);
	fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);

	return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */

int board_eth_init(bd_t *bis)
{
	cpu_eth_init(bis); /* Built in FEC comes first */
	return pci_eth_init(bis);
}

#ifdef CONFIG_VIDEO
extern GraphicDevice mb862xx;

static const gdc_regs init_regs[] = {
	{0x0100, 0x00000900},
	{0x0020, 0x80190257},
	{0x0024, 0x00000000},
	{0x0028, 0x00000000},
	{0x002c, 0x00000000},
	{0x0110, 0x00000000},
	{0x0114, 0x00000000},
	{0x0118, 0x02570320},
	{0x0004, 0x041f0000},
	{0x0008, 0x031f031f},
	{0x000c, 0x067f0347},
	{0x0010, 0x02780000},
	{0x0014, 0x0257025c},
	{0x0018, 0x00000000},
	{0x001c, 0x02570320},
	{0x0100, 0x80010900},
	{0x0, 0x0}
};

const gdc_regs *board_get_regs (void)
{
	return init_regs;
}

/* Returns Lime base address */
unsigned int board_video_init (void)
{
	if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
		return 0;

	mb862xx.winSizeX = 800;
	mb862xx.winSizeY = 600;
	mb862xx.gdfIndex = GDF_15BIT_555RGB;
	mb862xx.gdfBytesPP = 2;

	return CONFIG_SYS_LIME_BASE;
}

#if defined(CONFIG_CONSOLE_EXTRA_INFO)
/*
 * Return text to be printed besides the logo.
 */
void video_get_info_str (int line_number, char *info)
{
	if (line_number == 1)
		strcpy (info, " Board: IPEK01");
	else
		info[0] = '\0';
}
#endif
#endif /* CONFIG_VIDEO */
Commit	Line	Data
cd12f615 WG	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* (C) Copyright 2006
	9	* MicroSys GmbH
	10	*
	11	* (C) Copyright 2009
	12	* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
	13	*
1a459660	14	* SPDX-License-Identifier: GPL-2.0+
cd12f615 WG	15	*/
	16
	17	#include <common.h>
	18	#include <mpc5xxx.h>
	19	#include <pci.h>
	20	#include <netdev.h>
	21	#include <miiphy.h>
	22	#include <libfdt.h>
	23	#include <mb862xx.h>
	24	#include <video_fb.h>
	25	#include <asm/processor.h>
	26	#include <asm/io.h>
	27
	28	#ifdef CONFIG_OF_LIBFDT
	29	#include <fdt_support.h>
	30	#endif /* CONFIG_OF_LIBFDT */
	31
	32	/* mt46v16m16-75 */
	33	#ifdef CONFIG_MPC5200_DDR
	34	/* Settings for XLB = 132 MHz */
	35	#define SDRAM_MODE 0x018D0000
	36	#define SDRAM_EMODE 0x40090000
	37	#define SDRAM_CONTROL 0x714f0f00
	38	#define SDRAM_CONFIG1 0x73722930
	39	#define SDRAM_CONFIG2 0x47770000
	40	#define SDRAM_TAPDELAY 0x10000000
	41	#else
	42	#error SDRAM is not supported on this board
	43	#endif
	44
	45	DECLARE_GLOBAL_DATA_PTR;
	46
	47	static void sdram_start (int hi_addr)
	48	{
	49	struct mpc5xxx_sdram sdram = (struct mpc5xxx_sdram )MPC5XXX_SDRAM;
	50	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	51
	52	/* unlock mode register */
	53	out_be32 (&sdram->ctrl, SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit);
	54
	55	/* precharge all banks */
	56	out_be32 (&sdram->ctrl, SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit);
	57
	58	/* set mode register: extended mode */
	59	out_be32 (&sdram->mode, SDRAM_EMODE);
	60
	61	/* set mode register: reset DLL */
	62	out_be32 (&sdram->mode, SDRAM_MODE \| 0x04000000);
	63
	64	/* precharge all banks */
	65	out_be32 (&sdram->ctrl, SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit);
	66
	67	/* auto refresh */
	68	out_be32 (&sdram->ctrl, SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit);
	69
	70	/* set mode register */
	71	out_be32 (&sdram->mode, SDRAM_MODE);
	72
	73	/* normal operation */
	74	out_be32 (&sdram->ctrl, SDRAM_CONTROL \| hi_addr_bit);
	75	}
	76
	77	/*
	78	* ATTENTION: Although partially referenced initdram does NOT make real
93910edb WD	79	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if
93910edb WD	80	* CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
cd12f615 WG	81	*/
cd12f615 WG	82
088454cd	83	int initdram(void)
cd12f615 WG	84	{
	85	struct mpc5xxx_mmap_ctl *mmap_ctl =
	86	(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
	87	struct mpc5xxx_sdram sdram = (struct mpc5xxx_sdram )MPC5XXX_SDRAM;
	88	struct mpc5xxx_cdm cdm = (struct mpc5xxx_cdm )MPC5XXX_CDM;
	89	ulong dramsize = 0;
	90	ulong dramsize2 = 0;
	91	ulong test1, test2;
	92
	93	/* setup SDRAM chip selects */
	94	out_be32 (&mmap_ctl->sdram0, 0x0000001e); /* 2G at 0x0 */
	95	out_be32 (&mmap_ctl->sdram1, 0x00000000); /* disabled */
	96
	97	/* setup config registers */
	98	out_be32 (&sdram->config1, SDRAM_CONFIG1);
	99	out_be32 (&sdram->config2, SDRAM_CONFIG2);
	100
	101	/* set tap delay */
	102	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
	103
	104	/* find RAM size using SDRAM CS0 only */
	105	sdram_start (0);
	106	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	107	sdram_start (1);
	108	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	109	if (test1 > test2) {
	110	sdram_start (0);
	111	dramsize = test1;
	112	} else {
	113	dramsize = test2;
	114	}
	115
	116	/* memory smaller than 1MB is impossible */
	117	if (dramsize < (1 << 20))
	118	dramsize = 0;
	119
	120	/* set SDRAM CS0 size according to the amount of RAM found */
	121	if (dramsize > 0)
	122	out_be32 (&mmap_ctl->sdram0,
	123	0x13 + __builtin_ffs (dramsize >> 20) - 1);
	124	else
	125	out_be32 (&mmap_ctl->sdram1, 0); /* disabled */
	126
	127	/*
	128	* On MPC5200B we need to set the special configuration delay in the
	129	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	130	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	131	*
	132	* "The SDelay should be written to a value of 0x00000004. It is
	133	* required to account for changes caused by normal wafer processing
	134	* parameters."
	135	*/
	136	out_be32 (&sdram->sdelay, 0x04);
	137
088454cd SG	138	gd->ram_size = dramsize + dramsize2;
	139
	140	return 0;
cd12f615 WG	141	}
	142
	143	int checkboard (void)
	144	{
	145	puts ("Board: IPEK01 \n");
	146	return 0;
	147	}
	148
	149	void flash_preinit (void)
	150	{
	151	struct mpc5xxx_lpb lpb = (struct mpc5xxx_lpb )MPC5XXX_LPB;
	152
	153	/*
	154	* Now, when we are in RAM, enable flash write
	155	* access for detection process.
	156	* Note that CS_BOOT cannot be cleared when
	157	* executing in flash.
	158	*/
	159	clrbits_be32 (&lpb->cs0_cfg, 0x1); /* clear RO */
	160	}
	161
	162	void flash_afterinit (ulong start, ulong size)
	163	{
	164	struct mpc5xxx_mmap_ctl *mmap_ctl =
	165	(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
	166
	167	#if defined(CONFIG_BOOT_ROM)
	168	/* adjust mapping */
	169	out_be32 (&mmap_ctl->cs1_start, START_REG (start));
	170	out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
	171	#else
	172	/* adjust mapping */
	173	out_be32 (&mmap_ctl->boot_start, START_REG (start));
	174	out_be32 (&mmap_ctl->cs0_start, START_REG (start));
	175	out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
	176	out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
	177	#endif
	178	}
	179
	180	extern flash_info_t flash_info[]; /* info for FLASH chips */
	181
	182	int misc_init_r (void)
	183	{
	184	/* adjust flash start */
	185	gd->bd->bi_flashstart = flash_info[0].start[0];
	186	return (0);
	187	}
	188
	189	#ifdef CONFIG_PCI
	190	static struct pci_controller hose;
	191
	192	extern void pci_mpc5xxx_init (struct pci_controller *);
	193
	194	void pci_init_board (void)
	195	{
	196	pci_mpc5xxx_init (&hose);
	197	}
	198	#endif
	199
7ffe3cd6	200	#ifdef CONFIG_OF_BOARD_SETUP
e895a4b0	201	int ft_board_setup(void blob, bd_t bd)
cd12f615 WG	202	{
	203	ft_cpu_setup (blob, bd);
	204	fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
e895a4b0 SG	205
e895a4b0 SG	206	return 0;
cd12f615	207	}
7ffe3cd6	208	#endif /* CONFIG_OF_BOARD_SETUP */
cd12f615 WG	209
	210	int board_eth_init(bd_t *bis)
	211	{
93910edb WD	212	cpu_eth_init(bis); /* Built in FEC comes first */
93910edb WD	213	return pci_eth_init(bis);
cd12f615 WG	214	}
	215
	216	#ifdef CONFIG_VIDEO
	217	extern GraphicDevice mb862xx;
	218
	219	static const gdc_regs init_regs[] = {
	220	{0x0100, 0x00000900},
	221	{0x0020, 0x80190257},
	222	{0x0024, 0x00000000},
	223	{0x0028, 0x00000000},
	224	{0x002c, 0x00000000},
	225	{0x0110, 0x00000000},
	226	{0x0114, 0x00000000},
	227	{0x0118, 0x02570320},
	228	{0x0004, 0x041f0000},
	229	{0x0008, 0x031f031f},
	230	{0x000c, 0x067f0347},
	231	{0x0010, 0x02780000},
	232	{0x0014, 0x0257025c},
	233	{0x0018, 0x00000000},
	234	{0x001c, 0x02570320},
	235	{0x0100, 0x80010900},
	236	{0x0, 0x0}
	237	};
	238
	239	const gdc_regs *board_get_regs (void)
	240	{
	241	return init_regs;
	242	}
	243
	244	/* Returns Lime base address */
	245	unsigned int board_video_init (void)
	246	{
	247	if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
	248	return 0;
	249
	250	mb862xx.winSizeX = 800;
	251	mb862xx.winSizeY = 600;
	252	mb862xx.gdfIndex = GDF_15BIT_555RGB;
	253	mb862xx.gdfBytesPP = 2;
	254
	255	return CONFIG_SYS_LIME_BASE;
	256	}
	257
	258	#if defined(CONFIG_CONSOLE_EXTRA_INFO)
	259	/*
	260	* Return text to be printed besides the logo.
	261	*/
	262	void video_get_info_str (int line_number, char *info)
	263	{
	264	if (line_number == 1)
	265	strcpy (info, " Board: IPEK01");
	266	else
	267	info[0] = '\0';
	268	}
	269	#endif
	270	#endif /* CONFIG_VIDEO */