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[people/ms/u-boot.git] / board / ispan / ispan.c
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c3c7f861
WD		 1/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Interphase iSPAN Communications Controllers
6 * (453x and others). Tested on 4532.
7 *
8 * Derived from iSPAN 4539 port (iphase4539) by
9 * Wolfgang Grandegger <wg@denx.de>
10 *
1a459660 11 * SPDX-License-Identifier: GPL-2.0+
c3c7f861
WD		 12 */
13
14#include <common.h>
15#include <ioports.h>
16#include <mpc8260.h>
17#include <asm/io.h>
18
19/*
20 * I/O Ports configuration table
21 *
22 * If conf is 1, then that port pin will be configured at boot time
23 * according to the five values podr/pdir/ppar/psor/pdat for that entry
24 */
25
6d0f6bcf
JCPV		 26#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
27#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
28#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
c3c7f861
WD		 29
30const iop_conf_t iop_conf_tab[4][32] = {
31 /* Port A */
32 { /* conf ppar psor pdir podr pdat */
6d0f6bcf
JCPV		 33 /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
34 /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
35 /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
36 /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
37 /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
38 /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
c3c7f861
WD		 39 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
40 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
41 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
42 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
6d0f6bcf
JCPV		 43 /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
44 /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
45 /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
46 /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
47 /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
48 /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
49 /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
50 /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
c3c7f861
WD		 51 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
52 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
53 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
54 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
55 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */
56 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */
57 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
58 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
59 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
60 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
61 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
62 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
63 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
64 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
65 },
66
67 /* Port B */
68 { /* conf ppar psor pdir podr pdat */
6d0f6bcf
JCPV		 69 /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
70 /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
71 /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
72 /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
73 /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
74 /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
75 /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
76 /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
77 /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
78 /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
79 /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
80 /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
81 /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
82 /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
83 /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
84 /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
85 /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
86 /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
87 /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
88 /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
89 /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
90 /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
91 /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
92 /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
93 /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
94 /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
95 /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
96 /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
c3c7f861
WD		 97 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
98 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
99 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
100 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
101 },
102
103 /* Port C */
104 { /* conf ppar psor pdir podr pdat */
105 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
106 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
107 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
108 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
109 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
110 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
111 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
112 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
113 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
114 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
115 /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
116 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
117 /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
6d0f6bcf 118 /* PC18 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */
c3c7f861 119 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
6d0f6bcf 120 /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */
c3c7f861
WD		 121 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
122 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
123 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
124 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
125 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
126 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
127 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
128 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
129 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
130 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
131 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
132 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
133 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
134 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
135 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
136 /* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */
137 },
138
139 /* Port D */
140 { /* conf ppar psor pdir podr pdat */
141 /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
142 /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
143 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
144 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
145 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
146 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
147 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
148 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
149 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
150 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
151 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
152 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
153 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
154 /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */
155 /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */
156 /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */
157 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
158 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
159 /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */
160 /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */
161 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
162 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
163 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */
164 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */
165 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
6d0f6bcf
JCPV		 166 /* PD6 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */
167 /* PD5 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */
c3c7f861
WD		 168 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
169 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
170 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
171 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
172 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
173 }
174};
175
176#define PSPAN_ADDR 0xF0020000
177#define EEPROM_REG 0x408
178#define EEPROM_READ_CMD 0xA000
179#define PSPAN_WRITE(a,v) \
180 *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
181#define PSPAN_READ(a) \
182 *((volatile unsigned long *)(PSPAN_ADDR+(a)))
183
184static int seeprom_read (int addr, uchar * data, int size)
185{
186 ulong val, cmd;
187 int i;
188
189 for (i = 0; i < size; i++) {
190
191 cmd = EEPROM_READ_CMD;
192 cmd |= ((addr + i) << 24) & 0xff000000;
193
194 /* Wait for ACT to authorize write */
195 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
196 eieio ();
197
198 /* Write command */
199 PSPAN_WRITE (EEPROM_REG, cmd);
200
201 /* Wait for data to be valid */
202 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
203 eieio ();
204 /* Do it twice, first read might be erratic */
205 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
206 eieio ();
207
208 /* Read error */
209 if (val & 0x00000040) {
210 return -1;
211 } else {
212 data[i] = (val >> 16) & 0xff;
213 }
214 }
215 return 0;
216}
217
218/***************************************************************
219 * We take some basic Hardware Configuration Parameter from the
220 * Serial EEPROM conected to the PSpan bridge. We keep it as
221 * simple as possible.
222 */
b54d32b4 223#ifdef DEBUG
c3c7f861
WD		 224static int hwc_flash_size (void)
225{
226 uchar byte;
227
228 if (!seeprom_read (0x40, &byte, sizeof (byte))) {
229 switch ((byte >> 2) & 0x3) {
230 case 0x1:
231 return 0x0400000;
232 break;
233 case 0x2:
234 return 0x0800000;
235 break;
236 case 0x3:
237 return 0x1000000;
238 default:
239 return 0x0100000;
240 }
241 }
242 return -1;
243}
244
245static int hwc_local_sdram_size (void)
246{
247 uchar byte;
248
249 if (!seeprom_read (0x40, &byte, sizeof (byte))) {
250 switch ((byte & 0x03)) {
251 case 0x1:
252 return 0x0800000;
253 case 0x2:
254 return 0x1000000;
255 default:
256 return 0; /* not present */
257 }
258 }
259 return -1;
260}
b54d32b4 261#endif /* DEBUG */
c3c7f861
WD		 262
263static int hwc_main_sdram_size (void)
264{
265 uchar byte;
266
267 if (!seeprom_read (0x41, &byte, sizeof (byte))) {
268 return 0x1000000 << ((byte >> 5) & 0x7);
269 }
270 return -1;
271}
272
273static int hwc_serial_number (void)
274{
275 int sn = -1;
276
77ddac94 277 if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
c3c7f861
WD		 278 sn = cpu_to_le32 (sn);
279 }
280 return sn;
281}
282
283static int hwc_mac_address (char *str)
284{
285 char mac[6];
286
77ddac94 287 if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
c3c7f861
WD		 288 sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
289 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
290 } else {
291 strcpy (str, "ERROR");
292 return -1;
293 }
294 return 0;
295}
296
297static int hwc_manufact_date (char *str)
298{
299 uchar byte;
300 int value;
301
302 if (seeprom_read (0x92, &byte, sizeof (byte)))
303 goto out;
304 value = byte;
305 if (seeprom_read (0x93, &byte, sizeof (byte)))
306 goto out;
307 value += byte << 8;
308 sprintf (str, "%02d/%02d/%04d",
309 value & 0x1F, (value >> 5) & 0xF,
310 1980 + ((value >> 9) & 0x1FF));
311 return 0;
312
313out:
314 strcpy (str, "ERROR");
315 return -1;
316}
317
318static int hwc_board_type (char **str)
319{
320 ushort id = 0;
321
322 if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
323 switch (id) {
324 case 0x9080:
325 *str = "4532-002";
326 break;
327 case 0x9081:
328 *str = "4532-001";
329 break;
330 case 0x9082:
331 *str = "4532-000";
332 break;
333 default:
334 *str = "Unknown";
335 }
336 } else {
337 *str = "Unknown";
338 }
339
340 return id;
341}
342
9973e3c6 343phys_size_t initdram (int board_type)
c3c7f861
WD		 344{
345 long maxsize = hwc_main_sdram_size();
346
6d0f6bcf
JCPV		 347#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE)
348 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
c3c7f861
WD		 349 volatile memctl8260_t *memctl = &immap->im_memctl;
350 volatile uchar *base;
351 int i;
352
353 immap->im_siu_conf.sc_ppc_acr = 0x00000026;
354 immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
355 immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
356 immap->im_siu_conf.sc_lcl_acr = 0x00000000;
357 immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
358 immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
359 immap->im_siu_conf.sc_tescr1 = 0x00004000;
360 immap->im_siu_conf.sc_ltescr1 = 0x00004000;
361
6d0f6bcf 362 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
c3c7f861
WD		 363
364 /* Initialise 60x bus SDRAM */
6d0f6bcf
JCPV		 365 base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110);
366 memctl->memc_psrt = CONFIG_SYS_PSRT;
367 memctl->memc_or1 = CONFIG_SYS_60x_OR;
368 memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR;
c3c7f861 369
6d0f6bcf 370 memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
c3c7f861 371 *base = 0xFF;
6d0f6bcf 372 memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
c3c7f861
WD		 373 for (i = 0; i < 8; i++)
374 *base = 0xFF;
6d0f6bcf 375 memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
c3c7f861 376 *base = 0xFF;
6d0f6bcf 377 memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
c3c7f861
WD		 378
379 /* Initialise local bus SDRAM */
6d0f6bcf
JCPV		 380 base = (uchar *)CONFIG_SYS_LSDRAM_BASE;
381 memctl->memc_lsrt = CONFIG_SYS_LSRT;
382 memctl->memc_or2 = CONFIG_SYS_LOC_OR;
383 memctl->memc_br2 = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR;
c3c7f861 384
6d0f6bcf 385 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
c3c7f861 386 *base = 0xFF;
6d0f6bcf 387 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
c3c7f861
WD		 388 for (i = 0; i < 8; i++)
389 *base = 0xFF;
6d0f6bcf 390 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
c3c7f861 391 *base = 0xFF;
6d0f6bcf 392 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
c3c7f861
WD		 393
394 /* We must be able to test a location outsize the maximum legal size
395 * to find out THAT we are outside; but this address still has to be
396 * mapped by the controller. That means, that the initial mapping has
397 * to be (at least) twice as large as the maximum expected size.
398 */
399 maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
400
401 maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
402
403 memctl->memc_or1 |= ~(maxsize - 1);
404
405 if (maxsize != hwc_main_sdram_size())
406 puts("Oops: memory test has not found all memory!\n");
6d0f6bcf 407#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */
c3c7f861
WD		 408
409 /* Return total RAM size (size of 60x SDRAM) */
410 return maxsize;
411}
412
413int checkboard(void)
414{
415 char string[32], *id;
416
417 hwc_manufact_date(string);
418 hwc_board_type(&id);
419 printf("Board: Interphase iSPAN %s (#%d %s)\n",
420 id, hwc_serial_number(), string);
421#ifdef DEBUG
422 printf("Manufacturing date: %s\n", string);
423 printf("Serial number : %d\n", hwc_serial_number());
424 printf("FLASH size : %d MB\n", hwc_flash_size() >> 20);
425 printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20);
426 printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20);
427 hwc_mac_address(string);
428 printf("MAC address : %s\n", string);
429#endif
430 return 0;
431}
432
433int misc_init_r(void)
434{
435 char *s, str[32];
436 int num;
437
438 if ((s = getenv("serial#")) == NULL &&
439 (num = hwc_serial_number()) != -1) {
440 sprintf(str, "%06d", num);
441 setenv("serial#", str);
442 }
443 if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
444 setenv("ethaddr", str);
445 }
446
447 return 0;
448}
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