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2d5b561e | 1 | /* |
ba94a1bb WD |
2 | * (C) Copyright 2006 |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
2d5b561e WD |
5 | * (C) Copyright 2002 |
6 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
7 | * | |
8 | * (C) Copyright 2002 | |
9 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
10 | * Marius Groeger <mgroeger@sysgo.de> | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | ||
2d5b561e | 31 | #include <common.h> |
ba94a1bb WD |
32 | #include <command.h> |
33 | #include <malloc.h> | |
10efa024 | 34 | #include <netdev.h> |
ba94a1bb | 35 | #include <asm/arch/ixp425.h> |
973af335 MS |
36 | #include <asm/io.h> |
37 | #ifdef CONFIG_PCI | |
38 | #include <pci.h> | |
39 | #include <asm/arch/ixp425pci.h> | |
40 | #endif | |
2d5b561e | 41 | |
d87080b7 | 42 | DECLARE_GLOBAL_DATA_PTR; |
2d5b561e | 43 | |
973af335 MS |
44 | #define IXDP425_LED_PORT 0x52000000 /* 4-digit hex display */ |
45 | ||
46 | int board_early_init_f(void) | |
47 | { | |
48 | /* CS2: LED port */ | |
49 | writel(0xbcff0002, IXP425_EXP_CS2); | |
50 | writew(0x0001, IXDP425_LED_PORT); /* output postcode to LEDs */ | |
51 | ||
52 | return 0; | |
53 | } | |
54 | ||
55 | #ifdef CONFIG_PCI | |
56 | #ifndef CONFIG_PCI_PNP | |
57 | static struct pci_config_table pci_ixpdp425_config_table[] = { | |
58 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, PCI_ANY_ID, | |
59 | pci_cfgfunc_config_device, | |
60 | { 0x400, | |
61 | 0x40000000, | |
62 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, | |
63 | ||
64 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x01, PCI_ANY_ID, | |
65 | pci_cfgfunc_config_device, | |
66 | { 0x800, | |
67 | 0x40010000, | |
68 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, | |
69 | ||
70 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x02, PCI_ANY_ID, | |
71 | pci_cfgfunc_config_device, | |
72 | { 0xc00, | |
73 | 0x40020000, | |
74 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, | |
75 | ||
76 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x03, PCI_ANY_ID, | |
77 | pci_cfgfunc_config_device, | |
78 | { 0x1000, | |
79 | 0x40030000, | |
80 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } }, | |
81 | { } | |
82 | }; | |
83 | #endif | |
84 | ||
85 | struct pci_controller hose = { | |
86 | #ifndef CONFIG_PCI_PNP | |
87 | config_table: pci_ixpdp425_config_table, | |
88 | #endif | |
89 | }; | |
90 | #endif /* CONFIG_PCI */ | |
91 | ||
92 | ||
2d5b561e WD |
93 | /* |
94 | * Miscelaneous platform dependent initialisations | |
95 | */ | |
973af335 | 96 | int board_init(void) |
2d5b561e | 97 | { |
973af335 MS |
98 | writew(0x0002, IXDP425_LED_PORT); /* output postcode to LEDs */ |
99 | ||
100 | #ifdef CONFIG_IXDPG425 | |
101 | /* arch number of IXDP */ | |
102 | gd->bd->bi_arch_number = MACH_TYPE_IXDPG425; | |
103 | #else | |
2d5b561e | 104 | /* arch number of IXDP */ |
731215eb | 105 | gd->bd->bi_arch_number = MACH_TYPE_IXDP425; |
973af335 | 106 | #endif |
2d5b561e WD |
107 | |
108 | /* adress of boot parameters */ | |
109 | gd->bd->bi_boot_params = 0x00000100; | |
110 | ||
ba94a1bb | 111 | #ifdef CONFIG_IXDPG425 |
ba94a1bb WD |
112 | /* |
113 | * Get realtek RTL8305 switch and SLIC out of reset | |
114 | */ | |
6d0f6bcf JCPV |
115 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SWITCH_RESET_N); |
116 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SWITCH_RESET_N); | |
117 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N); | |
118 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N); | |
ba94a1bb WD |
119 | |
120 | /* | |
973af335 | 121 | * Setup GPIOs for PCI INTA & INTB |
ba94a1bb | 122 | */ |
6d0f6bcf JCPV |
123 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N); |
124 | GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N); | |
125 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N); | |
126 | GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N); | |
ba94a1bb | 127 | |
973af335 MS |
128 | /* Setup GPIOs for 33MHz clock output */ |
129 | writel(0x01FF01FF, IXP425_GPIO_GPCLKR); | |
130 | ||
6d0f6bcf JCPV |
131 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); |
132 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); | |
973af335 MS |
133 | |
134 | /* set GPIO8..11 interrupt type to active low */ | |
135 | writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R); | |
136 | ||
137 | /* clear pending interrupts */ | |
138 | writel(-1, IXP425_GPIO_GPISR); | |
139 | ||
140 | /* assert PCI reset */ | |
141 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_SLIC_RESET_N); | |
142 | ||
143 | udelay(533); | |
144 | ||
145 | /* deassert PCI reset */ | |
146 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N); | |
147 | ||
148 | udelay(533); | |
149 | ||
150 | #else /* IXDP425 */ | |
151 | /* Setup GPIOs for 33MHz ExpBus and PCI clock output */ | |
152 | writel(0x01FF01FF, IXP425_GPIO_GPCLKR); | |
153 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); | |
154 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); | |
155 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_RESET_N); | |
156 | ||
157 | /* set GPIO8..11 interrupt type to active low */ | |
158 | writel((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1, IXP425_GPIO_GPIT2R); | |
159 | /* clear pending interrupts */ | |
160 | writel(-1, IXP425_GPIO_GPISR); | |
161 | ||
162 | /* assert PCI reset */ | |
163 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCI_RESET_N); | |
164 | ||
165 | udelay(533); | |
166 | ||
167 | /* deassert PCI reset */ | |
168 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCI_RESET_N); | |
169 | ||
170 | udelay(533); | |
ba94a1bb WD |
171 | #endif |
172 | ||
2d5b561e WD |
173 | return 0; |
174 | } | |
175 | ||
ba94a1bb WD |
176 | /* |
177 | * Check Board Identity | |
178 | */ | |
179 | int checkboard(void) | |
180 | { | |
f0c0b3a9 WD |
181 | char buf[64]; |
182 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
ba94a1bb WD |
183 | |
184 | #ifdef CONFIG_IXDPG425 | |
185 | puts("Board: IXDPG425 - Intel Network Gateway Reference Platform"); | |
186 | #else | |
187 | puts("Board: IXDP425 - Intel Development Platform"); | |
188 | #endif | |
189 | ||
f0c0b3a9 | 190 | if (i > 0) { |
ba94a1bb | 191 | puts(", serial# "); |
f0c0b3a9 | 192 | puts(buf); |
ba94a1bb WD |
193 | } |
194 | putc('\n'); | |
195 | ||
973af335 | 196 | return 0; |
ba94a1bb | 197 | } |
289f932c | 198 | |
973af335 | 199 | int dram_init(void) |
2d5b561e | 200 | { |
973af335 MS |
201 | /* we can only map 64MB via PCI, so we limit memory |
202 | until a better solution is implemented. */ | |
203 | #ifdef CONFIG_PCI | |
204 | gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 64<<20); | |
205 | #else | |
206 | gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 256<<20); | |
207 | #endif | |
208 | return 0; | |
2d5b561e | 209 | } |
289f932c | 210 | |
973af335 | 211 | #ifdef CONFIG_PCI |
a1191902 WD |
212 | void pci_init_board(void) |
213 | { | |
214 | pci_ixp_init(&hose); | |
a1191902 | 215 | } |
973af335 MS |
216 | |
217 | /* | |
218 | * dev 0 on the PCI bus is not the host bridge, so we have to override | |
219 | * these functions in order to not skip PCI slot 0 during configuration. | |
220 | */ | |
221 | int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) | |
222 | { | |
223 | return 0; | |
224 | } | |
225 | int pci_print_dev(struct pci_controller *hose, pci_dev_t dev) | |
226 | { | |
227 | return 1; | |
228 | } | |
229 | ||
ba94a1bb | 230 | #endif |
10efa024 BW |
231 | |
232 | int board_eth_init(bd_t *bis) | |
233 | { | |
973af335 MS |
234 | #ifdef CONFIG_PCI |
235 | pci_eth_init(bis); | |
236 | #endif | |
237 | return cpu_eth_init(bis); | |
10efa024 | 238 | } |