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db01a2ea WD |
1 | /* |
2 | * Copyright (c) 2004 Picture Elements, Inc. | |
3 | * Stephen Williams (steve@icarus.com) | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
db01a2ea WD |
6 | */ |
7 | ||
8 | # include <common.h> | |
b36df561 | 9 | # include <asm/ppc4xx.h> |
db01a2ea WD |
10 | # include <asm/processor.h> |
11 | # include <asm/io.h> | |
12 | # include "jse_priv.h" | |
13 | ||
14 | /* | |
15 | * This function is run very early, out of flash, and before devices are | |
a47a12be | 16 | * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue |
db01a2ea WD |
17 | * of being in the init_sequence array. |
18 | * | |
19 | * The SDRAM has been initialized already -- start.S:start called | |
20 | * init.S:init_sdram early on -- but it is not yet being used for | |
21 | * anything, not even stack. So be careful. | |
22 | */ | |
23 | int board_early_init_f (void) | |
24 | { | |
25 | /*-------------------------------------------------------------------------+ | |
26 | | Interrupt controller setup for the JSE board. | |
27 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
28 | | IRQ 16 405GP internally generated; active low; level sensitive | |
29 | | IRQ 17-24 RESERVED/UNUSED | |
30 | | IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive | |
31 | | IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive | |
32 | | IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive | |
33 | | IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive | |
34 | | IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high | |
35 | | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused) | |
36 | | IRQ 31 (EXT IRQ 6) (unused) | |
37 | +-------------------------------------------------------------------------*/ | |
952e7760 SR |
38 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
39 | mtdcr (UIC0ER, 0x00000000); /* disable all ints */ | |
40 | mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ | |
41 | mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */ | |
42 | mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ | |
43 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
db01a2ea WD |
44 | |
45 | /* Configure the interface to the SystemACE MCU port. | |
46 | The SystemACE is fast, but there is no reason to have | |
47 | excessivly tight timings. So the settings are slightly | |
48 | generous. */ | |
49 | ||
50 | /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1, | |
51 | WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */ | |
d1c3b275 SR |
52 | mtdcr (EBC0_CFGADDR, PB1AP); |
53 | mtdcr (EBC0_CFGDATA, 0x01011000); | |
db01a2ea WD |
54 | |
55 | /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */ | |
d1c3b275 SR |
56 | mtdcr (EBC0_CFGADDR, PB1CR); |
57 | mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000); | |
db01a2ea WD |
58 | |
59 | /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */ | |
60 | /* CPC0_CR1 |= PCIPW */ | |
61 | mtdcr (0xb2, mfdcr (0xb2) | 0x00004000); | |
62 | ||
63 | return 0; | |
64 | } | |
65 | ||
66 | #ifdef CONFIG_BOARD_PRE_INIT | |
67 | int board_pre_init (void) | |
68 | { | |
69 | return board_early_init_f (); | |
70 | } | |
71 | ||
72 | #endif | |
73 | ||
74 | /* | |
a47a12be | 75 | * This function is also called by arch/powerpc/lib/board.c:board_init_f (it is |
db01a2ea WD |
76 | * also in the init_sequence array) but later. Many more things are |
77 | * configured, but we are still running from flash. | |
78 | */ | |
79 | int checkboard (void) | |
80 | { | |
81 | unsigned vers, status; | |
82 | ||
83 | /* check that the SystemACE chip is alive. */ | |
84 | printf ("ACE: "); | |
6d0f6bcf | 85 | vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16); |
db01a2ea WD |
86 | printf ("SystemACE %u.%u (build %u)", |
87 | (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff); | |
88 | ||
6d0f6bcf | 89 | status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); |
db01a2ea WD |
90 | #ifdef DEBUG |
91 | printf (" STATUS=0x%08x", status); | |
92 | #endif | |
93 | /* If the flash card is present and there is an initial error, | |
94 | then force a restart of the program. */ | |
95 | if (status & 0x00000010) { | |
96 | printf (" CFDETECT"); | |
97 | ||
98 | if (status & 0x04) { | |
99 | /* CONTROLREG = CFGPROG */ | |
6d0f6bcf | 100 | writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18); |
db01a2ea WD |
101 | udelay (500); |
102 | /* CONTROLREG = CFGRESET */ | |
6d0f6bcf | 103 | writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18); |
db01a2ea | 104 | udelay (500); |
6d0f6bcf | 105 | writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18); |
db01a2ea | 106 | /* CONTROLREG = CFGSTART */ |
6d0f6bcf | 107 | writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18); |
db01a2ea | 108 | |
6d0f6bcf | 109 | status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); |
db01a2ea WD |
110 | } |
111 | } | |
112 | ||
113 | /* Wait for the SystemACE to program its chain of devices. */ | |
114 | while ((status & 0x84) == 0x00) { | |
115 | udelay (500); | |
6d0f6bcf | 116 | status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); |
db01a2ea WD |
117 | } |
118 | ||
119 | if (status & 0x04) | |
120 | printf (" CFG-ERROR"); | |
121 | if (status & 0x80) | |
122 | printf (" CFGDONE"); | |
123 | ||
124 | printf ("\n"); | |
125 | ||
126 | /* Force /RTS to active. The board it not wired quite | |
127 | correctly to use cts/rtc flow control, so just force the | |
128 | /RST active and forget about it. */ | |
129 | writeb (readb (0xef600404) | 0x03, 0xef600404); | |
130 | ||
131 | printf ("JSE: ready\n"); | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | /* **** No more functions called by board_init_f. **** */ | |
137 | ||
138 | /* | |
a47a12be | 139 | * This function is called by arch/powerpc/lib/board.c:board_init_r. At this |
db01a2ea WD |
140 | * point, basic setup is done, U-Boot has been moved into SDRAM and |
141 | * PCI has been set up. From here we done late setup. | |
142 | */ | |
143 | int misc_init_r (void) | |
144 | { | |
145 | host_bridge_init (); | |
146 | return 0; | |
147 | } |