[people/ms/u-boot.git] / board / keymile / km_arm / km_arm.c

/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Prafulla Wadaskar <prafulla@marvell.com>
 *
 * (C) Copyright 2009
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2010
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <nand.h>
#include <netdev.h>
#include <miiphy.h>
#include <spi.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>

#include "../common/common.h"

DECLARE_GLOBAL_DATA_PTR;

/*
 * BOCO FPGA definitions
 */
#define BOCO		0x10
#define REG_CTRL_H		0x02
#define MASK_WRL_UNITRUN	0x01
#define MASK_RBX_PGY_PRESENT	0x40
#define REG_IRQ_CIRQ2		0x2d
#define MASK_RBI_DEFECT_16	0x01

/*
 * PHY registers definitions
 */
#define PHY_MARVELL_OUI					0x5043
#define PHY_MARVELL_88E1118_MODEL			0x0022
#define PHY_MARVELL_88E1118R_MODEL			0x0024

#define PHY_MARVELL_PAGE_REG				0x0016
#define PHY_MARVELL_DEFAULT_PAGE			0x0000

#define PHY_MARVELL_88E1118R_LED_CTRL_PAGE		0x0003
#define PHY_MARVELL_88E1118R_LED_CTRL_REG		0x0010

#define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED		0x1000
#define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB	(0x7<<0)
#define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT		(0x3<<4)
#define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK		(0x0<<8)

/* I/O pin to erase flash RGPP09 = MPP43 */
#define KM_FLASH_ERASE_ENABLE	43

/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {
	MPP0_NF_IO2,
	MPP1_NF_IO3,
	MPP2_NF_IO4,
	MPP3_NF_IO5,
	MPP4_NF_IO6,
	MPP5_NF_IO7,
	MPP6_SYSRST_OUTn,
#if defined(KM_PCIE_RESET_MPP7)
	MPP7_GPO,
#else
	MPP7_PEX_RST_OUTn,
#endif
#if defined(CONFIG_SYS_I2C_SOFT)
	MPP8_GPIO,		/* SDA */
	MPP9_GPIO,		/* SCL */
#endif
	MPP10_UART0_TXD,
	MPP11_UART0_RXD,
	MPP12_GPO,		/* Reserved */
	MPP13_UART1_TXD,
	MPP14_UART1_RXD,
	MPP15_GPIO,		/* Not used */
	MPP16_GPIO,		/* Not used */
	MPP17_GPIO,		/* Reserved */
	MPP18_NF_IO0,
	MPP19_NF_IO1,
	MPP20_GPIO,
	MPP21_GPIO,
	MPP22_GPIO,
	MPP23_GPIO,
	MPP24_GPIO,
	MPP25_GPIO,
	MPP26_GPIO,
	MPP27_GPIO,
	MPP28_GPIO,
	MPP29_GPIO,
	MPP30_GPIO,
	MPP31_GPIO,
	MPP32_GPIO,
	MPP33_GPIO,
	MPP34_GPIO,		/* CDL1 (input) */
	MPP35_GPIO,		/* CDL2 (input) */
	MPP36_GPIO,		/* MAIN_IRQ (input) */
	MPP37_GPIO,		/* BOARD_LED */
	MPP38_GPIO,		/* Piggy3 LED[1] */
	MPP39_GPIO,		/* Piggy3 LED[2] */
	MPP40_GPIO,		/* Piggy3 LED[3] */
	MPP41_GPIO,		/* Piggy3 LED[4] */
	MPP42_GPIO,		/* Piggy3 LED[5] */
	MPP43_GPIO,		/* Piggy3 LED[6] */
	MPP44_GPIO,		/* Piggy3 LED[7], BIST_EN_L */
	MPP45_GPIO,		/* Piggy3 LED[8] */
	MPP46_GPIO,		/* Reserved */
	MPP47_GPIO,		/* Reserved */
	MPP48_GPIO,		/* Reserved */
	MPP49_GPIO,		/* SW_INTOUTn */
	0
};

static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];

#if defined(CONFIG_KM_MGCOGE3UN)
/*
 * Wait for startup OK from mgcoge3ne
 */
static int startup_allowed(void)
{
	unsigned char buf;

	/*
	 * Read CIRQ16 bit (bit 0)
	 */
	if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
		printf("%s: Error reading Boco\n", __func__);
	else
		if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
			return 1;
	return 0;
}
#endif

#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
/*
 * All boards with PIGGY4 connected via a simple switch have ethernet always
 * present.
 */
int ethernet_present(void)
{
	return 1;
}
#else
int ethernet_present(void)
{
	uchar	buf;
	int	ret = 0;

	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
		printf("%s: Error reading Boco\n", __func__);
		return -1;
	}
	if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
		ret = 1;

	return ret;
}
#endif

static int initialize_unit_leds(void)
{
	/*
	 * Init the unit LEDs per default they all are
	 * ok apart from bootstat
	 */
	uchar buf;

	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
		printf("%s: Error reading Boco\n", __func__);
		return -1;
	}
	buf |= MASK_WRL_UNITRUN;
	if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
		printf("%s: Error writing Boco\n", __func__);
		return -1;
	}
	return 0;
}

static void set_bootcount_addr(void)
{
	uchar buf[32];
	unsigned int bootcountaddr;
	bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
	sprintf((char *)buf, "0x%x", bootcountaddr);
	env_set("bootcountaddr", (char *)buf);
}

int misc_init_r(void)
{
#if defined(CONFIG_KM_MGCOGE3UN)
	char *wait_for_ne;
	u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
	wait_for_ne = env_get("waitforne");

	if ((wait_for_ne != NULL) && (dip_switch == 0)) {
		if (strcmp(wait_for_ne, "true") == 0) {
			int cnt = 0;
			int abort = 0;
			puts("NE go: ");
			while (startup_allowed() == 0) {
				if (tstc()) {
					(void) getc(); /* consume input */
					abort = 1;
					break;
				}
				udelay(200000);
				cnt++;
				if (cnt == 5)
					puts("wait\b\b\b\b");
				if (cnt == 10) {
					cnt = 0;
					puts("    \b\b\b\b");
				}
			}
			if (abort == 1)
				printf("\nAbort waiting for ne\n");
			else
				puts("OK\n");
		}
	}
#endif

	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);

	initialize_unit_leds();
	set_km_env();
	set_bootcount_addr();
	return 0;
}

int board_early_init_f(void)
{
#if defined(CONFIG_SYS_I2C_SOFT)
	u32 tmp;

	/* set the 2 bitbang i2c pins as output gpios */
	tmp = readl(MVEBU_GPIO0_BASE + 4);
	writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
#endif
	/* adjust SDRAM size for bank 0 */
	mvebu_sdram_size_adjust(0);
	kirkwood_mpp_conf(kwmpp_config, NULL);
	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;

	/*
	 * The KM_FLASH_GPIO_PIN switches between using a
	 * NAND or a SPI FLASH. Set this pin on start
	 * to NAND mode.
	 */
	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);

#if defined(CONFIG_SYS_I2C_SOFT)
	/*
	 * Reinit the GPIO for I2C Bitbang driver so that the now
	 * available gpio framework is consistent. The calls to
	 * direction output in are not necessary, they are already done in
	 * board_early_init_f
	 */
	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
	kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
#endif

#if defined(CONFIG_SYS_EEPROM_WREN)
	kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
	kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
#endif

#if defined(CONFIG_KM_FPGA_CONFIG)
	trigger_fpga_config();
#endif

	return 0;
}

int board_late_init(void)
{
#if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN))
	u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);

	/* if pin 1 do full erase */
	if (dip_switch != 0) {
		/* start bootloader */
		puts("DIP:   Enabled\n");
		env_set("actual_bank", "0");
	}
#endif

#if defined(CONFIG_KM_FPGA_CONFIG)
	wait_for_fpga_config();
	fpga_reset();
	toggle_eeprom_spi_bus();
#endif
	return 0;
}

int board_spi_claim_bus(struct spi_slave *slave)
{
	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);

	return 0;
}

void board_spi_release_bus(struct spi_slave *slave)
{
	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
}

#if (defined(CONFIG_KM_PIGGY4_88E6061))

#define	PHY_LED_SEL_REG		0x18
#define PHY_LED0_LINK		(0x5)
#define PHY_LED1_ACT		(0x8<<4)
#define PHY_LED2_INT		(0xe<<8)
#define	PHY_SPEC_CTRL_REG	0x1c
#define PHY_RGMII_CLK_STABLE	(0x1<<10)
#define PHY_CLSA		(0x1<<1)

/* Configure and enable MV88E3018 PHY */
void reset_phy(void)
{
	char *name = "egiga0";
	unsigned short reg;

	if (miiphy_set_current_dev(name))
		return;

	/* RGMII clk transition on data stable */
	if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
		printf("Error reading PHY spec ctrl reg\n");
	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
			 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
		printf("Error writing PHY spec ctrl reg\n");

	/* leds setup */
	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
			 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
		printf("Error writing PHY LED reg\n");

	/* reset the phy */
	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
#elif defined(CONFIG_KM_PIGGY4_88E6352)

#include <mv88e6352.h>

#if defined(CONFIG_KM_NUSA)
struct mv88e_sw_reg extsw_conf[] = {
	/*
	 * port 0, PIGGY4, autoneg
	 * first the fix for the 1000Mbits Autoneg, this is from
	 * a Marvell errata, the regs are undocumented
	 */
	{ PHY(0), PHY_PAGE, AN1000FIX_PAGE },
	{ PHY(0), PHY_STATUS, AN1000FIX },
	{ PHY(0), PHY_PAGE, 0 },
	/* now the real port and phy configuration */
	{ PORT(0), PORT_PHY, NO_SPEED_FOR },
	{ PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
	{ PHY(0), PHY_1000_CTRL, NO_ADV },
	{ PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
	{ PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
		FULL_DUPLEX },
	/* port 1, unused */
	{ PORT(1), PORT_CTRL, PORT_DIS },
	{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
	{ PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
	/* port 2, unused */
	{ PORT(2), PORT_CTRL, PORT_DIS },
	{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
	{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
	/* port 3, unused */
	{ PORT(3), PORT_CTRL, PORT_DIS },
	{ PHY(3), PHY_CTRL, PHY_PWR_DOWN },
	{ PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
	/* port 4, ICNEV, SerDes, SGMII */
	{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
	{ PORT(4), PORT_PHY, SPEED_1000_FOR },
	{ PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
	{ PHY(4), PHY_CTRL, PHY_PWR_DOWN },
	{ PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
	/* port 5, CPU_RGMII */
	{ PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
		FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
		FULL_DPX_FOR | SPEED_1000_FOR },
	{ PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
	/* port 6, unused, this port has no phy */
	{ PORT(6), PORT_CTRL, PORT_DIS },
};
#else
struct mv88e_sw_reg extsw_conf[] = {};
#endif

void reset_phy(void)
{
#if defined(CONFIG_KM_MVEXTSW_ADDR)
	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
		ARRAY_SIZE(extsw_conf));
	mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
#endif
}

#else
/* Configure and enable MV88E1118 PHY on the piggy*/
void reset_phy(void)
{
	unsigned int oui;
	unsigned char model, rev;

	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	/* reset the phy */
	miiphy_reset(name, CONFIG_PHY_BASE_ADR);

	/* get PHY model */
	if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
		return;

	/* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
	if ((oui == PHY_MARVELL_OUI) &&
	    (model == PHY_MARVELL_88E1118R_MODEL)) {
		/* set page register to 3 */
		if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
				 PHY_MARVELL_PAGE_REG,
				 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
			printf("Error writing PHY page reg\n");

		/*
		 * leds setup as printed on PCB:
		 * LED2 (Link): 0x0 (On Link, Off No Link)
		 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
		 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
		 */
		if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
				 PHY_MARVELL_88E1118R_LED_CTRL_REG,
				 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
				 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
				 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
				 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
			printf("Error writing PHY LED reg\n");

		/* set page register back to 0 */
		if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
				 PHY_MARVELL_PAGE_REG,
				 PHY_MARVELL_DEFAULT_PAGE))
			printf("Error writing PHY page reg\n");
	}
}
#endif


#if defined(CONFIG_HUSH_INIT_VAR)
int hush_init_var(void)
{
	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
	return 0;
}
#endif

#if defined(CONFIG_SYS_I2C_SOFT)
void set_sda(int state)
{
	I2C_ACTIVE;
	I2C_SDA(state);
}

void set_scl(int state)
{
	I2C_SCL(state);
}

int get_sda(void)
{
	I2C_TRISTATE;
	return I2C_READ;
}

int get_scl(void)
{
	return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
}
#endif

#if defined(CONFIG_POST)

#define KM_POST_EN_L	44
#define POST_WORD_OFF	8

int post_hotkeys_pressed(void)
{
#if defined(CONFIG_KM_COGE5UN)
	return kw_gpio_get_value(KM_POST_EN_L);
#else
	return !kw_gpio_get_value(KM_POST_EN_L);
#endif
}

ulong post_word_load(void)
{
	void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
	return in_le32(addr);

}
void post_word_store(ulong value)
{
	void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
	out_le32(addr, value);
}

int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
	*vstart = CONFIG_SYS_SDRAM_BASE;

	/* we go up to relocation plus a 1 MB margin */
	*size = CONFIG_SYS_TEXT_BASE - (1<<20);

	return 0;
}
#endif

#if defined(CONFIG_SYS_EEPROM_WREN)
int eeprom_write_enable(unsigned dev_addr, int state)
{
	kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);

	return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
}
#endif
Commit	Line	Data
67fa8c25 HS	1	/*
	2	* (C) Copyright 2009
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Prafulla Wadaskar <prafulla@marvell.com>
	5	*
	6	* (C) Copyright 2009
	7	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	8	*
	9	* (C) Copyright 2010
	10	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
67fa8c25 HS	13	*/
	14
	15	#include <common.h>
	16	#include <i2c.h>
	17	#include <nand.h>
	18	#include <netdev.h>
	19	#include <miiphy.h>
0c25defc	20	#include <spi.h>
67fa8c25	21	#include <asm/io.h>
a7efd719	22	#include <asm/arch/cpu.h>
3dc23f78	23	#include <asm/arch/soc.h>
67fa8c25 HS	24	#include <asm/arch/mpp.h>
	25
	26	#include "../common/common.h"
	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
8612b701 HB	30	/*
	31	* BOCO FPGA definitions
	32	*/
	33	#define BOCO 0x10
	34	#define REG_CTRL_H 0x02
	35	#define MASK_WRL_UNITRUN 0x01
	36	#define MASK_RBX_PGY_PRESENT 0x40
	37	#define REG_IRQ_CIRQ2 0x2d
	38	#define MASK_RBI_DEFECT_16 0x01
	39
9ff739e4 TM	40	/*
	41	* PHY registers definitions
	42	*/
	43	#define PHY_MARVELL_OUI 0x5043
	44	#define PHY_MARVELL_88E1118_MODEL 0x0022
	45	#define PHY_MARVELL_88E1118R_MODEL 0x0024
	46
	47	#define PHY_MARVELL_PAGE_REG 0x0016
	48	#define PHY_MARVELL_DEFAULT_PAGE 0x0000
	49
	50	#define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
	51	#define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
	52
	53	#define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
	54	#define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
	55	#define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
	56	#define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
	57
e23fde7d HB	58	/* I/O pin to erase flash RGPP09 = MPP43 */
	59	#define KM_FLASH_ERASE_ENABLE 43
	60
67fa8c25	61	/* Multi-Purpose Pins Functionality configuration */
9d86f0c3	62	static const u32 kwmpp_config[] = {
67fa8c25 HS	63	MPP0_NF_IO2,
	64	MPP1_NF_IO3,
	65	MPP2_NF_IO4,
	66	MPP3_NF_IO5,
	67	MPP4_NF_IO6,
	68	MPP5_NF_IO7,
	69	MPP6_SYSRST_OUTn,
9c134e18 GF	70	#if defined(KM_PCIE_RESET_MPP7)
	71	MPP7_GPO,
	72	#else
67fa8c25	73	MPP7_PEX_RST_OUTn,
9c134e18	74	#endif
ea818dbb	75	#if defined(CONFIG_SYS_I2C_SOFT)
67fa8c25 HS	76	MPP8_GPIO, /* SDA */
67fa8c25 HS	77	MPP9_GPIO, /* SCL */
67fa8c25 HS	78	#endif
	79	MPP10_UART0_TXD,
	80	MPP11_UART0_RXD,
	81	MPP12_GPO, /* Reserved */
	82	MPP13_UART1_TXD,
	83	MPP14_UART1_RXD,
	84	MPP15_GPIO, /* Not used */
	85	MPP16_GPIO, /* Not used */
	86	MPP17_GPIO, /* Reserved */
	87	MPP18_NF_IO0,
	88	MPP19_NF_IO1,
	89	MPP20_GPIO,
	90	MPP21_GPIO,
	91	MPP22_GPIO,
	92	MPP23_GPIO,
	93	MPP24_GPIO,
	94	MPP25_GPIO,
	95	MPP26_GPIO,
	96	MPP27_GPIO,
	97	MPP28_GPIO,
	98	MPP29_GPIO,
	99	MPP30_GPIO,
	100	MPP31_GPIO,
	101	MPP32_GPIO,
	102	MPP33_GPIO,
	103	MPP34_GPIO, /* CDL1 (input) */
	104	MPP35_GPIO, /* CDL2 (input) */
	105	MPP36_GPIO, /* MAIN_IRQ (input) */
	106	MPP37_GPIO, /* BOARD_LED */
	107	MPP38_GPIO, /* Piggy3 LED[1] */
	108	MPP39_GPIO, /* Piggy3 LED[2] */
	109	MPP40_GPIO, /* Piggy3 LED[3] */
	110	MPP41_GPIO, /* Piggy3 LED[4] */
	111	MPP42_GPIO, /* Piggy3 LED[5] */
	112	MPP43_GPIO, /* Piggy3 LED[6] */
44097e26	113	MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
67fa8c25 HS	114	MPP45_GPIO, /* Piggy3 LED[8] */
	115	MPP46_GPIO, /* Reserved */
	116	MPP47_GPIO, /* Reserved */
	117	MPP48_GPIO, /* Reserved */
	118	MPP49_GPIO, /* SW_INTOUTn */
	119	0
	120	};
	121
0bb95a68 VL	122	static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
0bb95a68 VL	123
f945439a	124	#if defined(CONFIG_KM_MGCOGE3UN)
8612b701 HB	125	/*
	126	* Wait for startup OK from mgcoge3ne
	127	*/
aef0bdc0	128	static int startup_allowed(void)
8612b701 HB	129	{
	130	unsigned char buf;
	131
	132	/*
	133	* Read CIRQ16 bit (bit 0)
	134	*/
	135	if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
	136	printf("%s: Error reading Boco\n", __func__);
	137	else
	138	if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
	139	return 1;
	140	return 0;
	141	}
01fa4e8c	142	#endif
8612b701	143
f945439a	144	#if (defined(CONFIG_KM_PIGGY4_88E6061)\|defined(CONFIG_KM_PIGGY4_88E6352))
8612b701	145	/*
8170aefc HB	146	* All boards with PIGGY4 connected via a simple switch have ethernet always
8170aefc HB	147	* present.
8612b701 HB	148	*/
	149	int ethernet_present(void)
	150	{
	151	return 1;
	152	}
	153	#else
67fa8c25 HS	154	int ethernet_present(void)
	155	{
	156	uchar buf;
	157	int ret = 0;
	158
8612b701	159	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
b11f53f3	160	printf("%s: Error reading Boco\n", __func__);
67fa8c25 HS	161	return -1;
67fa8c25 HS	162	}
8612b701	163	if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
67fa8c25	164	ret = 1;
b11f53f3	165
67fa8c25 HS	166	return ret;
67fa8c25 HS	167	}
8612b701	168	#endif
67fa8c25	169
74ae612f	170	static int initialize_unit_leds(void)
731b9680 HS	171	{
731b9680 HS	172	/*
8612b701	173	* Init the unit LEDs per default they all are
731b9680	174	* ok apart from bootstat
731b9680	175	*/
731b9680 HS	176	uchar buf;
731b9680 HS	177
8612b701	178	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
731b9680 HS	179	printf("%s: Error reading Boco\n", __func__);
	180	return -1;
	181	}
8612b701 HB	182	buf \|= MASK_WRL_UNITRUN;
8612b701 HB	183	if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
731b9680 HS	184	printf("%s: Error writing Boco\n", __func__);
	185	return -1;
	186	}
	187	return 0;
	188	}
	189
74ae612f	190	static void set_bootcount_addr(void)
22c67d08 VL	191	{
	192	uchar buf[32];
	193	unsigned int bootcountaddr;
	194	bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
	195	sprintf((char *)buf, "0x%x", bootcountaddr);
382bee57	196	env_set("bootcountaddr", (char *)buf);
22c67d08	197	}
22c67d08	198
67fa8c25 HS	199	int misc_init_r(void)
67fa8c25 HS	200	{
f945439a	201	#if defined(CONFIG_KM_MGCOGE3UN)
8612b701	202	char *wait_for_ne;
e23fde7d	203	u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
00caae6d	204	wait_for_ne = env_get("waitforne");
e23fde7d HB	205
e23fde7d HB	206	if ((wait_for_ne != NULL) && (dip_switch == 0)) {
8612b701 HB	207	if (strcmp(wait_for_ne, "true") == 0) {
8612b701 HB	208	int cnt = 0;
6264800e	209	int abort = 0;
8612b701 HB	210	puts("NE go: ");
8612b701 HB	211	while (startup_allowed() == 0) {
6264800e HB	212	if (tstc()) {
	213	(void) getc(); /* consume input */
	214	abort = 1;
	215	break;
	216	}
8612b701 HB	217	udelay(200000);
	218	cnt++;
	219	if (cnt == 5)
	220	puts("wait\b\b\b\b");
	221	if (cnt == 10) {
	222	cnt = 0;
	223	puts(" \b\b\b\b");
	224	}
	225	}
6264800e HB	226	if (abort == 1)
	227	printf("\nAbort waiting for ne\n");
	228	else
	229	puts("OK\n");
8612b701 HB	230	}
	231	}
	232	#endif
731b9680	233
60c4ae00	234	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
0bb95a68	235
731b9680	236	initialize_unit_leds();
22c67d08	237	set_km_env();
22c67d08	238	set_bootcount_addr();
67fa8c25 HS	239	return 0;
	240	}
	241
6b0ccc3b	242	int board_early_init_f(void)
67fa8c25	243	{
ea818dbb	244	#if defined(CONFIG_SYS_I2C_SOFT)
67fa8c25 HS	245	u32 tmp;
67fa8c25 HS	246
c471d848	247	/* set the 2 bitbang i2c pins as output gpios */
d5c5132f SR	248	tmp = readl(MVEBU_GPIO0_BASE + 4);
d5c5132f SR	249	writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
c471d848	250	#endif
3a5b9fe6	251	/* adjust SDRAM size for bank 0 */
96c5f081	252	mvebu_sdram_size_adjust(0);
84683638	253	kirkwood_mpp_conf(kwmpp_config, NULL);
c471d848 HB	254	return 0;
c471d848 HB	255	}
67fa8c25	256
c471d848 HB	257	int board_init(void)
c471d848 HB	258	{
c471d848	259	/* address of boot parameters */
96c5f081	260	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
c471d848 HB	261
	262	/*
	263	* The KM_FLASH_GPIO_PIN switches between using a
67fa8c25 HS	264	* NAND or a SPI FLASH. Set this pin on start
	265	* to NAND mode.
	266	*/
c471d848 HB	267	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
c471d848 HB	268	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
67fa8c25	269
ea818dbb	270	#if defined(CONFIG_SYS_I2C_SOFT)
c471d848 HB	271	/*
	272	* Reinit the GPIO for I2C Bitbang driver so that the now
	273	* available gpio framework is consistent. The calls to
	274	* direction output in are not necessary, they are already done in
	275	* board_early_init_f
	276	*/
44097e26 HS	277	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
44097e26 HS	278	kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
67fa8c25	279	#endif
c471d848	280
67fa8c25	281	#if defined(CONFIG_SYS_EEPROM_WREN)
44097e26 HS	282	kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
44097e26 HS	283	kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
f0d64257	284	#endif
6b0ccc3b	285
b37f7724 VL	286	#if defined(CONFIG_KM_FPGA_CONFIG)
	287	trigger_fpga_config();
	288	#endif
	289
	290	return 0;
	291	}
	292
	293	int board_late_init(void)
	294	{
30f9ad77	295	#if (defined(CONFIG_KM_COGE5UN) \| defined(CONFIG_KM_MGCOGE3UN))
b8cf7cc8 TH	296	u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
	297
	298	/* if pin 1 do full erase */
	299	if (dip_switch != 0) {
	300	/* start bootloader */
	301	puts("DIP: Enabled\n");
382bee57	302	env_set("actual_bank", "0");
b8cf7cc8 TH	303	}
	304	#endif
	305
b37f7724 VL	306	#if defined(CONFIG_KM_FPGA_CONFIG)
	307	wait_for_fpga_config();
	308	fpga_reset();
	309	toggle_eeprom_spi_bus();
	310	#endif
67fa8c25 HS	311	return 0;
	312	}
	313
0c25defc	314	int board_spi_claim_bus(struct spi_slave *slave)
67fa8c25	315	{
0c25defc	316	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
67fa8c25 HS	317
	318	return 0;
	319	}
	320
0c25defc VL	321	void board_spi_release_bus(struct spi_slave *slave)
	322	{
	323	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
	324	}
67fa8c25	325
6ef64861	326	#if (defined(CONFIG_KM_PIGGY4_88E6061))
8f2827fc	327
c1b8514a VL	328	#define PHY_LED_SEL_REG 0x18
	329	#define PHY_LED0_LINK (0x5)
	330	#define PHY_LED1_ACT (0x8<<4)
	331	#define PHY_LED2_INT (0xe<<8)
	332	#define PHY_SPEC_CTRL_REG 0x1c
8f2827fc	333	#define PHY_RGMII_CLK_STABLE (0x1<<10)
c1b8514a	334	#define PHY_CLSA (0x1<<1)
8f2827fc VL	335
	336	/* Configure and enable MV88E3018 PHY */
	337	void reset_phy(void)
	338	{
	339	char *name = "egiga0";
	340	unsigned short reg;
	341
	342	if (miiphy_set_current_dev(name))
	343	return;
	344
	345	/* RGMII clk transition on data stable */
fa6e0ecb	346	if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
8f2827fc	347	printf("Error reading PHY spec ctrl reg\n");
fa6e0ecb HB	348	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
fa6e0ecb HB	349	reg \| PHY_RGMII_CLK_STABLE \| PHY_CLSA))
8f2827fc VL	350	printf("Error writing PHY spec ctrl reg\n");
	351
	352	/* leds setup */
fa6e0ecb HB	353	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
fa6e0ecb HB	354	PHY_LED0_LINK \| PHY_LED1_ACT \| PHY_LED2_INT))
8f2827fc VL	355	printf("Error writing PHY LED reg\n");
	356
	357	/* reset the phy */
	358	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
	359	}
52638c41 VL	360	#elif defined(CONFIG_KM_PIGGY4_88E6352)
	361
	362	#include <mv88e6352.h>
	363
	364	#if defined(CONFIG_KM_NUSA)
	365	struct mv88e_sw_reg extsw_conf[] = {
	366	/*
3765b3e7	367	* port 0, PIGGY4, autoneg
52638c41 VL	368	* first the fix for the 1000Mbits Autoneg, this is from
	369	* a Marvell errata, the regs are undocumented
	370	*/
	371	{ PHY(0), PHY_PAGE, AN1000FIX_PAGE },
	372	{ PHY(0), PHY_STATUS, AN1000FIX },
	373	{ PHY(0), PHY_PAGE, 0 },
	374	/* now the real port and phy configuration */
	375	{ PORT(0), PORT_PHY, NO_SPEED_FOR },
	376	{ PORT(0), PORT_CTRL, FORWARDING \| EGRS_FLD_ALL },
	377	{ PHY(0), PHY_1000_CTRL, NO_ADV },
	378	{ PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
	379	{ PHY(0), PHY_CTRL, PHY_100_MBPS \| AUTONEG_EN \| AUTONEG_RST \|
	380	FULL_DUPLEX },
	381	/* port 1, unused */
	382	{ PORT(1), PORT_CTRL, PORT_DIS },
	383	{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
	384	{ PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
	385	/* port 2, unused */
	386	{ PORT(2), PORT_CTRL, PORT_DIS },
	387	{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
	388	{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
	389	/* port 3, unused */
	390	{ PORT(3), PORT_CTRL, PORT_DIS },
	391	{ PHY(3), PHY_CTRL, PHY_PWR_DOWN },
	392	{ PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
	393	/* port 4, ICNEV, SerDes, SGMII */
	394	{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
	395	{ PORT(4), PORT_PHY, SPEED_1000_FOR },
	396	{ PORT(4), PORT_CTRL, FORWARDING \| EGRS_FLD_ALL },
	397	{ PHY(4), PHY_CTRL, PHY_PWR_DOWN },
	398	{ PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
	399	/* port 5, CPU_RGMII */
	400	{ PORT(5), PORT_PHY, RX_RGMII_TIM \| TX_RGMII_TIM \| FLOW_CTRL_EN \|
	401	FLOW_CTRL_FOR \| LINK_VAL \| LINK_FOR \| FULL_DPX \|
	402	FULL_DPX_FOR \| SPEED_1000_FOR },
	403	{ PORT(5), PORT_CTRL, FORWARDING \| EGRS_FLD_ALL },
	404	/* port 6, unused, this port has no phy */
	405	{ PORT(6), PORT_CTRL, PORT_DIS },
	406	};
	407	#else
	408	struct mv88e_sw_reg extsw_conf[] = {};
	409	#endif
	410
	411	void reset_phy(void)
	412	{
	413	#if defined(CONFIG_KM_MVEXTSW_ADDR)
	414	char *name = "egiga0";
	415
	416	if (miiphy_set_current_dev(name))
	417	return;
	418
	419	mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
	420	ARRAY_SIZE(extsw_conf));
	421	mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
	422	#endif
	423	}
	424
8f2827fc VL	425	#else
8f2827fc VL	426	/* Configure and enable MV88E1118 PHY on the piggy*/
67fa8c25 HS	427	void reset_phy(void)
67fa8c25 HS	428	{
9ff739e4 TM	429	unsigned int oui;
	430	unsigned char model, rev;
	431
67fa8c25 HS	432	char *name = "egiga0";
	433
	434	if (miiphy_set_current_dev(name))
	435	return;
	436
	437	/* reset the phy */
	438	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
9ff739e4 TM	439
	440	/* get PHY model */
	441	if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
	442	return;
	443
	444	/* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
	445	if ((oui == PHY_MARVELL_OUI) &&
	446	(model == PHY_MARVELL_88E1118R_MODEL)) {
	447	/* set page register to 3 */
	448	if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
	449	PHY_MARVELL_PAGE_REG,
	450	PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
	451	printf("Error writing PHY page reg\n");
	452
	453	/*
	454	* leds setup as printed on PCB:
	455	* LED2 (Link): 0x0 (On Link, Off No Link)
	456	* LED1 (Activity): 0x3 (On Activity, Off No Activity)
	457	* LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
	458	*/
	459	if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
	460	PHY_MARVELL_88E1118R_LED_CTRL_REG,
	461	PHY_MARVELL_88E1118R_LED_CTRL_RESERVED \|
	462	PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB \|
	463	PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT \|
	464	PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
	465	printf("Error writing PHY LED reg\n");
	466
	467	/* set page register back to 0 */
	468	if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
	469	PHY_MARVELL_PAGE_REG,
	470	PHY_MARVELL_DEFAULT_PAGE))
	471	printf("Error writing PHY page reg\n");
	472	}
67fa8c25	473	}
8f2827fc VL	474	#endif
8f2827fc VL	475
67fa8c25 HS	476
67fa8c25 HS	477	#if defined(CONFIG_HUSH_INIT_VAR)
b11f53f3	478	int hush_init_var(void)
67fa8c25	479	{
0bb95a68	480	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
67fa8c25 HS	481	return 0;
	482	}
	483	#endif
	484
ea818dbb	485	#if defined(CONFIG_SYS_I2C_SOFT)
b11f53f3	486	void set_sda(int state)
67fa8c25 HS	487	{
	488	I2C_ACTIVE;
	489	I2C_SDA(state);
	490	}
	491
b11f53f3	492	void set_scl(int state)
67fa8c25 HS	493	{
	494	I2C_SCL(state);
	495	}
	496
b11f53f3	497	int get_sda(void)
67fa8c25 HS	498	{
	499	I2C_TRISTATE;
	500	return I2C_READ;
	501	}
	502
b11f53f3	503	int get_scl(void)
67fa8c25	504	{
44097e26	505	return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
67fa8c25 HS	506	}
	507	#endif
	508
9400f8fa VL	509	#if defined(CONFIG_POST)
	510
	511	#define KM_POST_EN_L 44
	512	#define POST_WORD_OFF 8
	513
	514	int post_hotkeys_pressed(void)
	515	{
d9354530 HB	516	#if defined(CONFIG_KM_COGE5UN)
	517	return kw_gpio_get_value(KM_POST_EN_L);
	518	#else
9400f8fa	519	return !kw_gpio_get_value(KM_POST_EN_L);
d9354530	520	#endif
9400f8fa VL	521	}
	522
	523	ulong post_word_load(void)
	524	{
6a23f311	525	void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
9400f8fa VL	526	return in_le32(addr);
	527
	528	}
	529	void post_word_store(ulong value)
	530	{
6a23f311	531	void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
9400f8fa VL	532	out_le32(addr, value);
	533	}
	534
	535	int arch_memory_test_prepare(u32 vstart, u32 size, phys_addr_t *phys_offset)
	536	{
	537	*vstart = CONFIG_SYS_SDRAM_BASE;
	538
	539	/* we go up to relocation plus a 1 MB margin */
	540	*size = CONFIG_SYS_TEXT_BASE - (1<<20);
	541
	542	return 0;
	543	}
	544	#endif
	545
67fa8c25	546	#if defined(CONFIG_SYS_EEPROM_WREN)
b11f53f3	547	int eeprom_write_enable(unsigned dev_addr, int state)
67fa8c25	548	{
44097e26	549	kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
67fa8c25	550
44097e26	551	return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
67fa8c25 HS	552	}
67fa8c25 HS	553	#endif