[people/ms/u-boot.git] / board / keymile / mgcoge / mgcoge.c

/*
 * (C) Copyright 2007 - 2008
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8260.h>
#include <ioports.h>
#include <malloc.h>
#include <asm/io.h>

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif

#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
#endif

#include "../common/common.h"

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */
const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A */
    {	/*	      conf	ppar psor pdir podr pdat */
	/* PA31 */ { 0,		 0,   0,   0,	0,   0 }, /* PA31	     */
	/* PA30 */ { 0,		 0,   0,   0,	0,   0 }, /* PA30	     */
	/* PA29 */ { 0,		 0,   0,   0,	0,   0 }, /* PA29	     */
	/* PA28 */ { 0,		 0,   0,   0,	0,   0 }, /* PA28	     */
	/* PA27 */ { 0,		 0,   0,   0,	0,   0 }, /* PA27	     */
	/* PA26 */ { 0,		 0,   0,   0,	0,   0 }, /* PA26	     */
	/* PA25 */ { 0,		 0,   0,   0,	0,   0 }, /* PA25	     */
	/* PA24 */ { 0,		 0,   0,   0,	0,   0 }, /* PA24	     */
	/* PA23 */ { 0,		 0,   0,   0,	0,   0 }, /* PA23	     */
	/* PA22 */ { 0,		 0,   0,   0,	0,   0 }, /* PA22	     */
	/* PA21 */ { 0,		 0,   0,   0,	0,   0 }, /* PA21	     */
	/* PA20 */ { 0,		 0,   0,   0,	0,   0 }, /* PA20	     */
	/* PA19 */ { 0,		 0,   0,   0,	0,   0 }, /* PA19	     */
	/* PA18 */ { 0,		 0,   0,   0,	0,   0 }, /* PA18	     */
	/* PA17 */ { 0,		 0,   0,   0,	0,   0 }, /* PA17	     */
	/* PA16 */ { 0,		 0,   0,   0,	0,   0 }, /* PA16	     */
	/* PA15 */ { 0,		 0,   0,   0,	0,   0 }, /* PA15	     */
	/* PA14 */ { 0,		 0,   0,   0,	0,   0 }, /* PA14	     */
	/* PA13 */ { 0,		 0,   0,   0,	0,   0 }, /* PA13	     */
	/* PA12 */ { 0,		 0,   0,   0,	0,   0 }, /* PA12	     */
	/* PA11 */ { 0,		 0,   0,   0,	0,   0 }, /* PA11	     */
	/* PA10 */ { 0,		 0,   0,   0,	0,   0 }, /* PA10	     */
	/* PA9	*/ { 1,		 1,   0,   1,	0,   0 }, /* SMC2 TxD	     */
	/* PA8	*/ { 1,		 1,   0,   0,	0,   0 }, /* SMC2 RxD	     */
	/* PA7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA7	     */
	/* PA6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA6	     */
	/* PA5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA5	     */
	/* PA4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA4	     */
	/* PA3	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA3	     */
	/* PA2	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA2	     */
	/* PA1	*/ { 0,		 0,   0,   0,	0,   0 }, /* PA1	     */
	/* PA0	*/ { 0,		 0,   0,   0,	0,   0 }  /* PA0	     */
    },

    /* Port B */
    {	/*	      conf	ppar psor pdir podr pdat */
	/* PB31 */ { 0,		 0,   0,   0,	0,   0 }, /* PB31	     */
	/* PB30 */ { 0,		 0,   0,   0,	0,   0 }, /* PB30	     */
	/* PB29 */ { 0,		 0,   0,   0,	0,   0 }, /* PB29	     */
	/* PB28 */ { 0,		 0,   0,   0,	0,   0 }, /* PB28	     */
	/* PB27 */ { 0,		 0,   0,   0,	0,   0 }, /* PB27	     */
	/* PB26 */ { 0,		 0,   0,   0,	0,   0 }, /* PB26	     */
	/* PB25 */ { 0,		 0,   0,   0,	0,   0 }, /* PB25	     */
	/* PB24 */ { 0,		 0,   0,   0,	0,   0 }, /* PB24	     */
	/* PB23 */ { 0,		 0,   0,   0,	0,   0 }, /* PB23	     */
	/* PB22 */ { 0,		 0,   0,   0,	0,   0 }, /* PB22	     */
	/* PB21 */ { 0,		 0,   0,   0,	0,   0 }, /* PB21	     */
	/* PB20 */ { 0,		 0,   0,   0,	0,   0 }, /* PB20	     */
	/* PB19 */ { 0,		 0,   0,   0,	0,   0 }, /* PB19	     */
	/* PB18 */ { 0,		 0,   0,   0,	0,   0 }, /* PB18	     */
	/* PB17 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB16 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB15 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB14 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB13 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB12 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB11 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB10 */ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB9	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB8	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB7	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB6	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB5	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB4	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PB0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
    },

    /* Port C */
    {	/*	      conf	ppar psor pdir podr pdat */
	/* PC31 */ { 0,		 0,   0,   0,	0,   0 }, /* PC31	     */
	/* PC30 */ { 0,		 0,   0,   0,	0,   0 }, /* PC30	     */
	/* PC29 */ { 0,		 0,   0,   0,	0,   0 }, /* PC29	     */
	/* PC28 */ { 0,		 0,   0,   0,	0,   0 }, /* PC28	     */
	/* PC27 */ { 0,		 0,   0,   0,	0,   0 }, /* PC27	     */
	/* PC26 */ { 0,		 0,   0,   0,	0,   0 }, /* PC26	     */
	/* PC25 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC4 RxClk      */
	/* PC24 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC4 TxClk      */
	/* PC23 */ { 0,		 0,   0,   0,	0,   0 }, /* PC23	     */
	/* PC22 */ { 0,		 0,   0,   0,	0,   0 }, /* PC22	     */
	/* PC21 */ { 0,		 0,   0,   0,	0,   0 }, /* PC21	     */
	/* PC20 */ { 0,		 0,   0,   0,	0,   0 }, /* PC20	     */
	/* PC19 */ { 0,		 0,   0,   0,	0,   0 }, /* PC19	     */
	/* PC18 */ { 0,		 0,   0,   0,	0,   0 }, /* PC18	     */
	/* PC17 */ { 0,		 0,   0,   0,	0,   0 }, /* PC17	     */
	/* PC16 */ { 0,		 0,   0,   0,	0,   0 }, /* PC16	     */
	/* PC15 */ { 0,		 0,   0,   0,	0,   0 }, /* PC15	     */
	/* PC14 */ { 0,		 0,   0,   0,	0,   0 }, /* PC14	     */
	/* PC13 */ { 0,		 0,   0,   0,	0,   0 }, /* PC13	     */
	/* PC12 */ { 0,		 0,   0,   0,	0,   0 }, /* PC12	     */
	/* PC11 */ { 0,		 0,   0,   0,	0,   0 }, /* PC11	     */
	/* PC10 */ { 0,		 0,   0,   0,	0,   0 }, /* PC10	     */
	/* PC9	*/ { 1,		 1,   0,   0,	0,   0 }, /* SCC4: CTS	     */
	/* PC8	*/ { 1,		 1,   0,   0,	0,   0 }, /* SCC4: CD	     */
	/* PC7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC7	     */
	/* PC6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC6	     */
	/* PC5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC5	     */
	/* PC4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC4	     */
	/* PC3	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC3	     */
	/* PC2	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC2	     */
	/* PC1	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC1	     */
	/* PC0	*/ { 0,		 0,   0,   0,	0,   0 }, /* PC0	     */
    },

    /* Port D */
    {	/*	      conf	ppar psor pdir podr pdat */
	/* PD31 */ { 0,		 0,   0,   0,	0,   0 }, /* PD31	     */
	/* PD30 */ { 0,		 0,   0,   0,	0,   0 }, /* PD30	     */
	/* PD29 */ { 0,		 0,   0,   0,	0,   0 }, /* PD29	     */
	/* PD28 */ { 0,		 0,   0,   0,	0,   0 }, /* PD28	     */
	/* PD27 */ { 0,		 0,   0,   0,	0,   0 }, /* PD27	     */
	/* PD26 */ { 0,		 0,   0,   0,	0,   0 }, /* PD26	     */
	/* PD25 */ { 0,		 0,   0,   0,	0,   0 }, /* PD25	     */
	/* PD24 */ { 0,		 0,   0,   0,	0,   0 }, /* PD24	     */
	/* PD23 */ { 0,		 0,   0,   0,	0,   0 }, /* PD23	     */
	/* PD22 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC4: RXD	     */
	/* PD21 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC4: TXD	     */
	/* PD20 */ { 1,		 1,   0,   1,	0,   0 }, /* SCC4: RTS	     */
	/* PD19 */ { 0,		 0,   0,   0,	0,   0 }, /* PD19	     */
	/* PD18 */ { 0,		 0,   0,   0,	0,   0 }, /* PD18	     */
	/* PD17 */ { 0,		 0,   0,   0,	0,   0 }, /* PD17	     */
	/* PD16 */ { 0,		 0,   0,   0,	0,   0 }, /* PD16	     */
#if defined(CONFIG_HARD_I2C)
	/* PD15 */ { 1,		 1,   1,   0,	1,   0 }, /* I2C SDA	     */
	/* PD14 */ { 1,		 1,   1,   0,	1,   0 }, /* I2C SCL	     */
#else
	/* PD15 */ { 1,		 0,   0,   0,	1,   1 }, /* PD15	     */
	/* PD14 */ { 1,		 0,   0,   1,	1,   1 }, /* PD14	     */
#endif
	/* PD13 */ { 0,		 0,   0,   0,	0,   0 }, /* PD13	     */
	/* PD12 */ { 0,		 0,   0,   0,	0,   0 }, /* PD12	     */
	/* PD11 */ { 0,		 0,   0,   0,	0,   0 }, /* PD11	     */
	/* PD10 */ { 0,		 0,   0,   0,	0,   0 }, /* PD10	     */
	/* PD9	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD9	     */
	/* PD8	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD8	     */
	/* PD7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD7	     */
	/* PD6	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD6	     */
	/* PD5	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD5	     */
	/* PD4	*/ { 0,		 0,   0,   0,	0,   0 }, /* PD4	     */
	/* PD3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PD2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PD1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
	/* PD0	*/ { 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
    }
};

/*
 * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 *
 * This routine performs standard 8260 initialization sequence
 * and calculates the available memory size. It may be called
 * several times to try different SDRAM configurations on both
 * 60x and local buses.
 */
static long int try_init(memctl8260_t *memctl, ulong sdmr,
				  ulong orx, uchar *base)
{
	uchar c = 0xff;
	ulong maxsize, size;
	int i;

	/*
	 * We must be able to test a location outsize the maximum legal size
	 * to find out THAT we are outside; but this address still has to be
	 * mapped by the controller. That means, that the initial mapping has
	 * to be (at least) twice as large as the maximum expected size.
	 */
	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;

	out_be32(&memctl->memc_or1, orx);

	/*
	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	 *
	 * "At system reset, initialization software must set up the
	 *  programmable parameters in the memory controller banks registers
	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
	 *  system software should execute the following initialization sequence
	 *  for each SDRAM device.
	 *
	 *  1. Issue a PRECHARGE-ALL-BANKS command
	 *  2. Issue eight CBR REFRESH commands
	 *  3. Issue a MODE-SET command to initialize the mode register
	 *
	 *  The initial commands are executed by setting P/LSDMR[OP] and
	 *  accessing the SDRAM with a single-byte transaction."
	 *
	 * The appropriate BRx/ORx registers have already been set when we
	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
	 */

	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
	out_8(base, c);

	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
	for (i = 0; i < 8; i++)
		out_8(base, c);

	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
	/* setting MR on address lines */
	out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);

	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
	out_8(base, c);

	size = get_ram_size((long *)base, maxsize);
	out_be32(&memctl->memc_or1, orx | ~(size - 1));

	return (size);
}

phys_size_t initdram(int board_type)
{
	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	memctl8260_t *memctl = &immap->im_memctl;

	long psize;

	out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);

#ifndef CONFIG_SYS_RAMBOOT
	/* 60x SDRAM setup:
	 */
	psize = try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
				  (uchar *) CONFIG_SYS_SDRAM_BASE);
#endif /* CONFIG_SYS_RAMBOOT */

	icache_enable();

	return (psize);
}

int checkboard(void)
{
#if defined(CONFIG_MGCOGE)
	puts("Board: Keymile mgcoge");
#else
	puts("Board: Keymile mgcoge2ne");
#endif
	if (ethernet_present())
		puts(" with PIGGY.");
	puts("\n");
	return 0;
}

#define DIPSWITCH_OFFSET 0x89
#define DIPSWITCH_MASK   0x0f

int last_stage_init(void)
{
	u8 dip_switch;
	/* Dip switch */
	dip_switch = readb(CONFIG_SYS_BFTICU_BASE + DIPSWITCH_OFFSET);
	dip_switch &= DIPSWITCH_MASK;
	/* dip switch 'full reset' or 'db erase' */
	if (dip_switch & 0x1 || dip_switch & 0x2) {
		/* start bootloader */
		puts("DIP:   Enabled\n");
		setenv("actual_bank", "0");
	}
	return 0;
}

/*
 * Early board initalization.
 */
int board_early_init_r(void)
{
	struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE;

	/* setup the UPIOx */
	/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
	out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
	/* SCC4 enable, halfduplex, FCC1 powerdown */
	out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
		H_OPORTS_FCC1_PW_DWN));

	return 0;
}

int hush_init_var(void)
{
	ivm_read_eeprom();
	return 0;
}

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
Commit	Line	Data
ac9db066	1	/*
0809ea2f	2	* (C) Copyright 2007 - 2008
ac9db066 HS	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc8260.h>
	26	#include <ioports.h>
9661bf9d	27	#include <malloc.h>
9e299192	28	#include <asm/io.h>
ac9db066 HS	29
	30	#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
	31	#include <libfdt.h>
	32	#endif
	33
9661bf9d HS	34	#if defined(CONFIG_HARD_I2C) \|\| defined(CONFIG_SOFT_I2C)
	35	#include <i2c.h>
	36	#endif
	37
210c8c00 HS	38	#include "../common/common.h"
210c8c00 HS	39
ac9db066 HS	40	/*
	41	* I/O Port configuration table
	42	*
	43	* if conf is 1, then that port pin will be configured at boot time
	44	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	45	*/
	46	const iop_conf_t iop_conf_tab[4][32] = {
	47
	48	/* Port A */
3cbd8231 WD	49	{ /* conf ppar psor pdir podr pdat */
	50	/* PA31 / { 0, 0, 0, 0, 0, 0 }, / PA31 */
	51	/* PA30 / { 0, 0, 0, 0, 0, 0 }, / PA30 */
	52	/* PA29 / { 0, 0, 0, 0, 0, 0 }, / PA29 */
	53	/* PA28 / { 0, 0, 0, 0, 0, 0 }, / PA28 */
	54	/* PA27 / { 0, 0, 0, 0, 0, 0 }, / PA27 */
	55	/* PA26 / { 0, 0, 0, 0, 0, 0 }, / PA26 */
	56	/* PA25 / { 0, 0, 0, 0, 0, 0 }, / PA25 */
	57	/* PA24 / { 0, 0, 0, 0, 0, 0 }, / PA24 */
	58	/* PA23 / { 0, 0, 0, 0, 0, 0 }, / PA23 */
	59	/* PA22 / { 0, 0, 0, 0, 0, 0 }, / PA22 */
	60	/* PA21 / { 0, 0, 0, 0, 0, 0 }, / PA21 */
	61	/* PA20 / { 0, 0, 0, 0, 0, 0 }, / PA20 */
	62	/* PA19 / { 0, 0, 0, 0, 0, 0 }, / PA19 */
	63	/* PA18 / { 0, 0, 0, 0, 0, 0 }, / PA18 */
	64	/* PA17 / { 0, 0, 0, 0, 0, 0 }, / PA17 */
	65	/* PA16 / { 0, 0, 0, 0, 0, 0 }, / PA16 */
	66	/* PA15 / { 0, 0, 0, 0, 0, 0 }, / PA15 */
	67	/* PA14 / { 0, 0, 0, 0, 0, 0 }, / PA14 */
	68	/* PA13 / { 0, 0, 0, 0, 0, 0 }, / PA13 */
	69	/* PA12 / { 0, 0, 0, 0, 0, 0 }, / PA12 */
	70	/* PA11 / { 0, 0, 0, 0, 0, 0 }, / PA11 */
	71	/* PA10 / { 0, 0, 0, 0, 0, 0 }, / PA10 */
	72	/* PA9 / { 1, 1, 0, 1, 0, 0 }, / SMC2 TxD */
	73	/* PA8 / { 1, 1, 0, 0, 0, 0 }, / SMC2 RxD */
	74	/* PA7 / { 0, 0, 0, 0, 0, 0 }, / PA7 */
	75	/* PA6 / { 0, 0, 0, 0, 0, 0 }, / PA6 */
	76	/* PA5 / { 0, 0, 0, 0, 0, 0 }, / PA5 */
	77	/* PA4 / { 0, 0, 0, 0, 0, 0 }, / PA4 */
	78	/* PA3 / { 0, 0, 0, 0, 0, 0 }, / PA3 */
	79	/* PA2 / { 0, 0, 0, 0, 0, 0 }, / PA2 */
	80	/* PA1 / { 0, 0, 0, 0, 0, 0 }, / PA1 */
	81	/* PA0 / { 0, 0, 0, 0, 0, 0 } / PA0 */
ac9db066 HS	82	},
	83
	84	/* Port B */
3cbd8231 WD	85	{ /* conf ppar psor pdir podr pdat */
	86	/* PB31 / { 0, 0, 0, 0, 0, 0 }, / PB31 */
	87	/* PB30 / { 0, 0, 0, 0, 0, 0 }, / PB30 */
	88	/* PB29 / { 0, 0, 0, 0, 0, 0 }, / PB29 */
	89	/* PB28 / { 0, 0, 0, 0, 0, 0 }, / PB28 */
	90	/* PB27 / { 0, 0, 0, 0, 0, 0 }, / PB27 */
	91	/* PB26 / { 0, 0, 0, 0, 0, 0 }, / PB26 */
	92	/* PB25 / { 0, 0, 0, 0, 0, 0 }, / PB25 */
	93	/* PB24 / { 0, 0, 0, 0, 0, 0 }, / PB24 */
	94	/* PB23 / { 0, 0, 0, 0, 0, 0 }, / PB23 */
	95	/* PB22 / { 0, 0, 0, 0, 0, 0 }, / PB22 */
	96	/* PB21 / { 0, 0, 0, 0, 0, 0 }, / PB21 */
	97	/* PB20 / { 0, 0, 0, 0, 0, 0 }, / PB20 */
	98	/* PB19 / { 0, 0, 0, 0, 0, 0 }, / PB19 */
	99	/* PB18 / { 0, 0, 0, 0, 0, 0 }, / PB18 */
	100	/* PB17 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	101	/* PB16 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	102	/* PB15 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	103	/* PB14 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	104	/* PB13 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	105	/* PB12 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	106	/* PB11 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	107	/* PB10 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	108	/* PB9 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	109	/* PB8 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	110	/* PB7 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	111	/* PB6 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	112	/* PB5 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	113	/* PB4 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	114	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	115	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	116	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	117	/* PB0 / { 0, 0, 0, 0, 0, 0 } / non-existent */
ac9db066 HS	118	},
	119
	120	/* Port C */
3cbd8231 WD	121	{ /* conf ppar psor pdir podr pdat */
	122	/* PC31 / { 0, 0, 0, 0, 0, 0 }, / PC31 */
	123	/* PC30 / { 0, 0, 0, 0, 0, 0 }, / PC30 */
	124	/* PC29 / { 0, 0, 0, 0, 0, 0 }, / PC29 */
	125	/* PC28 / { 0, 0, 0, 0, 0, 0 }, / PC28 */
	126	/* PC27 / { 0, 0, 0, 0, 0, 0 }, / PC27 */
	127	/* PC26 / { 0, 0, 0, 0, 0, 0 }, / PC26 */
	128	/* PC25 / { 1, 1, 0, 0, 0, 0 }, / SCC4 RxClk */
	129	/* PC24 / { 1, 1, 0, 0, 0, 0 }, / SCC4 TxClk */
	130	/* PC23 / { 0, 0, 0, 0, 0, 0 }, / PC23 */
	131	/* PC22 / { 0, 0, 0, 0, 0, 0 }, / PC22 */
	132	/* PC21 / { 0, 0, 0, 0, 0, 0 }, / PC21 */
	133	/* PC20 / { 0, 0, 0, 0, 0, 0 }, / PC20 */
	134	/* PC19 / { 0, 0, 0, 0, 0, 0 }, / PC19 */
	135	/* PC18 / { 0, 0, 0, 0, 0, 0 }, / PC18 */
	136	/* PC17 / { 0, 0, 0, 0, 0, 0 }, / PC17 */
	137	/* PC16 / { 0, 0, 0, 0, 0, 0 }, / PC16 */
	138	/* PC15 / { 0, 0, 0, 0, 0, 0 }, / PC15 */
	139	/* PC14 / { 0, 0, 0, 0, 0, 0 }, / PC14 */
	140	/* PC13 / { 0, 0, 0, 0, 0, 0 }, / PC13 */
	141	/* PC12 / { 0, 0, 0, 0, 0, 0 }, / PC12 */
	142	/* PC11 / { 0, 0, 0, 0, 0, 0 }, / PC11 */
	143	/* PC10 / { 0, 0, 0, 0, 0, 0 }, / PC10 */
	144	/* PC9 / { 1, 1, 0, 0, 0, 0 }, / SCC4: CTS */
	145	/* PC8 / { 1, 1, 0, 0, 0, 0 }, / SCC4: CD */
	146	/* PC7 / { 0, 0, 0, 0, 0, 0 }, / PC7 */
	147	/* PC6 / { 0, 0, 0, 0, 0, 0 }, / PC6 */
	148	/* PC5 / { 0, 0, 0, 0, 0, 0 }, / PC5 */
	149	/* PC4 / { 0, 0, 0, 0, 0, 0 }, / PC4 */
	150	/* PC3 / { 0, 0, 0, 0, 0, 0 }, / PC3 */
	151	/* PC2 / { 0, 0, 0, 0, 0, 0 }, / PC2 */
	152	/* PC1 / { 0, 0, 0, 0, 0, 0 }, / PC1 */
	153	/* PC0 / { 0, 0, 0, 0, 0, 0 }, / PC0 */
ac9db066 HS	154	},
	155
	156	/* Port D */
3cbd8231 WD	157	{ /* conf ppar psor pdir podr pdat */
	158	/* PD31 / { 0, 0, 0, 0, 0, 0 }, / PD31 */
	159	/* PD30 / { 0, 0, 0, 0, 0, 0 }, / PD30 */
	160	/* PD29 / { 0, 0, 0, 0, 0, 0 }, / PD29 */
	161	/* PD28 / { 0, 0, 0, 0, 0, 0 }, / PD28 */
	162	/* PD27 / { 0, 0, 0, 0, 0, 0 }, / PD27 */
	163	/* PD26 / { 0, 0, 0, 0, 0, 0 }, / PD26 */
	164	/* PD25 / { 0, 0, 0, 0, 0, 0 }, / PD25 */
	165	/* PD24 / { 0, 0, 0, 0, 0, 0 }, / PD24 */
	166	/* PD23 / { 0, 0, 0, 0, 0, 0 }, / PD23 */
	167	/* PD22 / { 1, 1, 0, 0, 0, 0 }, / SCC4: RXD */
	168	/* PD21 / { 1, 1, 0, 1, 0, 0 }, / SCC4: TXD */
	169	/* PD20 / { 1, 1, 0, 1, 0, 0 }, / SCC4: RTS */
	170	/* PD19 / { 0, 0, 0, 0, 0, 0 }, / PD19 */
	171	/* PD18 / { 0, 0, 0, 0, 0, 0 }, / PD18 */
	172	/* PD17 / { 0, 0, 0, 0, 0, 0 }, / PD17 */
	173	/* PD16 / { 0, 0, 0, 0, 0, 0 }, / PD16 */
9661bf9d	174	#if defined(CONFIG_HARD_I2C)
3cbd8231 WD	175	/* PD15 / { 1, 1, 1, 0, 1, 0 }, / I2C SDA */
3cbd8231 WD	176	/* PD14 / { 1, 1, 1, 0, 1, 0 }, / I2C SCL */
9661bf9d	177	#else
3cbd8231 WD	178	/* PD15 / { 1, 0, 0, 0, 1, 1 }, / PD15 */
3cbd8231 WD	179	/* PD14 / { 1, 0, 0, 1, 1, 1 }, / PD14 */
9661bf9d	180	#endif
3cbd8231 WD	181	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
	182	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
	183	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
	184	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
	185	/* PD9 / { 0, 0, 0, 0, 0, 0 }, / PD9 */
	186	/* PD8 / { 0, 0, 0, 0, 0, 0 }, / PD8 */
	187	/* PD7 / { 0, 0, 0, 0, 0, 0 }, / PD7 */
	188	/* PD6 / { 0, 0, 0, 0, 0, 0 }, / PD6 */
	189	/* PD5 / { 0, 0, 0, 0, 0, 0 }, / PD5 */
	190	/* PD4 / { 0, 0, 0, 0, 0, 0 }, / PD4 */
	191	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	192	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	193	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / non-existent */
	194	/* PD0 / { 0, 0, 0, 0, 0, 0 } / non-existent */
ac9db066 HS	195	}
	196	};
	197
b11f53f3 HS	198	/*
b11f53f3 HS	199	* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
ac9db066 HS	200	*
	201	* This routine performs standard 8260 initialization sequence
	202	* and calculates the available memory size. It may be called
	203	* several times to try different SDRAM configurations on both
	204	* 60x and local buses.
	205	*/
b11f53f3 HS	206	static long int try_init(memctl8260_t *memctl, ulong sdmr,
b11f53f3 HS	207	ulong orx, uchar *base)
ac9db066	208	{
b11f53f3	209	uchar c = 0xff;
ac9db066 HS	210	ulong maxsize, size;
	211	int i;
	212
b11f53f3 HS	213	/*
b11f53f3 HS	214	* We must be able to test a location outsize the maximum legal size
ac9db066 HS	215	* to find out THAT we are outside; but this address still has to be
	216	* mapped by the controller. That means, that the initial mapping has
	217	* to be (at least) twice as large as the maximum expected size.
	218	*/
	219	maxsize = (1 + (~orx \| 0x7fff))/* / 2*/;
	220
b11f53f3	221	out_be32(&memctl->memc_or1, orx);
ac9db066 HS	222
	223	/*
	224	* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	225	*
	226	* "At system reset, initialization software must set up the
	227	* programmable parameters in the memory controller banks registers
	228	* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
	229	* system software should execute the following initialization sequence
	230	* for each SDRAM device.
	231	*
	232	* 1. Issue a PRECHARGE-ALL-BANKS command
	233	* 2. Issue eight CBR REFRESH commands
	234	* 3. Issue a MODE-SET command to initialize the mode register
	235	*
	236	* The initial commands are executed by setting P/LSDMR[OP] and
	237	* accessing the SDRAM with a single-byte transaction."
	238	*
	239	* The appropriate BRx/ORx registers have already been set when we
6d0f6bcf	240	* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
ac9db066 HS	241	*/
ac9db066 HS	242
b11f53f3 HS	243	out_be32(&memctl->memc_psdmr, sdmr \| PSDMR_OP_PREA);
b11f53f3 HS	244	out_8(base, c);
ac9db066	245
b11f53f3	246	out_be32(&memctl->memc_psdmr, sdmr \| PSDMR_OP_CBRR);
ac9db066	247	for (i = 0; i < 8; i++)
b11f53f3	248	out_8(base, c);
ac9db066	249
b11f53f3 HS	250	out_be32(&memctl->memc_psdmr, sdmr \| PSDMR_OP_MRW);
	251	/* setting MR on address lines */
	252	out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
ac9db066	253
b11f53f3 HS	254	out_be32(&memctl->memc_psdmr, sdmr \| PSDMR_OP_NORM \| PSDMR_RFEN);
b11f53f3 HS	255	out_8(base, c);
ac9db066	256
b11f53f3 HS	257	size = get_ram_size((long *)base, maxsize);
b11f53f3 HS	258	out_be32(&memctl->memc_or1, orx \| ~(size - 1));
ac9db066 HS	259
	260	return (size);
	261	}
	262
b11f53f3	263	phys_size_t initdram(int board_type)
ac9db066	264	{
b11f53f3 HS	265	immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
b11f53f3 HS	266	memctl8260_t *memctl = &immap->im_memctl;
ac9db066 HS	267
	268	long psize;
	269
b11f53f3 HS	270	out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
b11f53f3 HS	271	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
ac9db066	272
6d0f6bcf	273	#ifndef CONFIG_SYS_RAMBOOT
ac9db066 HS	274	/* 60x SDRAM setup:
ac9db066 HS	275	*/
b11f53f3 HS	276	psize = try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
b11f53f3 HS	277	(uchar *) CONFIG_SYS_SDRAM_BASE);
6d0f6bcf	278	#endif /* CONFIG_SYS_RAMBOOT */
ac9db066	279
b11f53f3	280	icache_enable();
ac9db066 HS	281
	282	return (psize);
	283	}
	284
	285	int checkboard(void)
	286	{
af895e45	287	#if defined(CONFIG_MGCOGE)
b11f53f3	288	puts("Board: Keymile mgcoge");
af895e45 HS	289	#else
	290	puts("Board: Keymile mgcoge2ne");
	291	#endif
b11f53f3 HS	292	if (ethernet_present())
	293	puts(" with PIGGY.");
	294	puts("\n");
ac9db066 HS	295	return 0;
	296	}
	297
91a3c14c AH	298	#define DIPSWITCH_OFFSET 0x89
	299	#define DIPSWITCH_MASK 0x0f
	300
	301	int last_stage_init(void)
	302	{
	303	u8 dip_switch;
	304	/* Dip switch */
	305	dip_switch = readb(CONFIG_SYS_BFTICU_BASE + DIPSWITCH_OFFSET);
	306	dip_switch &= DIPSWITCH_MASK;
	307	/* dip switch 'full reset' or 'db erase' */
	308	if (dip_switch & 0x1 \|\| dip_switch & 0x2) {
	309	/* start bootloader */
	310	puts("DIP: Enabled\n");
	311	setenv("actual_bank", "0");
	312	}
	313	return 0;
	314	}
	315
e492c90c HS	316	/*
	317	* Early board initalization.
	318	*/
b11f53f3	319	int board_early_init_r(void)
e492c90c	320	{
b11f53f3 HS	321	struct km_bec_fpga base = (struct km_bec_fpga )CONFIG_SYS_PIGGY_BASE;
b11f53f3 HS	322
e492c90c	323	/* setup the UPIOx */
4897ee33	324	/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
b11f53f3	325	out_8(&base->oprth, (WRG_RESET \| H_OPORTS_14 \| WRG_LED));
4897ee33	326	/* SCC4 enable, halfduplex, FCC1 powerdown */
b11f53f3 HS	327	out_8(&base->oprtl, (H_OPORTS_SCC4_ENA \| H_OPORTS_SCC4_FD_ENA \|
	328	H_OPORTS_FCC1_PW_DWN));
	329
e492c90c HS	330	return 0;
	331	}
	332
b11f53f3	333	int hush_init_var(void)
8f64da7f	334	{
b11f53f3	335	ivm_read_eeprom();
8f64da7f HS	336	return 0;
	337	}
	338
ac9db066	339	#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
b11f53f3	340	void ft_board_setup(void blob, bd_t bd)
ac9db066	341	{
b11f53f3	342	ft_cpu_setup(blob, bd);
ac9db066 HS	343	}
ac9db066 HS	344	#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */