[people/ms/u-boot.git] / board / kup / kup4x / kup4x.c

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8xx.h>
#include <post.h>
#include "../common/kup.h"
#ifdef CONFIG_KUP4K_LOGO
/* #include "s1d13706.h" */
#endif

#define KUP4X_USB


typedef struct {
	volatile unsigned char *VmemAddr;
	volatile unsigned char *RegAddr;
} FB_INFO_S1D13xxx;

/* ------------------------------------------------------------------------- */

int usb_init_kup4x (void);


#ifdef CONFIG_KUP4K_LOGO
void lcd_logo (bd_t * bd);
#endif

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
	0x1FF77C47,		/* last */

	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */

	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,	/* last */
	_NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 */
	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07,	/* last */
	_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x7FFFFC07,		/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_,
};

/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 */

int checkboard (void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile uchar *latch;
	uchar rev, mod;

	/*
	 * Init ChipSelect #4 (CAN + HW-Latch)
	 */
	memctl->memc_or4 = 0xFFFF8926;
	memctl->memc_br4 = 0x90000401;
	__asm__ ("eieio");
	latch = (volatile uchar *) 0x90000200;
	rev = (*latch & 0xF8) >> 3;
	mod = (*latch & 0x03);
	printf ("Board: KUP4X Rev %d.%d\n",rev,mod);
	return (0);
}

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size_b0 = 0;
	long int size_b1 = 0;
	long int size_b2 = 0;
	long int size_b3 = 0;

	upmconfig (UPMA, (uint *) sdram_table,
		   sizeof (sdram_table) / sizeof (uint));
	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
	 * preliminary addresses - these have to be modified after the
	 * SDRAM size has been determined.
	 */
/*	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;	*/
/*	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;	*/

/*	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;	*/
/*	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;	*/

	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
	udelay (1);
	memctl->memc_mcr = 0x80002830;	/* SDRAM bank 0 - execute twice */
	udelay (1);
	memctl->memc_mcr = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
	udelay (1);

	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
	udelay (1);
	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 1 - execute twice */
	udelay (1);
	memctl->memc_mcr = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
	udelay (1);

	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 2 */
	udelay (1);
	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 2 - execute twice */
	udelay (1);
	memctl->memc_mcr = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
	udelay (1);

	memctl->memc_mcr = 0x8000C105;	/* SDRAM bank 2 */
	udelay (1);
	memctl->memc_mcr = 0x8000C830;	/* SDRAM bank 2 - execute twice */
	udelay (1);
	memctl->memc_mcr = 0x8000C106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
	udelay (1);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
	udelay (1000);
#if 0				/* 4 x 8MB */
	size_b0 = 0x00800000;
	size_b1 = 0x00800000;
	size_b2 = 0x00800000;
	size_b3 = 0x00800000;
	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
	udelay (1000);
	memctl->memc_or1 = 0xFF800A00;
	memctl->memc_br1 = 0x00000081;
	memctl->memc_or2 = 0xFF000A00;
	memctl->memc_br2 = 0x00800081;
	memctl->memc_or3 = 0xFE000A00;
	memctl->memc_br3 = 0x01000081;
	memctl->memc_or6 = 0xFE000A00;
	memctl->memc_br6 = 0x01800081;
#else  /* 4 x 16 MB */
	size_b0 = 0x01000000;
	size_b1 = 0x01000000;
	size_b2 = 0x01000000;
	size_b3 = 0x01000000;
	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
	udelay (1000);
	memctl->memc_or1 = 0xFF000A00;
	memctl->memc_br1 = 0x00000081;
	memctl->memc_or2 = 0xFE000A00;
	memctl->memc_br2 = 0x01000081;
	memctl->memc_or3 = 0xFD000A00;
	memctl->memc_br3 = 0x02000081;
	memctl->memc_or6 = 0xFC000A00;
	memctl->memc_br6 = 0x03000081;
#endif
	udelay (10000);

	return (size_b0 + size_b1 + size_b2 + size_b3);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */
#if 0
static long int dram_size (long int mamr_value, long int *base,
			   long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile long int *addr;
	ulong cnt, val;
	ulong save[32];		/* to make test non-destructive */
	unsigned char i = 0;

	memctl->memc_mamr = mamr_value;

	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
		addr = base + cnt;	/* pointer arith! */

		save[i++] = *addr;
		*addr = ~cnt;
	}

	/* write 0 to base address */
	addr = base;
	save[i] = *addr;
	*addr = 0;

	/* check at base address */
	if ((val = *addr) != 0) {
		*addr = save[i];
		return (0);
	}

	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
		addr = base + cnt;	/* pointer arith! */

		val = *addr;
		*addr = save[--i];

		if (val != (~cnt)) {
			return (cnt * sizeof (long));
		}
	}
	return (maxsize);
}
#endif

int misc_init_r (void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;

#ifdef CONFIG_IDE_LED
	/* Configure PA8 as output port */
	immap->im_ioport.iop_padir |= 0x80;
	immap->im_ioport.iop_paodr |= 0x80;
	immap->im_ioport.iop_papar &= ~0x80;
	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
#endif
#ifdef KUP4X_USB
	usb_init_kup4x ();
#endif
	setenv ("hw", "4x");
	poweron_key ();
	return (0);
}
Commit	Line	Data
56f94be3	1	/*
0608e04d	2	* (C) Copyright 2000-2004
56f94be3 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <mpc8xx.h>
02b11f8e	27	#include <post.h>
0608e04d	28	#include "../common/kup.h"
56f94be3	29	#ifdef CONFIG_KUP4K_LOGO
0608e04d	30	/* #include "s1d13706.h" */
56f94be3 WD	31	#endif
56f94be3 WD	32
0608e04d	33	#define KUP4X_USB
56f94be3	34
0608e04d WD	35
	36	typedef struct {
	37	volatile unsigned char *VmemAddr;
	38	volatile unsigned char *RegAddr;
	39	} FB_INFO_S1D13xxx;
56f94be3 WD	40
	41	/* ------------------------------------------------------------------------- */
	42
0608e04d WD	43	int usb_init_kup4x (void);
0608e04d WD	44
56f94be3 WD	45
56f94be3 WD	46	#ifdef CONFIG_KUP4K_LOGO
0608e04d	47	void lcd_logo (bd_t * bd);
56f94be3 WD	48	#endif
	49
	50	/* ------------------------------------------------------------------------- */
	51
	52	#define _NOT_USED_ 0xFFFFFFFF
	53
0608e04d	54	const uint sdram_table[] = {
56f94be3 WD	55	/*
	56	* Single Read. (Offset 0 in UPMA RAM)
	57	*/
682011ff	58	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
0608e04d	59	0x1FF77C47, /* last */
56f94be3 WD	60
	61	/*
	62	* SDRAM Initialization (offset 5 in UPMA RAM)
	63	*
	64	* This is no UPM entry point. The following definition uses
	65	* the remaining space to establish an initialization
	66	* sequence, which is executed by a RUN command.
	67	*
	68	*/
0608e04d	69	0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
56f94be3 WD	70
	71	/*
	72	* Burst Read. (Offset 8 in UPMA RAM)
	73	*/
682011ff	74	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
0608e04d	75	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
56f94be3 WD	76	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	77	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	78
	79	/*
	80	* Single Write. (Offset 18 in UPMA RAM)
	81	*/
0608e04d	82	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
56f94be3 WD	83	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	84
	85	/*
	86	* Burst Write. (Offset 20 in UPMA RAM)
	87	*/
682011ff	88	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
0608e04d WD	89	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
0608e04d WD	90	_NOT_USED_,
56f94be3 WD	91	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	92	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	93
	94	/*
	95	* Refresh (Offset 30 in UPMA RAM)
	96	*/
682011ff	97	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0608e04d WD	98	0xFFFFFC84, 0xFFFFFC07, /* last */
0608e04d WD	99	_NOT_USED_, _NOT_USED_,
56f94be3 WD	100	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	101
	102	/*
	103	* Exception. (Offset 3c in UPMA RAM)
	104	*/
0608e04d WD	105	0x7FFFFC07, /* last */
0608e04d WD	106	_NOT_USED_, _NOT_USED_, _NOT_USED_,
56f94be3 WD	107	};
	108
	109	/* ------------------------------------------------------------------------- */
	110
56f94be3 WD	111	/*
	112	* Check Board Identity:
	113	*/
	114
	115	int checkboard (void)
	116	{
6d0f6bcf	117	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
0608e04d	118	volatile memctl8xx_t *memctl = &immap->im_memctl;
2729af9d WD	119	volatile uchar *latch;
2729af9d WD	120	uchar rev, mod;
56f94be3	121
0608e04d WD	122	/*
	123	* Init ChipSelect #4 (CAN + HW-Latch)
	124	*/
	125	memctl->memc_or4 = 0xFFFF8926;
	126	memctl->memc_br4 = 0x90000401;
02b11f8e	127	__asm__ ("eieio");
2729af9d	128	latch = (volatile uchar *) 0x90000200;
0608e04d WD	129	rev = (*latch & 0xF8) >> 3;
0608e04d WD	130	mod = (*latch & 0x03);
02b11f8e	131	printf ("Board: KUP4X Rev %d.%d\n",rev,mod);
56f94be3 WD	132	return (0);
	133	}
	134
	135	/* ------------------------------------------------------------------------- */
	136
9973e3c6	137	phys_size_t initdram (int board_type)
56f94be3	138	{
6d0f6bcf	139	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
682011ff WD	140	volatile memctl8xx_t *memctl = &immap->im_memctl;
	141	long int size_b0 = 0;
	142	long int size_b1 = 0;
	143	long int size_b2 = 0;
0608e04d	144	long int size_b3 = 0;
56f94be3	145
682011ff	146	upmconfig (UPMA, (uint *) sdram_table,
0608e04d	147	sizeof (sdram_table) / sizeof (uint));
682011ff WD	148	/*
	149	* Preliminary prescaler for refresh (depends on number of
	150	* banks): This value is selected for four cycles every 62.4 us
	151	* with two SDRAM banks or four cycles every 31.2 us with one
	152	* bank. It will be adjusted after memory sizing.
	153	*/
6d0f6bcf	154	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
56f94be3	155
682011ff	156	memctl->memc_mar = 0x00000088;
56f94be3	157
682011ff WD	158	/*
	159	* Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
	160	* preliminary addresses - these have to be modified after the
	161	* SDRAM size has been determined.
	162	*/
6d0f6bcf JCPV	163	/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */
6d0f6bcf JCPV	164	/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */
682011ff	165
6d0f6bcf JCPV	166	/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */
6d0f6bcf JCPV	167	/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */
56f94be3	168
6d0f6bcf	169	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
56f94be3	170
682011ff	171	udelay (200);
56f94be3	172
682011ff	173	/* perform SDRAM initializsation sequence */
56f94be3	174
682011ff WD	175	memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
	176	udelay (1);
	177	memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
	178	udelay (1);
	179	memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
	180	udelay (1);
56f94be3	181
682011ff WD	182	memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
	183	udelay (1);
	184	memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
	185	udelay (1);
	186	memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
	187	udelay (1);
56f94be3	188
682011ff WD	189	memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
	190	udelay (1);
	191	memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
	192	udelay (1);
	193	memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
	194	udelay (1);
56f94be3	195
0608e04d WD	196	memctl->memc_mcr = 0x8000C105; /* SDRAM bank 2 */
	197	udelay (1);
	198	memctl->memc_mcr = 0x8000C830; /* SDRAM bank 2 - execute twice */
	199	udelay (1);
	200	memctl->memc_mcr = 0x8000C106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
	201	udelay (1);
	202
682011ff WD	203	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
682011ff WD	204	udelay (1000);
0608e04d	205	#if 0 /* 4 x 8MB */
682011ff WD	206	size_b0 = 0x00800000;
	207	size_b1 = 0x00800000;
	208	size_b2 = 0x00800000;
0608e04d	209	size_b3 = 0x00800000;
6d0f6bcf	210	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
682011ff	211	udelay (1000);
56f94be3 WD	212	memctl->memc_or1 = 0xFF800A00;
56f94be3 WD	213	memctl->memc_br1 = 0x00000081;
682011ff WD	214	memctl->memc_or2 = 0xFF000A00;
682011ff WD	215	memctl->memc_br2 = 0x00800081;
56f94be3 WD	216	memctl->memc_or3 = 0xFE000A00;
56f94be3 WD	217	memctl->memc_br3 = 0x01000081;
0608e04d WD	218	memctl->memc_or6 = 0xFE000A00;
	219	memctl->memc_br6 = 0x01800081;
	220	#else /* 4 x 16 MB */
682011ff WD	221	size_b0 = 0x01000000;
	222	size_b1 = 0x01000000;
	223	size_b2 = 0x01000000;
0608e04d	224	size_b3 = 0x01000000;
6d0f6bcf	225	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
682011ff WD	226	udelay (1000);
	227	memctl->memc_or1 = 0xFF000A00;
	228	memctl->memc_br1 = 0x00000081;
	229	memctl->memc_or2 = 0xFE000A00;
	230	memctl->memc_br2 = 0x01000081;
0608e04d	231	memctl->memc_or3 = 0xFD000A00;
682011ff	232	memctl->memc_br3 = 0x02000081;
0608e04d WD	233	memctl->memc_or6 = 0xFC000A00;
0608e04d WD	234	memctl->memc_br6 = 0x03000081;
682011ff	235	#endif
682011ff	236	udelay (10000);
56f94be3	237
0608e04d	238	return (size_b0 + size_b1 + size_b2 + size_b3);
56f94be3 WD	239	}
	240
	241	/* ------------------------------------------------------------------------- */
	242
	243	/*
	244	* Check memory range for valid RAM. A simple memory test determines
	245	* the actually available RAM size between addresses `base' and
	246	* `base + maxsize'. Some (not all) hardware errors are detected:
	247	* - short between address lines
	248	* - short between data lines
	249	*/
	250	#if 0
682011ff	251	static long int dram_size (long int mamr_value, long int *base,
0608e04d	252	long int maxsize)
56f94be3	253	{
6d0f6bcf	254	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
682011ff	255	volatile memctl8xx_t *memctl = &immap->im_memctl;
0608e04d WD	256	volatile long int *addr;
	257	ulong cnt, val;
	258	ulong save[32]; /* to make test non-destructive */
	259	unsigned char i = 0;
56f94be3	260
682011ff	261	memctl->memc_mamr = mamr_value;
56f94be3	262
0608e04d WD	263	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
	264	addr = base + cnt; /* pointer arith! */
	265
	266	save[i++] = *addr;
	267	*addr = ~cnt;
	268	}
	269
	270	/* write 0 to base address */
	271	addr = base;
	272	save[i] = *addr;
	273	*addr = 0;
	274
	275	/* check at base address */
	276	if ((val = *addr) != 0) {
	277	*addr = save[i];
	278	return (0);
	279	}
	280
	281	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
	282	addr = base + cnt; /* pointer arith! */
	283
	284	val = *addr;
	285	*addr = save[--i];
	286
	287	if (val != (~cnt)) {
	288	return (cnt * sizeof (long));
	289	}
	290	}
	291	return (maxsize);
56f94be3 WD	292	}
	293	#endif
	294
	295	int misc_init_r (void)
	296	{
6d0f6bcf	297	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
56f94be3	298
1f53a416 WD	299	#ifdef CONFIG_IDE_LED
	300	/* Configure PA8 as output port */
	301	immap->im_ioport.iop_padir \|= 0x80;
	302	immap->im_ioport.iop_paodr \|= 0x80;
	303	immap->im_ioport.iop_papar &= ~0x80;
682011ff	304	immap->im_ioport.iop_padat \|= 0x80; /* turn it off */
1f53a416	305	#endif
0608e04d WD	306	#ifdef KUP4X_USB
0608e04d WD	307	usb_init_kup4x ();
56f94be3	308	#endif
0608e04d WD	309	setenv ("hw", "4x");
	310	poweron_key ();
	311	return (0);
1f53a416	312	}