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Commit | Line | Data |
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04386f65 SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #include <asm-offsets.h> | |
11 | #include <ppc_asm.tmpl> | |
12 | #include <config.h> | |
13 | #include <asm/mmu.h> | |
14 | ||
15 | /************************************************************************** | |
16 | * TLB TABLE | |
17 | * | |
18 | * This table is used by the cpu boot code to setup the initial tlb | |
19 | * entries. Rather than make broad assumptions in the cpu source tree, | |
20 | * this table lets each board set things up however they like. | |
21 | * | |
22 | * Pointer to the table is returned in r1 | |
23 | * | |
24 | *************************************************************************/ | |
25 | .section .bootpg,"ax" | |
26 | .globl tlbtab | |
27 | ||
28 | tlbtab: | |
29 | tlbtab_start | |
30 | ||
31 | /* | |
32 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
33 | * speed up boot process. It is patched after relocation to enable SA_I | |
34 | */ | |
35 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G) | |
36 | ||
37 | /* | |
38 | * TLB entries for SDRAM are not needed on this platform. | |
39 | * They are dynamically generated in the SPD DDR(2) detection | |
40 | * routine. | |
41 | */ | |
42 | ||
43 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE | |
44 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ | |
45 | tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) | |
46 | #endif | |
47 | ||
48 | /* TLB-entry for PCI Memory */ | |
49 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG) | |
50 | tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG) | |
51 | tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG) | |
52 | tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG) | |
53 | ||
54 | /* TLB-entry for the FPGA Chip select 2 */ | |
55 | tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G) | |
56 | ||
57 | /* TLB-entry for the FPGA Chip select 3 */ | |
58 | tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G) | |
59 | ||
60 | /* TLB-entry for the LIME Controller */ | |
61 | tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G) | |
62 | tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G) | |
63 | tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G) | |
64 | tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G) | |
65 | ||
66 | /* TLB-entry for Internal Registers & OCM */ | |
67 | tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I) | |
68 | ||
69 | /*TLB-entry PCI registers*/ | |
70 | tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG) | |
71 | ||
72 | /* TLB-entry for peripherals */ | |
73 | tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) | |
74 | ||
75 | tlbtab_end |