[people/ms/u-boot.git] / board / logicpd / omap3som / omap3logic.c

/*
 * (C) Copyright 2011
 * Logic Product Development <www.logicpd.com>
 *
 * Author :
 *	Peter Barada <peter.barada@logicpd.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <dm.h>
#include <ns16550.h>
#include <netdev.h>
#include <flash.h>
#include <nand.h>
#include <i2c.h>
#include <twl4030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <linux/mtd/rawnand.h>
#include <asm/omap_musb.h>
#include <linux/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
#include "omap3logic.h"
#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/* This is only needed until SPL gets OF support */
#ifdef CONFIG_SPL_BUILD
static const struct ns16550_platdata omap3logic_serial = {
	.base = OMAP34XX_UART1,
	.reg_shift = 2,
	.clock = V_NS16550_CLK,
	.fcr = UART_FCR_DEFVAL,
};

U_BOOT_DEVICE(omap3logic_uart) = {
	"ns16550_serial",
	&omap3logic_serial
};
#endif

/*
 * two dimensional array of strucures containining board name and Linux
 * machine IDs; row it selected based on CPU column is slected based
 * on hsusb0_data5 pin having a pulldown resistor
 */
static struct board_id {
	char *name;
	int machine_id;
	char *fdtfile;
} boards[2][2] = {
	{
		{
			.name		= "OMAP35xx SOM LV",
			.machine_id	= MACH_TYPE_OMAP3530_LV_SOM,
			.fdtfile	= "logicpd-som-lv-35xx-devkit.dtb",
		},
		{
			.name		= "OMAP35xx Torpedo",
			.machine_id	= MACH_TYPE_OMAP3_TORPEDO,
			.fdtfile	= "logicpd-torpedo-35xx-devkit.dtb",
		},
	},
	{
		{
			.name		= "DM37xx SOM LV",
			.fdtfile	= "logicpd-som-lv-37xx-devkit.dtb",
		},
		{
			.name		= "DM37xx Torpedo",
			.fdtfile	= "logicpd-torpedo-37xx-devkit.dtb",
		},
	},
};

#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
	/* break into full u-boot on 'c' */
	return serial_tstc() && serial_getc() == 'c';
}
#endif

#if defined(CONFIG_SPL_BUILD)
/*
 * Routine: get_board_mem_timings
 * Description: If we use SPL then there is no x-loader nor config header
 * so we have to setup the DDR timings ourself on the first bank.  This
 * provides the timing values back to the function that configures
 * the memory.
 */
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
	timings->mr = MICRON_V_MR_165;
	/* 256MB DDR */
	timings->mcfg = MICRON_V_MCFG_200(256 << 20);
	timings->ctrla = MICRON_V_ACTIMA_200;
	timings->ctrlb = MICRON_V_ACTIMB_200;
	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
}

#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)

void spl_board_prepare_for_linux(void)
{
	/* The Micron NAND starts locked which
	 * prohibits mounting the NAND as RW
	 * The following commands are what unlocks
	 * the NAND to become RW Falcon Mode does not
	 * have as many smarts as U-Boot, but Logic PD
	 * only makes NAND with 512MB so these hard coded
	 * values should work for all current models
	 */

	writeb(0x70, GPMC_NAND_COMMAND_0);
	writeb(-1, GPMC_NAND_DATA_0);
	writeb(0x7a, GPMC_NAND_COMMAND_0);
	writeb(0x00, GPMC_NAND_ADDRESS_0);
	writeb(0x00, GPMC_NAND_ADDRESS_0);
	writeb(0x00, GPMC_NAND_ADDRESS_0);
	writeb(-1, GPMC_NAND_COMMAND_0);

	/* Begin address 0 */
	writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
	writeb(0x00, GPMC_NAND_ADDRESS_0);
	writeb(0x00, GPMC_NAND_ADDRESS_0);
	writeb(0x00, GPMC_NAND_ADDRESS_0);
	writeb(-1, GPMC_NAND_DATA_0);

	/* Ending address at the end of Flash */
	writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
	writeb(0xc0, GPMC_NAND_ADDRESS_0);
	writeb(0xff, GPMC_NAND_ADDRESS_0);
	writeb(0x03, GPMC_NAND_ADDRESS_0);
	writeb(-1, GPMC_NAND_DATA_0);
	writeb(0x79, GPMC_NAND_COMMAND_0);
	writeb(-1, GPMC_NAND_DATA_0);
	writeb(-1, GPMC_NAND_DATA_0);
}
#endif

#ifdef CONFIG_USB_MUSB_OMAP2PLUS
static struct musb_hdrc_config musb_config = {
	.multipoint     = 1,
	.dyn_fifo       = 1,
	.num_eps        = 16,
	.ram_bits       = 12,
};

static struct omap_musb_board_data musb_board_data = {
	.interface_type	= MUSB_INTERFACE_ULPI,
};

static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_HOST)
	.mode           = MUSB_HOST,
#elif defined(CONFIG_USB_MUSB_GADGET)
	.mode		= MUSB_PERIPHERAL,
#else
#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
#endif
	.config         = &musb_config,
	.power          = 100,
	.platform_ops	= &omap2430_ops,
	.board_data	= &musb_board_data,
};
#endif

#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
{
	if (val == BOOTSTAGE_ID_RUN_OS)
		usb_stop();
}

static struct omap_usbhs_board_data usbhs_bdata = {
	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
};

int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}

int ehci_hcd_stop(int index)
{
	return omap_ehci_hcd_stop();
}

#endif /* CONFIG_USB_EHCI_HCD */


/*
 * Routine: misc_init_r
 * Description: Configure board specific parts
 */
int misc_init_r(void)
{
	twl4030_power_init();
	omap_die_id_display();

#ifdef CONFIG_USB_MUSB_OMAP2PLUS
	musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
#endif

	return 0;
}

/*
 * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
 */
#define BOARD_ID_GPIO	189 /* hsusb0_data5 pin */

/*
 * Routine: board_init
 * Description: Early hardware init.
 */
int board_init(void)
{
	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */

	/* boot param addr */
	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT

static void unlock_nand(void)
{
	int dev = nand_curr_device;
	struct mtd_info *mtd;

	mtd = get_nand_dev_by_index(dev);
	nand_unlock(mtd, 0, mtd->size, 0);
}

int board_late_init(void)
{
	struct board_id *board;
	unsigned int val;

	/*
	 * To identify between a SOM LV and Torpedo module,
	 * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
	 * Drive the pin (and let it soak), then read it back.
	 * If the pin is still high its a Torpedo.  If low its a SOM LV
	 */

	/* Mux hsusb0_data5 as a GPIO */
	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M4));

	if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {

		/*
		 * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
		 * will drain the voltage.
		 */
		gpio_direction_output(BOARD_ID_GPIO, 0);
		gpio_set_value(BOARD_ID_GPIO, 1);

		/* Let it soak for a bit */
		sdelay(0x100);

		/*
		 * Read state of BOARD_ID_GPIO as an input and if its set.
		 * If so the board is a Torpedo
		 */
		gpio_direction_input(BOARD_ID_GPIO);
		val = gpio_get_value(BOARD_ID_GPIO);
		gpio_free(BOARD_ID_GPIO);

		board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
		printf("Board: %s\n", board->name);

		/* Set the machine_id passed to Linux */
		if (board->machine_id)
			gd->bd->bi_arch_number = board->machine_id;

		/* If the user has not set fdtimage, set the default */
		if (!env_get("fdtimage"))
			env_set("fdtimage", board->fdtfile);
	}

	/* restore hsusb0_data5 pin as hsusb0_data5 */
	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0));

#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
	unlock_nand();
#endif
	return 0;
}
#endif

#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
	return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif

#if defined(CONFIG_MMC)
void board_mmc_power_init(void)
{
	twl4030_power_mmc_init(0);
}
#endif

#ifdef CONFIG_SMC911X
/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
static const u32 gpmc_lan92xx_config[] = {
	NET_LAN92XX_GPMC_CONFIG1,
	NET_LAN92XX_GPMC_CONFIG2,
	NET_LAN92XX_GPMC_CONFIG3,
	NET_LAN92XX_GPMC_CONFIG4,
	NET_LAN92XX_GPMC_CONFIG5,
	NET_LAN92XX_GPMC_CONFIG6,
};

int board_eth_init(bd_t *bis)
{
	enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);

	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
}
#endif
Commit	Line	Data
86887f8e PB	1	/*
	2	* (C) Copyright 2011
	3	* Logic Product Development <www.logicpd.com>
	4	*
	5	* Author :
	6	* Peter Barada <peter.barada@logicpd.com>
	7	*
	8	* Derived from Beagle Board and 3430 SDP code by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <khasim@ti.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
86887f8e PB	13	*/
86887f8e PB	14	#include <common.h>
7b77b1f6 AF	15	#include <dm.h>
7b77b1f6 AF	16	#include <ns16550.h>
86887f8e PB	17	#include <netdev.h>
	18	#include <flash.h>
	19	#include <nand.h>
	20	#include <i2c.h>
	21	#include <twl4030.h>
	22	#include <asm/io.h>
	23	#include <asm/arch/mmc_host_def.h>
	24	#include <asm/arch/mux.h>
	25	#include <asm/arch/mem.h>
	26	#include <asm/arch/sys_proto.h>
	27	#include <asm/gpio.h>
	28	#include <asm/mach-types.h>
6ae3900a	29	#include <linux/mtd/rawnand.h>
588e41d2	30	#include <asm/omap_musb.h>
1221ce45	31	#include <linux/errno.h>
588e41d2 AF	32	#include <linux/usb/ch9.h>
	33	#include <linux/usb/gadget.h>
	34	#include <linux/usb/musb.h>
86887f8e	35	#include "omap3logic.h"
74cd48e1 AF	36	#ifdef CONFIG_USB_EHCI_HCD
	37	#include <usb.h>
	38	#include <asm/ehci-omap.h>
	39	#endif
86887f8e PB	40
	41	DECLARE_GLOBAL_DATA_PTR;
	42
15fde737 AF	43	/* This is only needed until SPL gets OF support */
15fde737 AF	44	#ifdef CONFIG_SPL_BUILD
7b77b1f6	45	static const struct ns16550_platdata omap3logic_serial = {
2f6ed3b8 AF	46	.base = OMAP34XX_UART1,
2f6ed3b8 AF	47	.reg_shift = 2,
17fa0326 HS	48	.clock = V_NS16550_CLK,
17fa0326 HS	49	.fcr = UART_FCR_DEFVAL,
7b77b1f6 AF	50	};
	51
	52	U_BOOT_DEVICE(omap3logic_uart) = {
c7b9686d	53	"ns16550_serial",
7b77b1f6 AF	54	&omap3logic_serial
7b77b1f6 AF	55	};
15fde737	56	#endif
7b77b1f6	57
15fde737 AF	58	/*
	59	* two dimensional array of strucures containining board name and Linux
	60	* machine IDs; row it selected based on CPU column is slected based
	61	* on hsusb0_data5 pin having a pulldown resistor
	62	*/
86887f8e PB	63	static struct board_id {
	64	char *name;
	65	int machine_id;
c63d270d	66	char *fdtfile;
86887f8e PB	67	} boards[2][2] = {
	68	{
	69	{
	70	.name = "OMAP35xx SOM LV",
	71	.machine_id = MACH_TYPE_OMAP3530_LV_SOM,
c63d270d	72	.fdtfile = "logicpd-som-lv-35xx-devkit.dtb",
86887f8e PB	73	},
	74	{
	75	.name = "OMAP35xx Torpedo",
	76	.machine_id = MACH_TYPE_OMAP3_TORPEDO,
c63d270d	77	.fdtfile = "logicpd-torpedo-35xx-devkit.dtb",
86887f8e PB	78	},
	79	},
	80	{
	81	{
	82	.name = "DM37xx SOM LV",
c63d270d	83	.fdtfile = "logicpd-som-lv-37xx-devkit.dtb",
86887f8e PB	84	},
	85	{
	86	.name = "DM37xx Torpedo",
c63d270d	87	.fdtfile = "logicpd-torpedo-37xx-devkit.dtb",
86887f8e PB	88	},
	89	},
	90	};
	91
49c7303f AF	92	#ifdef CONFIG_SPL_OS_BOOT
	93	int spl_start_uboot(void)
	94	{
	95	/* break into full u-boot on 'c' */
	96	return serial_tstc() && serial_getc() == 'c';
	97	}
	98	#endif
	99
	100	#if defined(CONFIG_SPL_BUILD)
	101	/*
	102	* Routine: get_board_mem_timings
	103	* Description: If we use SPL then there is no x-loader nor config header
	104	* so we have to setup the DDR timings ourself on the first bank. This
	105	* provides the timing values back to the function that configures
	106	* the memory.
	107	*/
	108	void get_board_mem_timings(struct board_sdrc_timings *timings)
	109	{
	110	timings->mr = MICRON_V_MR_165;
	111	/* 256MB DDR */
	112	timings->mcfg = MICRON_V_MCFG_200(256 << 20);
	113	timings->ctrla = MICRON_V_ACTIMA_200;
	114	timings->ctrlb = MICRON_V_ACTIMB_200;
	115	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
	116	}
6032c029 AF	117
	118	#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
	119	#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
	120	#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
	121
	122	void spl_board_prepare_for_linux(void)
	123	{
	124	/* The Micron NAND starts locked which
	125	* prohibits mounting the NAND as RW
	126	* The following commands are what unlocks
	127	* the NAND to become RW Falcon Mode does not
	128	* have as many smarts as U-Boot, but Logic PD
	129	* only makes NAND with 512MB so these hard coded
	130	* values should work for all current models
	131	*/
	132
	133	writeb(0x70, GPMC_NAND_COMMAND_0);
	134	writeb(-1, GPMC_NAND_DATA_0);
	135	writeb(0x7a, GPMC_NAND_COMMAND_0);
	136	writeb(0x00, GPMC_NAND_ADDRESS_0);
	137	writeb(0x00, GPMC_NAND_ADDRESS_0);
	138	writeb(0x00, GPMC_NAND_ADDRESS_0);
	139	writeb(-1, GPMC_NAND_COMMAND_0);
	140
	141	/* Begin address 0 */
	142	writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
	143	writeb(0x00, GPMC_NAND_ADDRESS_0);
	144	writeb(0x00, GPMC_NAND_ADDRESS_0);
	145	writeb(0x00, GPMC_NAND_ADDRESS_0);
	146	writeb(-1, GPMC_NAND_DATA_0);
	147
	148	/* Ending address at the end of Flash */
	149	writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
	150	writeb(0xc0, GPMC_NAND_ADDRESS_0);
	151	writeb(0xff, GPMC_NAND_ADDRESS_0);
	152	writeb(0x03, GPMC_NAND_ADDRESS_0);
	153	writeb(-1, GPMC_NAND_DATA_0);
	154	writeb(0x79, GPMC_NAND_COMMAND_0);
	155	writeb(-1, GPMC_NAND_DATA_0);
	156	writeb(-1, GPMC_NAND_DATA_0);
	157	}
49c7303f AF	158	#endif
49c7303f AF	159
588e41d2 AF	160	#ifdef CONFIG_USB_MUSB_OMAP2PLUS
	161	static struct musb_hdrc_config musb_config = {
	162	.multipoint = 1,
	163	.dyn_fifo = 1,
	164	.num_eps = 16,
	165	.ram_bits = 12,
	166	};
	167
	168	static struct omap_musb_board_data musb_board_data = {
	169	.interface_type = MUSB_INTERFACE_ULPI,
	170	};
	171
	172	static struct musb_hdrc_platform_data musb_plat = {
	173	#if defined(CONFIG_USB_MUSB_HOST)
	174	.mode = MUSB_HOST,
	175	#elif defined(CONFIG_USB_MUSB_GADGET)
	176	.mode = MUSB_PERIPHERAL,
	177	#else
	178	#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
	179	#endif
	180	.config = &musb_config,
	181	.power = 100,
	182	.platform_ops = &omap2430_ops,
	183	.board_data = &musb_board_data,
	184	};
	185	#endif
	186
74cd48e1 AF	187	#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
	188	/* Call usb_stop() before starting the kernel */
	189	void show_boot_progress(int val)
	190	{
	191	if (val == BOOTSTAGE_ID_RUN_OS)
	192	usb_stop();
	193	}
	194
	195	static struct omap_usbhs_board_data usbhs_bdata = {
	196	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
	197	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
	198	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
	199	};
	200
	201	int ehci_hcd_init(int index, enum usb_init_type init,
	202	struct ehci_hccr hccr, struct ehci_hcor hcor)
	203	{
	204	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
	205	}
	206
	207	int ehci_hcd_stop(int index)
	208	{
	209	return omap_ehci_hcd_stop();
	210	}
	211
	212	#endif /* CONFIG_USB_EHCI_HCD */
	213
588e41d2	214
49c7303f AF	215	/*
	216	* Routine: misc_init_r
	217	* Description: Configure board specific parts
	218	*/
	219	int misc_init_r(void)
	220	{
49c7303f	221	twl4030_power_init();
49c7303f	222	omap_die_id_display();
49c7303f	223
588e41d2 AF	224	#ifdef CONFIG_USB_MUSB_OMAP2PLUS
	225	musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
	226	#endif
	227
49c7303f AF	228	return 0;
	229	}
	230
86887f8e PB	231	/*
	232	* BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
	233	*/
	234	#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
	235
	236	/*
	237	* Routine: board_init
	238	* Description: Early hardware init.
	239	*/
	240	int board_init(void)
	241	{
86887f8e PB	242	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
	243
	244	/* boot param addr */
	245	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
	246
c63d270d TR	247	return 0;
	248	}
	249
	250	#ifdef CONFIG_BOARD_LATE_INIT
157af4f8 AF	251
	252	static void unlock_nand(void)
	253	{
	254	int dev = nand_curr_device;
	255	struct mtd_info *mtd;
	256
	257	mtd = get_nand_dev_by_index(dev);
	258	nand_unlock(mtd, 0, mtd->size, 0);
	259	}
	260
c63d270d TR	261	int board_late_init(void)
	262	{
	263	struct board_id *board;
	264	unsigned int val;
	265
86887f8e PB	266	/*
	267	* To identify between a SOM LV and Torpedo module,
	268	* a pulldown resistor is on hsusb0_data5 for the SOM LV module.
	269	* Drive the pin (and let it soak), then read it back.
	270	* If the pin is still high its a Torpedo. If low its a SOM LV
	271	*/
	272
	273	/* Mux hsusb0_data5 as a GPIO */
	274	MUX_VAL(CP(HSUSB0_DATA5), (IEN \| PTD \| DIS \| M4));
	275
	276	if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
	277
	278	/*
	279	* Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
	280	* will drain the voltage.
	281	*/
	282	gpio_direction_output(BOARD_ID_GPIO, 0);
	283	gpio_set_value(BOARD_ID_GPIO, 1);
	284
	285	/* Let it soak for a bit */
	286	sdelay(0x100);
	287
	288	/*
	289	* Read state of BOARD_ID_GPIO as an input and if its set.
	290	* If so the board is a Torpedo
	291	*/
	292	gpio_direction_input(BOARD_ID_GPIO);
	293	val = gpio_get_value(BOARD_ID_GPIO);
	294	gpio_free(BOARD_ID_GPIO);
	295
	296	board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
	297	printf("Board: %s\n", board->name);
	298
	299	/* Set the machine_id passed to Linux */
c63d270d TR	300	if (board->machine_id)
	301	gd->bd->bi_arch_number = board->machine_id;
	302
	303	/* If the user has not set fdtimage, set the default */
00caae6d	304	if (!env_get("fdtimage"))
382bee57	305	env_set("fdtimage", board->fdtfile);
86887f8e PB	306	}
	307
	308	/* restore hsusb0_data5 pin as hsusb0_data5 */
	309	MUX_VAL(CP(HSUSB0_DATA5), (IEN \| PTD \| DIS \| M0));
157af4f8 AF	310
	311	#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
	312	unlock_nand();
	313	#endif
26ef7a27 AF	314	return 0;
	315	}
	316	#endif
	317
4aa2ba3a	318	#if defined(CONFIG_MMC)
86887f8e PB	319	int board_mmc_init(bd_t *bis)
86887f8e PB	320	{
e3913f56	321	return omap_mmc_init(0, 0, 0, -1, -1);
86887f8e PB	322	}
	323	#endif
	324
4aa2ba3a	325	#if defined(CONFIG_MMC)
aac5450e PK	326	void board_mmc_power_init(void)
	327	{
	328	twl4030_power_mmc_init(0);
	329	}
	330	#endif
	331
86887f8e PB	332	#ifdef CONFIG_SMC911X
	333	/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
	334	static const u32 gpmc_lan92xx_config[] = {
	335	NET_LAN92XX_GPMC_CONFIG1,
	336	NET_LAN92XX_GPMC_CONFIG2,
	337	NET_LAN92XX_GPMC_CONFIG3,
	338	NET_LAN92XX_GPMC_CONFIG4,
	339	NET_LAN92XX_GPMC_CONFIG5,
	340	NET_LAN92XX_GPMC_CONFIG6,
	341	};
	342
	343	int board_eth_init(bd_t *bis)
	344	{
	345	enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
	346	CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
	347
	348	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
	349	}
	350	#endif
	351
86887f8e	352