[people/ms/u-boot.git] / board / logodl / memsetup.S

/*
 * Most of this taken from Redboot hal_platform_setup.h with cleanup
 *
 * NOTE: I haven't clean this up considerably, just enough to get it
 * running. See hal_platform_setup.h for the source. See
 * board/cradle/memsetup.S for another PXA250 setup that is
 * much cleaner.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>

DRAM_SIZE:  .long   CFG_DRAM_SIZE

/* wait for coprocessor write complete */
   .macro CPWAIT reg
   mrc  p15,0,\reg,c2,c0,0
   mov  \reg,\reg
   sub  pc,pc,#4
   .endm

_TEXT_BASE:
	.word	TEXT_BASE


/*
 * 	Memory setup
 */

.globl memsetup
memsetup:

    mov      r10, lr

	/* Set up GPIO pins first ----------------------------------------- */

	ldr		r0,	=GPSR0
	ldr		r1,	=CFG_GPSR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPSR1
	ldr		r1,	=CFG_GPSR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPSR2
	ldr		r1,	=CFG_GPSR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR0
	ldr		r1,	=CFG_GPCR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR1
	ldr		r1,	=CFG_GPCR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR2
	ldr		r1,	=CFG_GPCR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR0
	ldr		r1,	=CFG_GPDR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR1
	ldr		r1,	=CFG_GPDR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR2
	ldr		r1,	=CFG_GPDR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR0_L
	ldr		r1,	=CFG_GAFR0_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR0_U
	ldr		r1,	=CFG_GAFR0_U_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR1_L
	ldr		r1,	=CFG_GAFR1_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR1_U
	ldr		r1,	=CFG_GAFR1_U_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR2_L
	ldr		r1,	=CFG_GAFR2_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR2_U
	ldr		r1,	=CFG_GAFR2_U_VAL
	str		r1,   [r0]

	ldr	r0,	=PSSR		/* enable GPIO pins */
	ldr		r1,	=CFG_PSSR_VAL
	str		r1,   [r0]

/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
/*	ldr	r2,	=CFG_MSC1_VAL	/  high - bank 3 Ethernet Controller */
/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
/* */
/*	ldr	r1,	=LED_BLANK */
/*	mov	r0,	#0xFF */
/*	str	r0,	[r1]		/  turn on hex leds */
/* */
/*loop: */
/* */
/*   ldr	r0, =0xB0070001 */
/*   ldr    	r1, =_LED */
/*   str    	r0, [r1]		/  hex display */


	/* ---------------------------------------------------------------- */
	/* Enable memory interface                                          */
	/*                                                                  */
	/* The sequence below is based on the recommended init steps        */
	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	/* Chapter 10.                                                      */
	/* ---------------------------------------------------------------- */

	/* ---------------------------------------------------------------- */
	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
	/*         clocks to settle. Only necessary after hard reset...     */
	/*         FIXME: can be optimized later                            */
	/* ---------------------------------------------------------------- */

	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
	mov r2, #0
	str r2, [r3]
	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
					/* so 0x300 should be plenty        */
1:
	ldr r2, [r3]
	cmp r4, r2
	bgt 1b

mem_init:

	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */

	/* ---------------------------------------------------------------- */
	/* Step 2a: Initialize Asynchronous static memory controller        */
	/* ---------------------------------------------------------------- */

	/* MSC registers: timing, bus width, mem type                       */

	/* MSC0: nCS(0,1)                                                   */
	ldr     r2,   =CFG_MSC0_VAL
	str     r2,   [r1, #MSC0_OFFSET]
	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
						/* that data latches        */
	/* MSC1: nCS(2,3)                                                   */
	ldr     r2,  =CFG_MSC1_VAL
	str     r2,  [r1, #MSC1_OFFSET]
	ldr     r2,  [r1, #MSC1_OFFSET]

	/* MSC2: nCS(4,5)                                                   */
	ldr     r2,  =CFG_MSC2_VAL
	str     r2,  [r1, #MSC2_OFFSET]
	ldr     r2,  [r1, #MSC2_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2b: Initialize Card Interface                               */
	/* ---------------------------------------------------------------- */

	/* MECR: Memory Expansion Card Register                             */
	ldr     r2,  =CFG_MECR_VAL
	str     r2,  [r1, #MECR_OFFSET]
	ldr	r2,	[r1, #MECR_OFFSET]

	/* MCMEM0: Card Interface slot 0 timing                             */
	ldr     r2,  =CFG_MCMEM0_VAL
	str     r2,  [r1, #MCMEM0_OFFSET]
	ldr	r2,	[r1, #MCMEM0_OFFSET]

	/* MCMEM1: Card Interface slot 1 timing                             */
	ldr     r2,  =CFG_MCMEM1_VAL
	str     r2,  [r1, #MCMEM1_OFFSET]
	ldr	r2,	[r1, #MCMEM1_OFFSET]

	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
	ldr     r2,  =CFG_MCATT0_VAL
	str     r2,  [r1, #MCATT0_OFFSET]
	ldr	r2,	[r1, #MCATT0_OFFSET]

	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
	ldr     r2,  =CFG_MCATT1_VAL
	str     r2,  [r1, #MCATT1_OFFSET]
	ldr	r2,	[r1, #MCATT1_OFFSET]

	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
	ldr     r2,  =CFG_MCIO0_VAL
	str     r2,  [r1, #MCIO0_OFFSET]
	ldr	r2,	[r1, #MCIO0_OFFSET]

	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
	ldr     r2,  =CFG_MCIO1_VAL
	str     r2,  [r1, #MCIO1_OFFSET]
	ldr	r2,	[r1, #MCIO1_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
	/* ---------------------------------------------------------------- */

	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
	adr	r3, mem_init		/* r0 <- current position of code   */
	ldr	r2, =mem_init
	cmp	r3, r2			/* skip init if in place            */
	beq	initirqs


	/* ---------------------------------------------------------------- */
	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
	/* ---------------------------------------------------------------- */

	/* Before accessing MDREFR we need a valid DRI field, so we set     */
	/* this to power on defaults + DRI field.                           */

	ldr 	r3, 	=CFG_MDREFR_VAL
	ldr	r2,	=0xFFF
	and	r3,	r3, r2
	ldr	r4,	=0x03ca4000
	orr	r4,	r4,  r3

	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
	ldr     r4,	[r1, #MDREFR_OFFSET]


	/* ---------------------------------------------------------------- */
	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	/* ---------------------------------------------------------------- */

	/* Initialize SXCNFG register. Assert the enable bits               */

	/* Write SXMRS to cause an MRS command to all enabled banks of      */
	/* synchronous static memory. Note that SXLCR need not be written   */
	/* at this time.                                                    */

	/* FIXME: we use async mode for now                                 */


	/* ---------------------------------------------------------------- */
	/* Step 4: Initialize SDRAM                                         */
	/* ---------------------------------------------------------------- */

	/* Step 4a: assert MDREFR:K?RUN and configure                       */
	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */

	ldr	r4,	=CFG_MDREFR_VAL
	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
	ldr	r4,	[r1, #MDREFR_OFFSET]

	/* Step 4b: de-assert MDREFR:SLFRSH.                                */

	bic	r4,	r4, #(MDREFR_SLFRSH)

	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r4,     [r1, #MDREFR_OFFSET]


	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */

	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)

	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r4,     [r1, #MDREFR_OFFSET]


	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
	/*          configure but not enable each SDRAM partition pair.     */

	ldr	r4,	=CFG_MDCNFG_VAL
	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)

	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
	ldr     r4,     [r1, #MDCNFG_OFFSET]


	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
Commit	Line	Data
52f52c14 WD	1	/*
	2	* Most of this taken from Redboot hal_platform_setup.h with cleanup
	3	*
	4	* NOTE: I haven't clean this up considerably, just enough to get it
	5	* running. See hal_platform_setup.h for the source. See
	6	* board/cradle/memsetup.S for another PXA250 setup that is
	7	* much cleaner.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <config.h>
	29	#include <version.h>
	30	#include <asm/arch/pxa-regs.h>
	31
	32	DRAM_SIZE: .long CFG_DRAM_SIZE
	33
	34	/* wait for coprocessor write complete */
	35	.macro CPWAIT reg
	36	mrc p15,0,\reg,c2,c0,0
	37	mov \reg,\reg
	38	sub pc,pc,#4
	39	.endm
	40
	41	_TEXT_BASE:
	42	.word TEXT_BASE
	43
	44
	45	/*
	46	* Memory setup
	47	*/
	48
	49	.globl memsetup
	50	memsetup:
	51
	52	mov r10, lr
	53
	54	/* Set up GPIO pins first ----------------------------------------- */
	55
	56	ldr r0, =GPSR0
	57	ldr r1, =CFG_GPSR0_VAL
	58	str r1, [r0]
	59
	60	ldr r0, =GPSR1
	61	ldr r1, =CFG_GPSR1_VAL
	62	str r1, [r0]
	63
	64	ldr r0, =GPSR2
65	ldr r1, =CFG_GPSR2_VAL
66	str r1, [r0]
67
68	ldr r0, =GPCR0
69	ldr r1, =CFG_GPCR0_VAL
70	str r1, [r0]
71
72	ldr r0, =GPCR1
73	ldr r1, =CFG_GPCR1_VAL
74	str r1, [r0]
75
76	ldr r0, =GPCR2
77	ldr r1, =CFG_GPCR2_VAL
78	str r1, [r0]
79
80	ldr r0, =GPDR0
81	ldr r1, =CFG_GPDR0_VAL
82	str r1, [r0]
83
84	ldr r0, =GPDR1
85	ldr r1, =CFG_GPDR1_VAL
86	str r1, [r0]
87
88	ldr r0, =GPDR2
89	ldr r1, =CFG_GPDR2_VAL
90	str r1, [r0]
91
92	ldr r0, =GAFR0_L
93	ldr r1, =CFG_GAFR0_L_VAL
94	str r1, [r0]
95
96	ldr r0, =GAFR0_U
97	ldr r1, =CFG_GAFR0_U_VAL
98	str r1, [r0]
99
100	ldr r0, =GAFR1_L
101	ldr r1, =CFG_GAFR1_L_VAL
102	str r1, [r0]
103
104	ldr r0, =GAFR1_U
105	ldr r1, =CFG_GAFR1_U_VAL
106	str r1, [r0]
107
108	ldr r0, =GAFR2_L
109	ldr r1, =CFG_GAFR2_L_VAL
110	str r1, [r0]
111
112	ldr r0, =GAFR2_U
113	ldr r1, =CFG_GAFR2_U_VAL
114	str r1, [r0]
115
116	ldr r0, =PSSR /* enable GPIO pins */
117	ldr r1, =CFG_PSSR_VAL
118	str r1, [r0]
119
120	/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
121	/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
122	/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
123	/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
124	/* */
125	/* ldr r1, =LED_BLANK */
126	/* mov r0, #0xFF */
127	/* str r0, [r1] / turn on hex leds */
128	/* */
129	/loop: /
130	/* */
131	/* ldr r0, =0xB0070001 */
132	/* ldr r1, =_LED */
133	/* str r0, [r1] / hex display */
134
135
136	/* ---------------------------------------------------------------- */
137	/* Enable memory interface */
138	/* */
139	/* The sequence below is based on the recommended init steps */
140	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
141	/* Chapter 10. */
142	/* ---------------------------------------------------------------- */
143
144	/* ---------------------------------------------------------------- */
145	/* Step 1: Wait for at least 200 microsedonds to allow internal */
146	/* clocks to settle. Only necessary after hard reset... */
147	/* FIXME: can be optimized later */
148	/* ---------------------------------------------------------------- */
149
150	ldr r3, =OSCR /* reset the OS Timer Count to zero */
151	mov r2, #0
152	str r2, [r3]
153	ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
154	/* so 0x300 should be plenty */
155	1:
156	ldr r2, [r3]
157	cmp r4, r2
158	bgt 1b
159
160	mem_init:
161
8bde7f77	162	ldr r1, =MEMC_BASE /* get memory controller base addr. */
52f52c14 WD	163
	164	/* ---------------------------------------------------------------- */
	165	/* Step 2a: Initialize Asynchronous static memory controller */
	166	/* ---------------------------------------------------------------- */
	167
	168	/* MSC registers: timing, bus width, mem type */
	169
8bde7f77 WD	170	/* MSC0: nCS(0,1) */
	171	ldr r2, =CFG_MSC0_VAL
	172	str r2, [r1, #MSC0_OFFSET]
	173	ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
52f52c14	174	/* that data latches */
8bde7f77 WD	175	/* MSC1: nCS(2,3) */
	176	ldr r2, =CFG_MSC1_VAL
	177	str r2, [r1, #MSC1_OFFSET]
	178	ldr r2, [r1, #MSC1_OFFSET]
52f52c14 WD	179
52f52c14 WD	180	/* MSC2: nCS(4,5) */
8bde7f77 WD	181	ldr r2, =CFG_MSC2_VAL
	182	str r2, [r1, #MSC2_OFFSET]
	183	ldr r2, [r1, #MSC2_OFFSET]
52f52c14 WD	184
	185	/* ---------------------------------------------------------------- */
	186	/* Step 2b: Initialize Card Interface */
	187	/* ---------------------------------------------------------------- */
	188
	189	/* MECR: Memory Expansion Card Register */
8bde7f77 WD	190	ldr r2, =CFG_MECR_VAL
8bde7f77 WD	191	str r2, [r1, #MECR_OFFSET]
52f52c14 WD	192	ldr r2, [r1, #MECR_OFFSET]
	193
	194	/* MCMEM0: Card Interface slot 0 timing */
8bde7f77 WD	195	ldr r2, =CFG_MCMEM0_VAL
8bde7f77 WD	196	str r2, [r1, #MCMEM0_OFFSET]
52f52c14 WD	197	ldr r2, [r1, #MCMEM0_OFFSET]
52f52c14 WD	198
8bde7f77 WD	199	/* MCMEM1: Card Interface slot 1 timing */
	200	ldr r2, =CFG_MCMEM1_VAL
	201	str r2, [r1, #MCMEM1_OFFSET]
52f52c14 WD	202	ldr r2, [r1, #MCMEM1_OFFSET]
	203
	204	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
8bde7f77 WD	205	ldr r2, =CFG_MCATT0_VAL
8bde7f77 WD	206	str r2, [r1, #MCATT0_OFFSET]
52f52c14 WD	207	ldr r2, [r1, #MCATT0_OFFSET]
	208
	209	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
8bde7f77 WD	210	ldr r2, =CFG_MCATT1_VAL
8bde7f77 WD	211	str r2, [r1, #MCATT1_OFFSET]
52f52c14 WD	212	ldr r2, [r1, #MCATT1_OFFSET]
	213
	214	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
8bde7f77 WD	215	ldr r2, =CFG_MCIO0_VAL
8bde7f77 WD	216	str r2, [r1, #MCIO0_OFFSET]
52f52c14 WD	217	ldr r2, [r1, #MCIO0_OFFSET]
	218
	219	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
8bde7f77 WD	220	ldr r2, =CFG_MCIO1_VAL
8bde7f77 WD	221	str r2, [r1, #MCIO1_OFFSET]
52f52c14 WD	222	ldr r2, [r1, #MCIO1_OFFSET]
	223
	224	/* ---------------------------------------------------------------- */
8bde7f77 WD	225	/* Step 2c: Write FLYCNFG FIXME: what's that??? */
8bde7f77 WD	226	/* ---------------------------------------------------------------- */
52f52c14	227
8bde7f77	228	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
52f52c14 WD	229	adr r3, mem_init /* r0 <- current position of code */
	230	ldr r2, =mem_init
	231	cmp r3, r2 /* skip init if in place */
	232	beq initirqs
	233
	234
	235	/* ---------------------------------------------------------------- */
8bde7f77 WD	236	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
8bde7f77 WD	237	/* ---------------------------------------------------------------- */
52f52c14 WD	238
	239	/* Before accessing MDREFR we need a valid DRI field, so we set */
	240	/* this to power on defaults + DRI field. */
	241
	242	ldr r3, =CFG_MDREFR_VAL
	243	ldr r2, =0xFFF
	244	and r3, r3, r2
	245	ldr r4, =0x03ca4000
	246	orr r4, r4, r3
	247
	248	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
8bde7f77	249	ldr r4, [r1, #MDREFR_OFFSET]
52f52c14 WD	250
	251
	252	/* ---------------------------------------------------------------- */
	253	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	254	/* ---------------------------------------------------------------- */
	255
	256	/* Initialize SXCNFG register. Assert the enable bits */
	257
	258	/* Write SXMRS to cause an MRS command to all enabled banks of */
	259	/* synchronous static memory. Note that SXLCR need not be written */
	260	/* at this time. */
	261
	262	/* FIXME: we use async mode for now */
	263
	264
8bde7f77 WD	265	/* ---------------------------------------------------------------- */
	266	/* Step 4: Initialize SDRAM */
	267	/* ---------------------------------------------------------------- */
52f52c14 WD	268
	269	/* Step 4a: assert MDREFR:K?RUN and configure */
	270	/* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
	271
	272	ldr r4, =CFG_MDREFR_VAL
	273	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	274	ldr r4, [r1, #MDREFR_OFFSET]
	275
	276	/* Step 4b: de-assert MDREFR:SLFRSH. */
	277
	278	bic r4, r4, #(MDREFR_SLFRSH)
	279
8bde7f77 WD	280	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
8bde7f77 WD	281	ldr r4, [r1, #MDREFR_OFFSET]
52f52c14 WD	282
	283
	284	/* Step 4c: assert MDREFR:E1PIN and E0PIO */
	285
	286	orr r4, r4, #(MDREFR_E1PIN\|MDREFR_E0PIN)
	287
8bde7f77 WD	288	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
8bde7f77 WD	289	ldr r4, [r1, #MDREFR_OFFSET]
52f52c14 WD	290
	291
	292	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
	293	/* configure but not enable each SDRAM partition pair. */
	294
	295	ldr r4, =CFG_MDCNFG_VAL
	296	bic r4, r4, #(MDCNFG_DE0\|MDCNFG_DE1)
	297
8bde7f77 WD	298	str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
8bde7f77 WD	299	ldr r4, [r1, #MDCNFG_OFFSET]
52f52c14 WD	300
	301
	302	/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
	303