[people/ms/u-boot.git] / board / lwmon / lwmon.c

/***********************************************************************
 *
M* Modul:         lwmon.c
M*
M* Content:       LWMON specific U-Boot commands.
 *
 * (C) Copyright 2001, 2002
 * DENX Software Engineering
 * Wolfgang Denk, wd@denx.de
 * All rights reserved.
 *
D* Design:        wd@denx.de
C* Coding:        wd@denx.de
V* Verification:  dzu@denx.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 ***********************************************************************/

/*---------------------------- Headerfiles ----------------------------*/
#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <i2c.h>
#include <command.h>
#include <malloc.h>
#include <post.h>
#include <serial.h>

#include <linux/types.h>
#include <linux/string.h>	/* for strdup */

DECLARE_GLOBAL_DATA_PTR;

/*------------------------ Local prototypes ---------------------------*/
static long int dram_size (long int, long int *, long int);
static void kbd_init (void);
static int compare_magic (uchar *kbd_data, uchar *str);


/*--------------------- Local macros and constants --------------------*/
#define	_NOT_USED_	0xFFFFFFFF

#ifdef CONFIG_MODEM_SUPPORT
static int key_pressed(void);
extern void disable_putc(void);
#endif /* CONFIG_MODEM_SUPPORT */

/*
 * 66 MHz SDRAM access using UPM A
 */
const uint sdram_table[] =
{
#if defined(CONFIG_SYS_MEMORY_75) || defined(CONFIG_SYS_MEMORY_8E)
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	0x1FF5FC47, /* last */
	/*
	 * SDRAM Initialization (offset 5 in UPM RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7FFFFC07, /* last */
		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
#endif
#ifdef CONFIG_SYS_MEMORY_7E
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
	_NOT_USED_,
	/*
	 * SDRAM Initialization (offset 5 in UPM RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
	0xE1BAFC04, 0x1FF5FC47, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7FFFFC07, /* last */
		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
#endif
};

/*
 * Check Board Identity:
 *
 */

/***********************************************************************
F* Function:     int checkboard (void) P*A*Z*
 *
P* Parameters:   none
P*
P* Returnvalue:  int - 0 is always returned
 *
Z* Intention:    This function is the checkboard() method implementation
Z*               for the lwmon board.  Only a standard message is printed.
 *
D* Design:       wd@denx.de
C* Coding:       wd@denx.de
V* Verification: dzu@denx.de
 ***********************************************************************/
int checkboard (void)
{
	puts ("Board: LICCON Konsole LCD3\n");
	return (0);
}

/***********************************************************************
F* Function:     phys_size_t initdram (int board_type) P*A*Z*
 *
P* Parameters:   int board_type
P*                - Usually type of the board - ignored here.
P*
P* Returnvalue:  long int
P*                - Size of initialized memory
 *
Z* Intention:    This function is the initdram() method implementation
Z*               for the lwmon board.
Z*               The memory controller is initialized to access the
Z*               DRAM.
 *
D* Design:       wd@denx.de
C* Coding:       wd@denx.de
V* Verification: dzu@denx.de
 ***********************************************************************/
phys_size_t initdram (int board_type)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;
	long int size_b0;
	long int size8, size9;
	int i;

	/*
	 * Configure UPMA for SDRAM
	 */
	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));

	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

	/* burst length=4, burst type=sequential, CAS latency=2 */
	memctl->memc_mar = CONFIG_SYS_MAR;

	/*
	 * Map controller bank 3 to the SDRAM bank at preliminary address.
	 */
	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;

	/* initialize memory address register */
	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* refresh not enabled yet */

	/* mode initialization (offset 5) */
	udelay (200);				/* 0x80006105 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);

	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
	udelay (1);				/* 0x80006130 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
	udelay (1);				/* 0x80006130 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);

	udelay (1);				/* 0x80006106 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);

	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */

	udelay (200);

	/* Need at least 10 DRAM accesses to stabilize */
	for (i = 0; i < 10; ++i) {
		volatile unsigned long *addr =
			(volatile unsigned long *) SDRAM_BASE3_PRELIM;
		unsigned long val;

		val = *(addr + i);
		*(addr + i) = val;
	}

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	if (size8 < size9) {		/* leave configuration at 9 columns */
		size_b0 = size9;
		memctl->memc_mamr = CONFIG_SYS_MAMR_9COL | MAMR_PTAE;
		udelay (500);
	} else {			/* back to 8 columns            */
		size_b0 = size8;
		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
		udelay (500);
	}

	/*
	 * Final mapping:
	 */

	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |
			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
	udelay (1000);

	return (size_b0);
}

/***********************************************************************
F* Function:     static long int dram_size (long int mamr_value,
F*                                          long int *base,
F*                                          long int maxsize) P*A*Z*
 *
P* Parameters:   long int mamr_value
P*                - Value for MAMR for the test
P*               long int *base
P*                - Base address for the test
P*               long int maxsize
P*                - Maximum size to test for
P*
P* Returnvalue:  long int
P*                - Size of probed memory
 *
Z* Intention:    Check memory range for valid RAM. A simple memory test
Z*               determines the actually available RAM size between
Z*               addresses `base' and `base + maxsize'. Some (not all)
Z*               hardware errors are detected:
Z*                - short between address lines
Z*                - short between data lines
 *
D* Design:       wd@denx.de
C* Coding:       wd@denx.de
V* Verification: dzu@denx.de
 ***********************************************************************/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size(base, maxsize));
}

/* ------------------------------------------------------------------------- */

#ifndef	PB_ENET_TENA
# define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
#endif

/***********************************************************************
F* Function:     int board_early_init_f (void) P*A*Z*
 *
P* Parameters:   none
P*
P* Returnvalue:  int
P*                - 0 is always returned.
 *
Z* Intention:    This function is the board_early_init_f() method implementation
Z*               for the lwmon board.
Z*               Disable Ethernet TENA on Port B.
 *
D* Design:       wd@denx.de
C* Coding:       wd@denx.de
V* Verification: dzu@denx.de
 ***********************************************************************/
int board_early_init_f (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	/* Disable Ethernet TENA on Port B
	 * Necessary because of pull up in COM3 port.
	 *
	 * This is just a preliminary fix, intended to turn off TENA
	 * as soon as possible to avoid noise on the network. Once
Commit	Line	Data
e2211743 WD	1	/***********************************************************************
	2	*
	3	M* Modul: lwmon.c
	4	M*
	5	M* Content: LWMON specific U-Boot commands.
	6	*
	7	* (C) Copyright 2001, 2002
	8	* DENX Software Engineering
	9	* Wolfgang Denk, wd@denx.de
	10	* All rights reserved.
	11	*
	12	D* Design: wd@denx.de
	13	C* Coding: wd@denx.de
	14	V* Verification: dzu@denx.de
	15	*
	16	* See file CREDITS for list of people who contributed to this
	17	* project.
	18	*
	19	* This program is free software; you can redistribute it and/or
	20	* modify it under the terms of the GNU General Public License as
	21	* published by the Free Software Foundation; either version 2 of
	22	* the License, or (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	32	* MA 02111-1307 USA
	33	***********************************************************************/
	34
	35	/---------------------------- Headerfiles ----------------------------/
	36	#include <common.h>
	37	#include <mpc8xx.h>
	38	#include <commproc.h>
	39	#include <i2c.h>
	40	#include <command.h>
e2211743 WD	41	#include <malloc.h>
e2211743 WD	42	#include <post.h>
281e00a3	43	#include <serial.h>
e2211743 WD	44
	45	#include <linux/types.h>
	46	#include <linux/string.h> /* for strdup */
	47
d87080b7 WD	48	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	49
e2211743 WD	50	/------------------------ Local prototypes ---------------------------/
e2211743 WD	51	static long int dram_size (long int, long int *, long int);
4532cb69 WD	52	static void kbd_init (void);
4532cb69 WD	53	static int compare_magic (uchar kbd_data, uchar str);
e2211743 WD	54
	55
	56	/--------------------- Local macros and constants --------------------/
	57	#define _NOT_USED_ 0xFFFFFFFF
	58
4532cb69 WD	59	#ifdef CONFIG_MODEM_SUPPORT
	60	static int key_pressed(void);
	61	extern void disable_putc(void);
	62	#endif /* CONFIG_MODEM_SUPPORT */
	63
e2211743 WD	64	/*
	65	* 66 MHz SDRAM access using UPM A
	66	*/
	67	const uint sdram_table[] =
	68	{
6d0f6bcf	69	#if defined(CONFIG_SYS_MEMORY_75) \|\| defined(CONFIG_SYS_MEMORY_8E)
e2211743 WD	70	/*
	71	* Single Read. (Offset 0 in UPM RAM)
	72	*/
	73	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	74	0x1FF5FC47, /* last */
	75	/*
	76	* SDRAM Initialization (offset 5 in UPM RAM)
	77	*
8bde7f77 WD	78	* This is no UPM entry point. The following definition uses
	79	* the remaining space to establish an initialization
	80	* sequence, which is executed by a RUN command.
e2211743 WD	81	*
	82	*/
	83	0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	84	/*
	85	* Burst Read. (Offset 8 in UPM RAM)
	86	*/
	87	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	88	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	89	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	90	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	91	/*
	92	* Single Write. (Offset 18 in UPM RAM)
	93	*/
	94	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	95	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	96	/*
	97	* Burst Write. (Offset 20 in UPM RAM)
	98	*/
	99	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	100	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
	101	_NOT_USED_,
	102	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	103	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	104	/*
	105	* Refresh (Offset 30 in UPM RAM)
	106	*/
	107	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	108	0xFFFFFC84, 0xFFFFFC07, /* last */
	109	_NOT_USED_, _NOT_USED_,
	110	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	111	/*
	112	* Exception. (Offset 3c in UPM RAM)
	113	*/
	114	0x7FFFFC07, /* last */
	115	0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
	116	#endif
6d0f6bcf	117	#ifdef CONFIG_SYS_MEMORY_7E
e2211743 WD	118	/*
	119	* Single Read. (Offset 0 in UPM RAM)
	120	*/
	121	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
	122	_NOT_USED_,
	123	/*
	124	* SDRAM Initialization (offset 5 in UPM RAM)
	125	*
8bde7f77 WD	126	* This is no UPM entry point. The following definition uses
	127	* the remaining space to establish an initialization
	128	* sequence, which is executed by a RUN command.
e2211743 WD	129	*
	130	*/
	131	0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	132	/*
	133	* Burst Read. (Offset 8 in UPM RAM)
	134	*/
	135	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
	136	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
8bde7f77	137	_NOT_USED_,
e2211743 WD	138	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	139	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	140	/*
	141	* Single Write. (Offset 18 in UPM RAM)
	142	*/
	143	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
	144	_NOT_USED_,
	145	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	146	/*
	147	* Burst Write. (Offset 20 in UPM RAM)
	148	*/
	149	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
	150	0xE1BAFC04, 0x1FF5FC47, /* last */
8bde7f77	151	_NOT_USED_, _NOT_USED_,
e2211743 WD	152	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	153	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	154	/*
	155	* Refresh (Offset 30 in UPM RAM)
	156	*/
	157	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	158	0xFFFFFC84, 0xFFFFFC07, /* last */
	159	_NOT_USED_, _NOT_USED_,
	160	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	161	/*
	162	* Exception. (Offset 3c in UPM RAM)
	163	*/
	164	0x7FFFFC07, /* last */
	165	0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
	166	#endif
	167	};
	168
	169	/*
	170	* Check Board Identity:
	171	*
	172	*/
	173
	174	/***********************************************************************
	175	F* Function: int checkboard (void) PAZ*
	176	*
	177	P* Parameters: none
	178	P*
	179	P* Returnvalue: int - 0 is always returned
	180	*
	181	Z* Intention: This function is the checkboard() method implementation
	182	Z* for the lwmon board. Only a standard message is printed.
	183	*
	184	D* Design: wd@denx.de
	185	C* Coding: wd@denx.de
	186	V* Verification: dzu@denx.de
	187	***********************************************************************/
	188	int checkboard (void)
	189	{
ee073a55	190	puts ("Board: LICCON Konsole LCD3\n");
e2211743 WD	191	return (0);
	192	}
	193
	194	/***********************************************************************
9973e3c6	195	F* Function: phys_size_t initdram (int board_type) PAZ*
e2211743 WD	196	*
	197	P* Parameters: int board_type
	198	P* - Usually type of the board - ignored here.
	199	P*
	200	P* Returnvalue: long int
	201	P* - Size of initialized memory
	202	*
	203	Z* Intention: This function is the initdram() method implementation
	204	Z* for the lwmon board.
	205	Z* The memory controller is initialized to access the
	206	Z* DRAM.
	207	*
	208	D* Design: wd@denx.de
	209	C* Coding: wd@denx.de
	210	V* Verification: dzu@denx.de
	211	***********************************************************************/
9973e3c6	212	phys_size_t initdram (int board_type)
e2211743	213	{
6d0f6bcf	214	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
e2211743 WD	215	volatile memctl8xx_t *memctl = &immr->im_memctl;
	216	long int size_b0;
	217	long int size8, size9;
	218	int i;
	219
	220	/*
	221	* Configure UPMA for SDRAM
	222	*/
	223	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
	224
6d0f6bcf	225	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
e2211743 WD	226
e2211743 WD	227	/* burst length=4, burst type=sequential, CAS latency=2 */
6d0f6bcf	228	memctl->memc_mar = CONFIG_SYS_MAR;
e2211743 WD	229
	230	/*
	231	* Map controller bank 3 to the SDRAM bank at preliminary address.
	232	*/
6d0f6bcf JCPV	233	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
6d0f6bcf JCPV	234	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
e2211743 WD	235
e2211743 WD	236	/* initialize memory address register */
6d0f6bcf	237	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */
e2211743 WD	238
	239	/* mode initialization (offset 5) */
	240	udelay (200); /* 0x80006105 */
	241	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x05);
	242
	243	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
	244	udelay (1); /* 0x80006130 */
	245	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x30);
	246	udelay (1); /* 0x80006130 */
	247	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x30);
	248
	249	udelay (1); /* 0x80006106 */
	250	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x06);
	251
2535d602	252	memctl->memc_mamr \|= MAMR_PTAE; /* refresh enabled */
e2211743 WD	253
	254	udelay (200);
	255
	256	/* Need at least 10 DRAM accesses to stabilize */
	257	for (i = 0; i < 10; ++i) {
	258	volatile unsigned long *addr =
	259	(volatile unsigned long *) SDRAM_BASE3_PRELIM;
	260	unsigned long val;
	261
	262	val = *(addr + i);
	263	*(addr + i) = val;
	264	}
	265
	266	/*
	267	* Check Bank 0 Memory Size for re-configuration
	268	*
	269	* try 8 column mode
	270	*/
6d0f6bcf	271	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
e2211743 WD	272
	273	udelay (1000);
	274
	275	/*
	276	* try 9 column mode
	277	*/
6d0f6bcf	278	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
e2211743 WD	279
	280	if (size8 < size9) { /* leave configuration at 9 columns */
	281	size_b0 = size9;
6d0f6bcf	282	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL \| MAMR_PTAE;
e2211743 WD	283	udelay (500);
	284	} else { /* back to 8 columns */
	285	size_b0 = size8;
6d0f6bcf	286	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL \| MAMR_PTAE;
e2211743 WD	287	udelay (500);
	288	}
	289
	290	/*
	291	* Final mapping:
	292	*/
	293
	294	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) \|
	295	OR_CSNT_SAM \| OR_G5LS \| SDRAM_TIMING;
6d0f6bcf	296	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
e2211743 WD	297	udelay (1000);
	298
	299	return (size_b0);
	300	}
	301
	302	/***********************************************************************
	303	F* Function: static long int dram_size (long int mamr_value,
	304	F* long int *base,
	305	F* long int maxsize) PAZ*
	306	*
	307	P* Parameters: long int mamr_value
	308	P* - Value for MAMR for the test
	309	P* long int *base
	310	P* - Base address for the test
	311	P* long int maxsize
	312	P* - Maximum size to test for
	313	P*
	314	P* Returnvalue: long int
	315	P* - Size of probed memory
	316	*
	317	Z* Intention: Check memory range for valid RAM. A simple memory test
	318	Z* determines the actually available RAM size between
	319	Z* addresses `base' and `base + maxsize'. Some (not all)
	320	Z* hardware errors are detected:
	321	Z* - short between address lines
	322	Z* - short between data lines
	323	*
	324	D* Design: wd@denx.de
	325	C* Coding: wd@denx.de
	326	V* Verification: dzu@denx.de
	327	***********************************************************************/
	328	static long int dram_size (long int mamr_value, long int *base, long int maxsize)
	329	{
6d0f6bcf	330	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
e2211743	331	volatile memctl8xx_t *memctl = &immr->im_memctl;
e2211743 WD	332
	333	memctl->memc_mamr = mamr_value;
	334
c83bf6a2	335	return (get_ram_size(base, maxsize));
e2211743 WD	336	}
	337
	338	/* ------------------------------------------------------------------------- */
	339
	340	#ifndef PB_ENET_TENA
	341	# define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
	342	#endif
	343
	344	/***********************************************************************
c837dcb1	345	F* Function: int board_early_init_f (void) PAZ*
e2211743 WD	346	*
	347	P* Parameters: none
	348	P*
	349	P* Returnvalue: int
	350	P* - 0 is always returned.
	351	*
c837dcb1	352	Z* Intention: This function is the board_early_init_f() method implementation
e2211743 WD	353	Z* for the lwmon board.
	354	Z* Disable Ethernet TENA on Port B.
	355	*
	356	D* Design: wd@denx.de
	357	C* Coding: wd@denx.de
	358	V* Verification: dzu@denx.de
	359	***********************************************************************/
c837dcb1	360	int board_early_init_f (void)
e2211743	361	{
6d0f6bcf	362	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
e2211743 WD	363
	364	/* Disable Ethernet TENA on Port B
	365	* Necessary because of pull up in COM3 port.
	366	*
	367	* This is just a preliminary fix, intended to turn off TENA
	368	* as soon as possible to avoid noise on the network. Once
	369