[people/ms/u-boot.git] / board / lwmon5 / lwmon5.c

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <ppc440.h>
#include <asm/processor.h>
#include <asm/gpio.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/

ulong flash_get_size(ulong base, int banknum);
int misc_init_r_kbd(void);

int board_early_init_f(void)
{
	u32 sdr0_pfc1, sdr0_pfc2;
	u32 reg;

	/* PLB Write pipelining disabled. Denali Core workaround */
	mtdcr(PLB0_ACR, 0xDE000000);
	mtdcr(PLB1_ACR, 0xDE000000);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr(UIC0SR, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
	mtdcr(UIC0ER, 0x00000000);  /* disable all */
	mtdcr(UIC0CR, 0x00000000);  /* we have not critical interrupts at the moment */
	mtdcr(UIC0PR, 0xFFBFF1EF);  /* Adjustment of the polarity */
	mtdcr(UIC0TR, 0x00000900);  /* per ref-board manual */
	mtdcr(UIC0VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
	mtdcr(UIC0SR, 0xffffffff);  /* clear all */

	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
	mtdcr(UIC1ER, 0x00000000);  /* disable all */
	mtdcr(UIC1CR, 0x00000000);  /* all non-critical */
	mtdcr(UIC1PR, 0xFFFFC6A5);  /* Adjustment of the polarity */
	mtdcr(UIC1TR, 0x60000040);  /* per ref-board manual */
	mtdcr(UIC1VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
	mtdcr(UIC1SR, 0xffffffff);  /* clear all */

	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
	mtdcr(UIC2ER, 0x00000000);  /* disable all */
	mtdcr(UIC2CR, 0x00000000);  /* all non-critical */
	mtdcr(UIC2PR, 0x27C00000);  /* Adjustment of the polarity */
	mtdcr(UIC2TR, 0x3C000000);  /* per ref-board manual */
	mtdcr(UIC2VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
	mtdcr(UIC2SR, 0xffffffff);  /* clear all */

	/* Trace Pins are disabled. SDR0_PFC0 Register */
	mtsdr(SDR0_PFC0, 0x0);

	/* select Ethernet pins */
	mfsdr(SDR0_PFC1, sdr0_pfc1);
	/* SMII via ZMII */
	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
		SDR0_PFC1_SELECT_CONFIG_6;
	mfsdr(SDR0_PFC2, sdr0_pfc2);
	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
		SDR0_PFC2_SELECT_CONFIG_6;

	/* enable SPI (SCP) */
	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;

	mtsdr(SDR0_PFC2, sdr0_pfc2);
	mtsdr(SDR0_PFC1, sdr0_pfc1);

	mtsdr(SDR0_PFC4, 0x80000000);

	/* PCI arbiter disabled */
	/* PCI Host Configuration disbaled */
	mfsdr(SDR0_PCI0, reg);
	reg = 0;
	mtsdr(SDR0_PCI0, 0x00000000 | reg);

	gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);

#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);

	reg = 0; /* reuse as counter */
	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
		in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
			& ~CONFIG_SYS_DSPIC_TEST_MASK);
	while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
		udelay(1000);
	}
	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
	if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
		/* set "boot error" flag */
		out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
			in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
			CONFIG_SYS_DSPIC_TEST_MASK);
	}
#endif

	/*
	 * Reset PHY's:
	 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
	 * upon reset, and with the first reset upon powerup, the addresses are
	 * not latched reliable, since the IRQ line is multiplexed with an
	 * MDIO address. A 2nd reset at this time will make sure, that the
	 * correct address is latched.
	 */
	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
	udelay(1000);
	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
	udelay(1000);
	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);

	return 0;
}

/*---------------------------------------------------------------------------+
  | misc_init_r.
  +---------------------------------------------------------------------------*/
int misc_init_r(void)
{
	u32 pbcr;
	int size_val = 0;
	u32 reg;
	unsigned long usb2d0cr = 0;
	unsigned long usb2phy0cr, usb2h0cr = 0;
	unsigned long sdr0_pfc1;

	/*
	 * FLASH stuff...
	 */

	/* Re-do sizing to get full correct info */

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	mfebc(PB0CR, pbcr);
	switch (gd->bd->bi_flashsize) {
	case 1 << 20:
		size_val = 0;
		break;
	case 2 << 20:
		size_val = 1;
		break;
	case 4 << 20:
		size_val = 2;
		break;
	case 8 << 20:
		size_val = 3;
		break;
	case 16 << 20:
		size_val = 4;
		break;
	case 32 << 20:
		size_val = 5;
		break;
	case 64 << 20:
		size_val = 6;
		break;
	case 128 << 20:
		size_val = 7;
		break;
	}
	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
	mtebc(PB0CR, pbcr);

	/*
	 * Re-check to get correct base address
	 */
	flash_get_size(gd->bd->bi_flashstart, 0);

	/* Monitor protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    -CONFIG_SYS_MONITOR_LEN,
			    0xffffffff,
			    &flash_info[1]);

	/* Env protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    CONFIG_ENV_ADDR_REDUND,
			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
			    &flash_info[1]);

	/*
	 * USB suff...
	 */
	/* SDR Setting */
	mfsdr(SDR0_PFC1, sdr0_pfc1);
	mfsdr(SDR0_USB0, usb2d0cr);
	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
	mfsdr(SDR0_USB2H0CR, usb2h0cr);

	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/

	/* An 8-bit/60MHz interface is the only possible alternative
	   when connecting the Device to the PHY */
	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/

	mtsdr(SDR0_PFC1, sdr0_pfc1);
	mtsdr(SDR0_USB0, usb2d0cr);
	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
	mtsdr(SDR0_USB2H0CR, usb2h0cr);

	/*
	 * Clear resets
	 */
	udelay (1000);
	mtsdr(SDR0_SRST1, 0x00000000);
	udelay (1000);
	mtsdr(SDR0_SRST0, 0x00000000);

	printf("USB:   Host(int phy) Device(ext phy)\n");

	/*
	 * Clear PLB4A0_ACR[WRP]
	 * This fix will make the MAL burst disabling patch for the Linux
	 * EMAC driver obsolete.
	 */
	reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
	mtdcr(PLB4_ACR, reg);

	/*
	 * Init matrix keyboard
	 */
	misc_init_r_kbd();

	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: lwmon5");

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

void hw_watchdog_reset(void)
{
	int val;
#if defined(CONFIG_WD_MAX_RATE)
	unsigned long long ct = get_ticks();

	/*
	 * Don't allow watch-dog triggering more frequently than
	 * the predefined value CONFIG_WD_MAX_RATE [ticks].
	 */
	if (ct >= gd->wdt_last) {
		if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
			return;
	} else {
		/* Time base counter had been reset */
		if (((unsigned long long)(-1) - gd->wdt_last + ct) <
		    CONFIG_WD_MAX_RATE)
			return;
	}
	gd->wdt_last = get_ticks();
#endif

	/*
	 * Toggle watchdog output
	 */
	val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
	gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
}

int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	if (argc < 2) {
		cmd_usage(cmdtp);
		return 1;
	}

	if ((strcmp(argv[1], "on") == 0)) {
		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
	} else if ((strcmp(argv[1], "off") == 0)) {
		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
	} else {
		cmd_usage(cmdtp);
		return 1;
	}


	return 0;
}

U_BOOT_CMD(
	eepromwp,	2,	0,	do_eeprom_wp,
	"eeprom write protect off/on",
	"<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
);

#if defined(CONFIG_VIDEO)
#include <video_fb.h>
#include <mb862xx.h>

extern GraphicDevice mb862xx;

static const gdc_regs init_regs [] =
{
	{0x0100, 0x00000f00},
	{0x0020, 0x801401df},
	{0x0024, 0x00000000},
	{0x0028, 0x00000000},
	{0x002c, 0x00000000},
	{0x0110, 0x00000000},
	{0x0114, 0x00000000},
	{0x0118, 0x01df0280},
	{0x0004, 0x031f0000},
	{0x0008, 0x027f027f},
	{0x000c, 0x015f028f},
	{0x0010, 0x020c0000},
	{0x0014, 0x01df01ea},
	{0x0018, 0x00000000},
	{0x001c, 0x01e00280},
	{0x0100, 0x80010f00},
	{0x0, 0x0}
};

const gdc_regs *board_get_regs (void)
{
	return init_regs;
}

/* Returns Lime base address */
unsigned int board_video_init (void)
{
	/*
	 * Reset Lime controller
	 */
	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
	udelay(500);
	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);

	mb862xx.winSizeX = 640;
	mb862xx.winSizeY = 480;
	mb862xx.gdfBytesPP = 2;
	mb862xx.gdfIndex = GDF_15BIT_555RGB;

	return CONFIG_SYS_LIME_BASE_0;
}

#define DEFAULT_BRIGHTNESS 0x64

static void board_backlight_brightness(int brightness)
{
	if (brightness > 0) {
		/* pwm duty, lamp on */
		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
	} else {
		/* lamp off */
		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
	}
}

void board_backlight_switch (int flag)
{
	char * param;
	int rc;

	if (flag) {
		param = getenv("brightness");
		rc = param ? simple_strtol(param, NULL, 10) : -1;
		if (rc < 0)
			rc = DEFAULT_BRIGHTNESS;
	} else {
		rc = 0;
	}
	board_backlight_brightness(rc);
}

#if defined(CONFIG_CONSOLE_EXTRA_INFO)
/*
 * Return text to be printed besides the logo.
 */
void video_get_info_str (int line_number, char *info)
{
	if (line_number == 1) {
		strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
	} else {
		info [0] = '\0';
	}
}
#endif
#endif /* CONFIG_VIDEO */

void board_reset(void)
{
	gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
}
Commit	Line	Data
b765ffb7 SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20
	21	#include <common.h>
c25dd8fc	22	#include <command.h>
b765ffb7	23	#include <ppc440.h>
04e6c38b	24	#include <asm/processor.h>
b765ffb7	25	#include <asm/gpio.h>
04e6c38b	26	#include <asm/io.h>
b765ffb7 SR	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
6d0f6bcf	30	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
b765ffb7	31
3ad63878 SR	32	ulong flash_get_size(ulong base, int banknum);
3ad63878 SR	33	int misc_init_r_kbd(void);
b765ffb7 SR	34
	35	int board_early_init_f(void)
	36	{
	37	u32 sdr0_pfc1, sdr0_pfc2;
	38	u32 reg;
	39
83b4cfa3	40	/* PLB Write pipelining disabled. Denali Core workaround */
d1c3b275 SR	41	mtdcr(PLB0_ACR, 0xDE000000);
d1c3b275 SR	42	mtdcr(PLB1_ACR, 0xDE000000);
b765ffb7 SR	43
	44	/*--------------------------------------------------------------------
	45	* Setup the interrupt controller polarities, triggers, etc.
	46	-------------------------------------------------------------------/
952e7760 SR	47	mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
	48	mtdcr(UIC0ER, 0x00000000); /* disable all */
	49	mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
	50	mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
	51	mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
	52	mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
	53	mtdcr(UIC0SR, 0xffffffff); /* clear all */
b765ffb7	54
952e7760 SR	55	mtdcr(UIC1SR, 0xffffffff); /* clear all */
	56	mtdcr(UIC1ER, 0x00000000); /* disable all */
	57	mtdcr(UIC1CR, 0x00000000); /* all non-critical */
	58	mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
	59	mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
	60	mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
	61	mtdcr(UIC1SR, 0xffffffff); /* clear all */
b765ffb7	62
952e7760 SR	63	mtdcr(UIC2SR, 0xffffffff); /* clear all */
	64	mtdcr(UIC2ER, 0x00000000); /* disable all */
	65	mtdcr(UIC2CR, 0x00000000); /* all non-critical */
	66	mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
	67	mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
	68	mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
	69	mtdcr(UIC2SR, 0xffffffff); /* clear all */
b765ffb7 SR	70
	71	/* Trace Pins are disabled. SDR0_PFC0 Register */
	72	mtsdr(SDR0_PFC0, 0x0);
	73
	74	/* select Ethernet pins */
	75	mfsdr(SDR0_PFC1, sdr0_pfc1);
	76	/* SMII via ZMII */
	77	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) \|
	78	SDR0_PFC1_SELECT_CONFIG_6;
	79	mfsdr(SDR0_PFC2, sdr0_pfc2);
	80	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) \|
	81	SDR0_PFC2_SELECT_CONFIG_6;
	82
	83	/* enable SPI (SCP) */
	84	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) \| SDR0_PFC1_SIS_SCP_SEL;
	85
	86	mtsdr(SDR0_PFC2, sdr0_pfc2);
	87	mtsdr(SDR0_PFC1, sdr0_pfc1);
	88
	89	mtsdr(SDR0_PFC4, 0x80000000);
	90
	91	/* PCI arbiter disabled */
83b4cfa3	92	/* PCI Host Configuration disbaled */
d1c3b275	93	mfsdr(SDR0_PCI0, reg);
83b4cfa3	94	reg = 0;
d1c3b275	95	mtsdr(SDR0_PCI0, 0x00000000 \| reg);
b765ffb7	96
6d0f6bcf	97	gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
b765ffb7	98
6d0f6bcf JCPV	99	#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
6d0f6bcf JCPV	100	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);
65b20dce YT	101
65b20dce YT	102	reg = 0; /* reuse as counter */
6d0f6bcf JCPV	103	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
	104	in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
	105	& ~CONFIG_SYS_DSPIC_TEST_MASK);
	106	while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
65b20dce YT	107	udelay(1000);
65b20dce YT	108	}
6d0f6bcf JCPV	109	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
6d0f6bcf JCPV	110	if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
65b20dce	111	/* set "boot error" flag */
6d0f6bcf JCPV	112	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
	113	in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) \|
	114	CONFIG_SYS_DSPIC_TEST_MASK);
65b20dce YT	115	}
	116	#endif
	117
54fd6c93 SR	118	/*
	119	* Reset PHY's:
	120	* The PHY's need a 2nd reset pulse, since the MDIO address is latched
	121	* upon reset, and with the first reset upon powerup, the addresses are
	122	* not latched reliable, since the IRQ line is multiplexed with an
	123	* MDIO address. A 2nd reset at this time will make sure, that the
	124	* correct address is latched.
	125	*/
6d0f6bcf JCPV	126	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
6d0f6bcf JCPV	127	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
54fd6c93	128	udelay(1000);
6d0f6bcf JCPV	129	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
6d0f6bcf JCPV	130	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
54fd6c93	131	udelay(1000);
6d0f6bcf JCPV	132	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
6d0f6bcf JCPV	133	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
54fd6c93	134
b765ffb7 SR	135	return 0;
	136	}
	137
	138	/*---------------------------------------------------------------------------+
	139	\| misc_init_r.
	140	+---------------------------------------------------------------------------*/
	141	int misc_init_r(void)
	142	{
	143	u32 pbcr;
	144	int size_val = 0;
	145	u32 reg;
	146	unsigned long usb2d0cr = 0;
	147	unsigned long usb2phy0cr, usb2h0cr = 0;
	148	unsigned long sdr0_pfc1;
	149
	150	/*
	151	* FLASH stuff...
	152	*/
	153
	154	/* Re-do sizing to get full correct info */
	155
	156	/* adjust flash start and offset */
	157	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	158	gd->bd->bi_flashoffset = 0;
	159
d1c3b275	160	mfebc(PB0CR, pbcr);
b765ffb7 SR	161	switch (gd->bd->bi_flashsize) {
	162	case 1 << 20:
	163	size_val = 0;
	164	break;
	165	case 2 << 20:
	166	size_val = 1;
	167	break;
	168	case 4 << 20:
	169	size_val = 2;
	170	break;
	171	case 8 << 20:
	172	size_val = 3;
	173	break;
	174	case 16 << 20:
	175	size_val = 4;
	176	break;
	177	case 32 << 20:
	178	size_val = 5;
	179	break;
	180	case 64 << 20:
	181	size_val = 6;
	182	break;
	183	case 128 << 20:
	184	size_val = 7;
	185	break;
	186	}
	187	pbcr = (pbcr & 0x0001ffff) \| gd->bd->bi_flashstart \| (size_val << 17);
d1c3b275	188	mtebc(PB0CR, pbcr);
b765ffb7 SR	189
	190	/*
	191	* Re-check to get correct base address
	192	*/
	193	flash_get_size(gd->bd->bi_flashstart, 0);
	194
	195	/* Monitor protection ON by default */
	196	(void)flash_protect(FLAG_PROTECT_SET,
6d0f6bcf	197	-CONFIG_SYS_MONITOR_LEN,
b765ffb7	198	0xffffffff,
9f24a808	199	&flash_info[1]);
b765ffb7 SR	200
	201	/* Env protection ON by default */
	202	(void)flash_protect(FLAG_PROTECT_SET,
0e8d1586 JCPV	203	CONFIG_ENV_ADDR_REDUND,
0e8d1586 JCPV	204	CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
9f24a808	205	&flash_info[1]);
b765ffb7 SR	206
	207	/*
	208	* USB suff...
	209	*/
	210	/* SDR Setting */
	211	mfsdr(SDR0_PFC1, sdr0_pfc1);
	212	mfsdr(SDR0_USB0, usb2d0cr);
	213	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
	214	mfsdr(SDR0_USB2H0CR, usb2h0cr);
	215
	216	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
	217	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /0/
	218	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
	219	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /1/
	220	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
	221	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_DVBUS_PURDIS; /0/
	222	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
	223	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_DWNSTR_HOST; /1/
	224	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
	225	usb2phy0cr = usb2phy0cr \| SDR0_USB2PHY0CR_UTMICN_HOST; /1/
	226
	227	/* An 8-bit/60MHz interface is the only possible alternative
	228	when connecting the Device to the PHY */
	229	usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
	230	usb2h0cr = usb2h0cr \| SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /1/
	231
	232	mtsdr(SDR0_PFC1, sdr0_pfc1);
	233	mtsdr(SDR0_USB0, usb2d0cr);
	234	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
	235	mtsdr(SDR0_USB2H0CR, usb2h0cr);
	236
	237	/*
	238	* Clear resets
	239	*/
	240	udelay (1000);
	241	mtsdr(SDR0_SRST1, 0x00000000);
	242	udelay (1000);
	243	mtsdr(SDR0_SRST0, 0x00000000);
	244
	245	printf("USB: Host(int phy) Device(ext phy)\n");
	246
	247	/*
	248	* Clear PLB4A0_ACR[WRP]
	249	* This fix will make the MAL burst disabling patch for the Linux
	250	* EMAC driver obsolete.
	251	*/
d1c3b275 SR	252	reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
d1c3b275 SR	253	mtdcr(PLB4_ACR, reg);
b765ffb7	254
3ad63878 SR	255	/*
	256	* Init matrix keyboard
	257	*/
	258	misc_init_r_kbd();
	259
b765ffb7 SR	260	return 0;
	261	}
	262
	263	int checkboard(void)
	264	{
	265	char *s = getenv("serial#");
	266
	267	printf("Board: lwmon5");
	268
	269	if (s != NULL) {
	270	puts(", serial# ");
	271	puts(s);
	272	}
	273	putc('\n');
	274
	275	return (0);
	276	}
	277
b765ffb7 SR	278	void hw_watchdog_reset(void)
	279	{
	280	int val;
d32a874b YT	281	#if defined(CONFIG_WD_MAX_RATE)
	282	unsigned long long ct = get_ticks();
	283
	284	/*
	285	* Don't allow watch-dog triggering more frequently than
	286	* the predefined value CONFIG_WD_MAX_RATE [ticks].
	287	*/
	288	if (ct >= gd->wdt_last) {
	289	if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
	290	return;
	291	} else {
	292	/* Time base counter had been reset */
	293	if (((unsigned long long)(-1) - gd->wdt_last + ct) <
	294	CONFIG_WD_MAX_RATE)
	295	return;
	296	}
	297	gd->wdt_last = get_ticks();
	298	#endif
b765ffb7 SR	299
	300	/*
	301	* Toggle watchdog output
	302	*/
6d0f6bcf JCPV	303	val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
6d0f6bcf JCPV	304	gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
b765ffb7	305	}
c25dd8fc SR	306
	307	int do_eeprom_wp(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	308	{
	309	if (argc < 2) {
62c3ae7c	310	cmd_usage(cmdtp);
c25dd8fc SR	311	return 1;
	312	}
	313
	314	if ((strcmp(argv[1], "on") == 0)) {
6d0f6bcf	315	gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
c25dd8fc	316	} else if ((strcmp(argv[1], "off") == 0)) {
6d0f6bcf	317	gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
c25dd8fc	318	} else {
62c3ae7c	319	cmd_usage(cmdtp);
c25dd8fc SR	320	return 1;
	321	}
	322
	323
	324	return 0;
	325	}
	326
	327	U_BOOT_CMD(
	328	eepromwp, 2, 0, do_eeprom_wp,
2fb2604d	329	"eeprom write protect off/on",
a89c33db	330	"<on\|off> - enable (on) or disable (off) I2C EEPROM write protect"
c25dd8fc	331	);
d610a607 AG	332
	333	#if defined(CONFIG_VIDEO)
	334	#include <video_fb.h>
	335	#include <mb862xx.h>
	336
	337	extern GraphicDevice mb862xx;
	338
	339	static const gdc_regs init_regs [] =
	340	{
	341	{0x0100, 0x00000f00},
	342	{0x0020, 0x801401df},
	343	{0x0024, 0x00000000},
	344	{0x0028, 0x00000000},
	345	{0x002c, 0x00000000},
	346	{0x0110, 0x00000000},
	347	{0x0114, 0x00000000},
	348	{0x0118, 0x01df0280},
	349	{0x0004, 0x031f0000},
	350	{0x0008, 0x027f027f},
	351	{0x000c, 0x015f028f},
	352	{0x0010, 0x020c0000},
	353	{0x0014, 0x01df01ea},
	354	{0x0018, 0x00000000},
	355	{0x001c, 0x01e00280},
	356	{0x0100, 0x80010f00},
	357	{0x0, 0x0}
	358	};
	359
	360	const gdc_regs *board_get_regs (void)
	361	{
	362	return init_regs;
	363	}
	364
	365	/* Returns Lime base address */
	366	unsigned int board_video_init (void)
	367	{
	368	/*
	369	* Reset Lime controller
	370	*/
6d0f6bcf	371	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
d610a607	372	udelay(500);
6d0f6bcf	373	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
d610a607	374
d610a607 AG	375	mb862xx.winSizeX = 640;
	376	mb862xx.winSizeY = 480;
	377	mb862xx.gdfBytesPP = 2;
	378	mb862xx.gdfIndex = GDF_15BIT_555RGB;
	379
6d0f6bcf	380	return CONFIG_SYS_LIME_BASE_0;
d610a607 AG	381	}
d610a607 AG	382
0f855a1f YT	383	#define DEFAULT_BRIGHTNESS 0x64
	384
	385	static void board_backlight_brightness(int brightness)
d610a607	386	{
0f855a1f	387	if (brightness > 0) {
d610a607	388	/* pwm duty, lamp on */
6d0f6bcf JCPV	389	out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
6d0f6bcf JCPV	390	out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
d610a607 AG	391	} else {
d610a607 AG	392	/* lamp off */
6d0f6bcf JCPV	393	out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
6d0f6bcf JCPV	394	out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
d610a607 AG	395	}
	396	}
	397
0f855a1f YT	398	void board_backlight_switch (int flag)
	399	{
	400	char * param;
	401	int rc;
	402
	403	if (flag) {
	404	param = getenv("brightness");
	405	rc = param ? simple_strtol(param, NULL, 10) : -1;
	406	if (rc < 0)
	407	rc = DEFAULT_BRIGHTNESS;
	408	} else {
	409	rc = 0;
	410	}
	411	board_backlight_brightness(rc);
	412	}
	413
d610a607 AG	414	#if defined(CONFIG_CONSOLE_EXTRA_INFO)
	415	/*
	416	* Return text to be printed besides the logo.
	417	*/
	418	void video_get_info_str (int line_number, char *info)
	419	{
	420	if (line_number == 1) {
	421	strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
	422	} else {
	423	info [0] = '\0';
	424	}
	425	}
	426	#endif
	427	#endif /* CONFIG_VIDEO */
ff818b21 YT	428
	429	void board_reset(void)
	430	{
6d0f6bcf	431	gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
ff818b21	432	}