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omap_hsmmc: add driver check for write protection
[people/ms/u-boot.git] / board / matrix_vision / mvblx / mvblx.c
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1/*
2 * MATRIX VISION GmbH mvBlueLYNX-X
3 *
4 * Derived from Beagle and Overo
5 *
6 * (C) Copyright 2004-2008
7 * Texas Instruments, <www.ti.com>
8 *
9 * Author :
10 * Sunil Kumar <sunilsaini05@gmail.com>
11 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 *
13 * Derived from Beagle Board and 3430 SDP code by
14 * Richard Woodruff <r-woodruff2@ti.com>
15 * Syed Mohammed Khasim <khasim@ti.com>
16 *
17 *
18 * See file CREDITS for list of people who contributed to this
19 * project.
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * MA 02111-1307 USA
35 */
36#include <common.h>
37#include <netdev.h>
38#include <twl4030.h>
39#include <asm/io.h>
40#include <asm/arch/mem.h>
41#include <asm/arch/mmc_host_def.h>
42#include <asm/arch/mux.h>
43#include <asm/arch/sys_proto.h>
44#include <asm/arch/gpio.h>
45#include <asm/mach-types.h>
46#include "mvblx.h"
47#include "fpga.h"
48
49DECLARE_GLOBAL_DATA_PTR;
50
51#if defined(CONFIG_CMD_NET)
52static void setup_net_chip(void);
53#endif /* CONFIG_CMD_NET */
54
55/*
56 * Routine: board_init
57 * Description: Early hardware init.
58 */
59int board_init(void)
60{
61 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
62 /* boot param addr */
63 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
64
65 return 0;
66}
67
68/*
69 * Routine: misc_init_r
70 * Description: Configure board specific parts
71 */
72int misc_init_r(void)
73{
74 printf("mvBlueLYNX-X\n");
75 if (get_cpu_family() == CPU_OMAP36XX)
76 setenv("mpurate", "1000");
77 else
78 setenv("mpurate", "600");
79
80 twl4030_power_init();
81
82#if defined(CONFIG_CMD_NET)
83 setup_net_chip();
84#endif /* CONFIG_CMD_NET */
85
86 mvblx_init_fpga();
87
88 mac_read_from_eeprom();
89
90 dieid_num_r();
91
92 return 0;
93}
94
95/*
96 * Routine: set_muxconf_regs
97 * Description: Setting up the configuration Mux registers specific to the
98 * hardware. Many pins need to be moved from protect to primary
99 * mode.
100 */
101void set_muxconf_regs(void)
102{
103 MUX_MVBLX();
104}
105
106#ifdef CONFIG_GENERIC_MMC
107int board_mmc_init(bd_t *bis)
108{
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109 omap_mmc_init(0, 0, 0, -1, -1);
110 omap_mmc_init(1, 0, 0, -1, -1);
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111 return 0;
112}
113#endif
114
115#if defined(CONFIG_CMD_NET)
116/*
117 * Routine: setup_net_chip
118 * Description: Setting up the configuration GPMC registers specific to the
119 * Ethernet hardware.
120 */
121static void setup_net_chip(void)
122{
123 struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
124 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
125
126 /* Configure GPMC registers */
127 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
128 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
129 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
130 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
131 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
132 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
133 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
134
135 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
136 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
137 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
138 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
139 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
140 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
141 &ctrl_base->gpmc_nadv_ale);
142
143 /* Make GPIO 139 as output pin */
144 writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
145
146 /* Now send a pulse on the GPIO pin */
147 writel(GPIO11, &gpio5_base->setdataout);
148 udelay(1);
149 writel(GPIO11, &gpio5_base->cleardataout);
150 udelay(1);
151 writel(GPIO11, &gpio5_base->setdataout);
152}
153
154int board_eth_init(bd_t *bis)
155{
156 int rc = 0;
157#ifdef CONFIG_SMC911X
158 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
159#endif
160 return rc;
161}
162
163int overwrite_console(void)
164{
165 /* return TRUE if console should be overwritten */
166 return 0;
167}
168
169#endif /* CONFIG_CMD_NET */