[people/ms/u-boot.git] / board / mcc200 / mcc200.c

/*
 * (C) Copyright 2003-2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>

/* Two MT48LC8M32B2 for 32 MB */
/* #include "mt48lc8m32b2-6-7.h" */

/* One MT48LC16M32S2 for 64 MB */
/* #include "mt48lc16m32s2-75.h" */
#if defined (CONFIG_MCC200_SDRAM)
#include "mt48lc16m16a2-75.h"
#else
#include "mt46v16m16-75.h"
#endif

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[];	/* FLASH chips info */

extern int do_auto_update(void);
ulong flash_get_size (ulong base, int banknum);

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");

	udelay(10);
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *	      is something else than 0x00000000.
 */

phys_size_t initdram (int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
	uint svr, pvr;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

	/* find RAM size using SDRAM CS1 only */
	if (!dramsize)
		sdram_start(0);
	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	if (!dramsize) {
		sdram_start(1);
		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	}
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else {
		dramsize2 = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20)) {
		dramsize2 = 0;
	}

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	}

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CONFIG_SYS_RAMBOOT */

	/*
	 * On MPC5200B we need to set the special configuration delay in the
	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	 *
	 * "The SDelay should be written to a value of 0x00000004. It is
	 * required to account for changes caused by normal wafer processing
	 * parameters."
	 */
	svr = get_svr();
	pvr = get_pvr();
	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
		__asm__ volatile ("sync");
	}

	return dramsize + dramsize2;
}

int checkboard (void)
{
#if defined(CONFIG_PRS200)
	puts ("Board: PRS200\n");
#else
	puts ("Board: MCC200\n");
#endif
	return 0;
}

int misc_init_r (void)
{
	ulong flash_sup_end, snum;

	/*
	 * Adjust flash start and offset to detected values
	 */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/*
	 * Check if boot FLASH isn't max size
	 */
	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
		/* adjust mapping */
		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
			START_REG(gd->bd->bi_flashstart);
		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
			STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);

		/*
		 * Re-check to get correct base address
		 */
		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);

		/*
		 * Re-do flash protection upon new addresses
		 */
		flash_protect (FLAG_PROTECT_CLEAR,
			       gd->bd->bi_flashstart, 0xffffffff,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Monitor protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_ENV_ADDR,
			       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Redundant environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_ENV_ADDR_REDUND,
			       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
	}

	if (gd->bd->bi_flashsize > (32 << 20)) {
		/* Unprotect the upper bank of the Flash */
		*(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
		flash_protect (FLAG_PROTECT_CLEAR,
			       flash_info[0].start[0] + flash_info[0].size / 2,
			       (flash_info[0].start[0] - 1) + flash_info[0].size,
			       &flash_info[0]);
		*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
		printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
		flash_info[0].size = 32 << 20;
		for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
			flash_info[0].start[snum] < flash_sup_end;
			snum++);
		flash_info[0].sector_count = snum;
	}

#ifdef CONFIG_AUTO_UPDATE
	do_auto_update();
#endif
	return (0);
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)

void init_ide_reset (void)
{
	debug ("init_ide_reset\n");

}

void ide_set_reset (int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

}
#endif

#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
	doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif
Commit	Line	Data
86ea5f93 WD	1	/*
	2	* (C) Copyright 2003-2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <mpc5xxx.h>
	29	#include <pci.h>
91650b3e	30	#include <asm/processor.h>
86ea5f93	31
9e18a4bc WD	32	/* Two MT48LC8M32B2 for 32 MB */
	33	/* #include "mt48lc8m32b2-6-7.h" */
	34
	35	/* One MT48LC16M32S2 for 64 MB */
4819fad9 WD	36	/* #include "mt48lc16m32s2-75.h" */
	37	#if defined (CONFIG_MCC200_SDRAM)
	38	#include "mt48lc16m16a2-75.h"
	39	#else
	40	#include "mt46v16m16-75.h"
	41	#endif
86ea5f93	42
d87080b7 WD	43	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	44
58ad4978 SR	45	extern flash_info_t flash_info[]; /* FLASH chips info */
58ad4978 SR	46
cdb97a66	47	extern int do_auto_update(void);
f18e874a SR	48	ulong flash_get_size (ulong base, int banknum);
f18e874a SR	49
6d0f6bcf	50	#ifndef CONFIG_SYS_RAMBOOT
86ea5f93 WD	51	static void sdram_start (int hi_addr)
	52	{
	53	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	54
	55	/* unlock mode register */
	56	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	57	__asm__ volatile ("sync");
	58
	59	/* precharge all banks */
	60	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	61	__asm__ volatile ("sync");
	62
	63	#if SDRAM_DDR
	64	/* set mode register: extended mode */
	65	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	66	__asm__ volatile ("sync");
	67
	68	/* set mode register: reset DLL */
	69	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	70	__asm__ volatile ("sync");
	71	#endif
	72
	73	/* precharge all banks */
	74	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	75	__asm__ volatile ("sync");
	76
	77	/* auto refresh */
	78	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	79	__asm__ volatile ("sync");
	80
	81	/* set mode register */
	82	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	83	__asm__ volatile ("sync");
	84
	85	/* normal operation */
	86	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	87	__asm__ volatile ("sync");
9e18a4bc WD	88
9e18a4bc WD	89	udelay(10);
86ea5f93 WD	90	}
	91	#endif
	92
	93	/*
	94	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	95	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
f11033e7	96	* is something else than 0x00000000.
86ea5f93 WD	97	*/
86ea5f93 WD	98
9973e3c6	99	phys_size_t initdram (int board_type)
86ea5f93 WD	100	{
	101	ulong dramsize = 0;
	102	ulong dramsize2 = 0;
91650b3e	103	uint svr, pvr;
6d0f6bcf	104	#ifndef CONFIG_SYS_RAMBOOT
86ea5f93 WD	105	ulong test1, test2;
	106
	107	/* setup SDRAM chip selects */
	108	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	109	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	110	__asm__ volatile ("sync");
	111
	112	/* setup config registers */
	113	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	114	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	115	__asm__ volatile ("sync");
	116
	117	#if SDRAM_DDR
	118	/* set tap delay */
	119	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	120	__asm__ volatile ("sync");
	121	#endif
	122
	123	/* find RAM size using SDRAM CS0 only */
	124	sdram_start(0);
6d0f6bcf	125	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
86ea5f93	126	sdram_start(1);
6d0f6bcf	127	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
86ea5f93 WD	128	if (test1 > test2) {
	129	sdram_start(0);
	130	dramsize = test1;
	131	} else {
	132	dramsize = test2;
	133	}
	134
	135	/* memory smaller than 1MB is impossible */
	136	if (dramsize < (1 << 20)) {
	137	dramsize = 0;
	138	}
	139
	140	/* set SDRAM CS0 size according to the amount of RAM found */
	141	if (dramsize > 0) {
	142	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	143	} else {
	144	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	145	}
	146
	147	/* let SDRAM CS1 start right after CS0 */
	148	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
	149
	150	/* find RAM size using SDRAM CS1 only */
	151	if (!dramsize)
	152	sdram_start(0);
6d0f6bcf	153	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
86ea5f93 WD	154	if (!dramsize) {
86ea5f93 WD	155	sdram_start(1);
6d0f6bcf	156	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
86ea5f93 WD	157	}
	158	if (test1 > test2) {
	159	sdram_start(0);
	160	dramsize2 = test1;
	161	} else {
	162	dramsize2 = test2;
	163	}
	164
	165	/* memory smaller than 1MB is impossible */
	166	if (dramsize2 < (1 << 20)) {
	167	dramsize2 = 0;
	168	}
	169
	170	/* set SDRAM CS1 size according to the amount of RAM found */
	171	if (dramsize2 > 0) {
	172	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
	173	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	174	} else {
	175	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	176	}
	177
6d0f6bcf	178	#else /* CONFIG_SYS_RAMBOOT */
86ea5f93 WD	179
	180	/* retrieve size of memory connected to SDRAM CS0 */
	181	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	182	if (dramsize >= 0x13) {
	183	dramsize = (1 << (dramsize - 0x13)) << 20;
	184	} else {
	185	dramsize = 0;
	186	}
	187
	188	/* retrieve size of memory connected to SDRAM CS1 */
	189	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	190	if (dramsize2 >= 0x13) {
	191	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	192	} else {
	193	dramsize2 = 0;
	194	}
	195
6d0f6bcf	196	#endif /* CONFIG_SYS_RAMBOOT */
86ea5f93	197
91650b3e WD	198	/*
	199	* On MPC5200B we need to set the special configuration delay in the
	200	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	201	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	202	*
	203	* "The SDelay should be written to a value of 0x00000004. It is
	204	* required to account for changes caused by normal wafer processing
	205	* parameters."
	206	*/
	207	svr = get_svr();
	208	pvr = get_pvr();
a9398e01	209	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
91650b3e WD	210	(vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;
	211	__asm__ volatile ("sync");
	212	}
	213
86ea5f93 WD	214	return dramsize + dramsize2;
	215	}
	216
86ea5f93 WD	217	int checkboard (void)
86ea5f93 WD	218	{
ed1cf845 WD	219	#if defined(CONFIG_PRS200)
	220	puts ("Board: PRS200\n");
	221	#else
c81eb1f5	222	puts ("Board: MCC200\n");
ed1cf845	223	#endif
86ea5f93 WD	224	return 0;
	225	}
	226
58ad4978	227	int misc_init_r (void)
86ea5f93	228	{
6183bb9e WD	229	ulong flash_sup_end, snum;
6183bb9e WD	230
86ea5f93	231	/*
58ad4978	232	* Adjust flash start and offset to detected values
86ea5f93	233	*/
58ad4978 SR	234	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
58ad4978 SR	235	gd->bd->bi_flashoffset = 0;
86ea5f93	236
58ad4978 SR	237	/*
	238	* Check if boot FLASH isn't max size
	239	*/
6d0f6bcf	240	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
58ad4978 SR	241	/* adjust mapping */
	242	(vu_long )MPC5XXX_BOOTCS_START = (vu_long )MPC5XXX_CS0_START =
	243	START_REG(gd->bd->bi_flashstart);
	244	(vu_long )MPC5XXX_BOOTCS_STOP = (vu_long )MPC5XXX_CS0_STOP =
	245	STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
	246
	247	/*
	248	* Re-check to get correct base address
	249	*/
6d0f6bcf	250	flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
58ad4978 SR	251
	252	/*
	253	* Re-do flash protection upon new addresses
	254	*/
	255	flash_protect (FLAG_PROTECT_CLEAR,
	256	gd->bd->bi_flashstart, 0xffffffff,
6d0f6bcf	257	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
58ad4978 SR	258
	259	/* Monitor protection ON by default */
	260	flash_protect (FLAG_PROTECT_SET,
6d0f6bcf JCPV	261	CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
6d0f6bcf JCPV	262	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
58ad4978 SR	263
	264	/* Environment protection ON by default */
	265	flash_protect (FLAG_PROTECT_SET,
0e8d1586 JCPV	266	CONFIG_ENV_ADDR,
0e8d1586 JCPV	267	CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf	268	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
58ad4978 SR	269
	270	/* Redundant environment protection ON by default */
	271	flash_protect (FLAG_PROTECT_SET,
0e8d1586 JCPV	272	CONFIG_ENV_ADDR_REDUND,
0e8d1586 JCPV	273	CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
6d0f6bcf	274	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
58ad4978	275	}
86ea5f93	276
3a5e2188 WD	277	if (gd->bd->bi_flashsize > (32 << 20)) {
	278	/* Unprotect the upper bank of the Flash */
	279	(volatile int)MPC5XXX_CS0_CFG \|= (1 << 6);
	280	flash_protect (FLAG_PROTECT_CLEAR,
5d7022b0	281	flash_info[0].start[0] + flash_info[0].size / 2,
985b950a	282	(flash_info[0].start[0] - 1) + flash_info[0].size,
3a5e2188 WD	283	&flash_info[0]);
3a5e2188 WD	284	(volatile int)MPC5XXX_CS0_CFG &= ~(1 << 6);
6183bb9e WD	285	printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
6183bb9e WD	286	flash_info[0].size = 32 << 20;
16850919 WD	287	for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
16850919 WD	288	flash_info[0].start[snum] < flash_sup_end;
6183bb9e WD	289	snum++);
6183bb9e WD	290	flash_info[0].sector_count = snum;
3a5e2188 WD	291	}
3a5e2188 WD	292
787fa158	293	#ifdef CONFIG_AUTO_UPDATE
f11033e7	294	do_auto_update();
787fa158	295	#endif
86ea5f93 WD	296	return (0);
	297	}
	298
	299	#ifdef CONFIG_PCI
	300	static struct pci_controller hose;
	301
	302	extern void pci_mpc5xxx_init(struct pci_controller *);
	303
	304	void pci_init_board(void)
	305	{
	306	pci_mpc5xxx_init(&hose);
	307	}
	308	#endif
	309
d39b5741	310	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
86ea5f93 WD	311
	312	void init_ide_reset (void)
	313	{
	314	debug ("init_ide_reset\n");
	315
	316	}
	317
	318	void ide_set_reset (int idereset)
	319	{
	320	debug ("ide_reset(%d)\n", idereset);
	321
	322	}
d39b5741	323	#endif
86ea5f93	324
3fe00109	325	#if defined(CONFIG_CMD_DOC)
86ea5f93 WD	326	void doc_init (void)
86ea5f93 WD	327	{
6d0f6bcf	328	doc_probe (CONFIG_SYS_DOC_BASE);
86ea5f93 WD	329	}
86ea5f93 WD	330	#endif