[people/ms/u-boot.git] / board / miromico / hammerhead / hammerhead.c

/*
 * Copyright (C) 2008 Miromico AG
 *
 * Mostly copied form atmel ATNGW100 sources
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <netdev.h>

#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>

DECLARE_GLOBAL_DATA_PTR;

struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
	{
		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
		.phys		= (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
					| MMU_VMR_CACHE_NONE,
	}, {
		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
		.nr_pages	= EBI_SDRAM_SIZE >> PAGE_SHIFT,
		.phys		= (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
					| MMU_VMR_CACHE_WRBACK,
	},
};

static const struct sdram_config sdram_config = {
	.data_bits	= SDRAM_DATA_32BIT,
	.row_bits	= 13,
	.col_bits	= 9,
	.bank_bits	= 2,
	.cas		= 3,
	.twr		= 2,
	.trc		= 7,
	.trp		= 2,
	.trcd		= 2,
	.tras		= 5,
	.txsr		= 5,
	/* 7.81 us */
	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
};

#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
	return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
		bis->bi_phy_id[0]);
}
#endif

int board_early_init_f(void)
{
	/* Enable SDRAM in the EBI mux */
	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));

	portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
	portmux_enable_usart1(PORTMUX_DRIVE_MIN);

#if defined(CONFIG_MACB)
	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
	return 0;
}

phys_size_t initdram(int board_type)
{
	unsigned long expected_size;
	unsigned long actual_size;
	void *sdram_base;

	sdram_base = uncached(EBI_SDRAM_BASE);

	expected_size = sdram_init(sdram_base, &sdram_config);
	actual_size = get_ram_size(sdram_base, expected_size);

	if (expected_size != actual_size)
		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
		       actual_size >> 20, expected_size >> 20);

	return actual_size;
}

int board_early_init_r(void)
{
	gd->bd->bi_phy_id[0] = 0x01;
	return 0;
}

int board_postclk_init(void)
{
	/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
	gclk_enable_output(3, PORTMUX_DRIVE_LOW);
	gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
	return 0;
}
Commit	Line	Data
5c374c9e JM	1	/*
	2	* Copyright (C) 2008 Miromico AG
	3	*
	4	* Mostly copied form atmel ATNGW100 sources
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
5c374c9e JM	7	*/
5c374c9e JM	8
5c374c9e	9	#include <common.h>
89973f8a	10	#include <netdev.h>
5c374c9e JM	11
	12	#include <asm/io.h>
	13	#include <asm/sdram.h>
	14	#include <asm/arch/clk.h>
5c374c9e	15	#include <asm/arch/hmatrix.h>
5d73bc7a	16	#include <asm/arch/hardware.h>
1f36f73f	17	#include <asm/arch/mmu.h>
ab0df36f	18	#include <asm/arch/portmux.h>
5c374c9e JM	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
1f36f73f HS	22	struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
	23	{
	24	.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
	25	.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
	26	.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
	27	\| MMU_VMR_CACHE_NONE,
	28	}, {
	29	.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
	30	.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
	31	.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
	32	\| MMU_VMR_CACHE_WRBACK,
	33	},
	34	};
	35
5c374c9e JM	36	static const struct sdram_config sdram_config = {
	37	.data_bits = SDRAM_DATA_32BIT,
	38	.row_bits = 13,
	39	.col_bits = 9,
	40	.bank_bits = 2,
	41	.cas = 3,
	42	.twr = 2,
	43	.trc = 7,
	44	.trp = 2,
	45	.trcd = 2,
	46	.tras = 5,
	47	.txsr = 5,
	48	/* 7.81 us */
	49	.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
	50	};
	51
5c374c9e JM	52	#ifdef CONFIG_CMD_NET
	53	int board_eth_init(bd_t *bis)
	54	{
f4278b71 AB	55	return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
f4278b71 AB	56	bis->bi_phy_id[0]);
5c374c9e JM	57	}
	58	#endif
	59
	60	int board_early_init_f(void)
	61	{
	62	/* Enable SDRAM in the EBI mux */
	63	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
	64
ab0df36f HS	65	portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
ab0df36f HS	66	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
5c374c9e JM	67
5c374c9e JM	68	#if defined(CONFIG_MACB)
ab0df36f	69	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
5c374c9e JM	70	#endif
5c374c9e JM	71	#if defined(CONFIG_MMC)
ab0df36f	72	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
5c374c9e JM	73	#endif
	74	return 0;
	75	}
	76
	77	phys_size_t initdram(int board_type)
	78	{
	79	unsigned long expected_size;
	80	unsigned long actual_size;
	81	void *sdram_base;
	82
9cec2fc2	83	sdram_base = uncached(EBI_SDRAM_BASE);
5c374c9e JM	84
	85	expected_size = sdram_init(sdram_base, &sdram_config);
	86	actual_size = get_ram_size(sdram_base, expected_size);
	87
5c374c9e JM	88	if (expected_size != actual_size)
	89	printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
	90	actual_size >> 20, expected_size >> 20);
	91
	92	return actual_size;
	93	}
	94
25e6854d	95	int board_early_init_r(void)
5c374c9e JM	96	{
5c374c9e JM	97	gd->bd->bi_phy_id[0] = 0x01;
25e6854d	98	return 0;
5c374c9e JM	99	}
5c374c9e JM	100
36d375fa	101	int board_postclk_init(void)
5c374c9e JM	102	{
5c374c9e JM	103	/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
abdde2b1 HS	104	gclk_enable_output(3, PORTMUX_DRIVE_LOW);
abdde2b1 HS	105	gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
36d375fa	106	return 0;
5c374c9e	107	}