[people/ms/u-boot.git] / board / mpc8349itx / pci.c

/*
 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <asm/mmu.h>
#include <asm/global_data.h>
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc8349itx_config_table[] = {
	{
	 PCI_ANY_ID,
	 PCI_ANY_ID,
	 PCI_ANY_ID,
	 PCI_ANY_ID,
	 PCI_IDSEL_NUMBER,
	 PCI_ANY_ID,
	 pci_cfgfunc_config_device,
	 {
	  PCI_ENET0_IOADDR,
	  PCI_ENET0_MEMADDR,
	  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
	 },
	{}
};
#endif

static struct pci_controller pci_hose[] = {
	{
#ifndef CONFIG_PCI_PNP
	      config_table:pci_mpc8349itx_config_table,
#endif
	 },
	{
#ifndef CONFIG_PCI_PNP
	      config_table:pci_mpc8349itx_config_table,
#endif
	 }
};

/**************************************************************************
 * pci_init_board()
 *
 * NOTICE: PCI2 is not currently supported
 *
 */
void pci_init_board(void)
{
	volatile immap_t *immr;
	volatile clk83xx_t *clk;
	volatile law83xx_t *pci_law;
	volatile pot83xx_t *pci_pot;
	volatile pcictrl83xx_t *pci_ctrl;
	volatile pciconf83xx_t *pci_conf;
	u8 reg8;
	u16 reg16;
	u32 reg32;
	u32 dev;
	struct pci_controller *hose;

	immr = (immap_t *) CFG_IMMR;
	clk = (clk83xx_t *) & immr->clk;
	pci_law = immr->sysconf.pcilaw;
	pci_pot = immr->ios.pot;
	pci_ctrl = immr->pci_ctrl;
	pci_conf = immr->pci_conf;

	hose = &pci_hose[0];

	/*
	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
	 */

	reg32 = clk->occr;
	udelay(2000);

#ifdef CONFIG_HARD_I2C
	i2c_set_bus_num(1);
	/* Read the PCI_M66EN jumper setting */
	if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
	    (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
		if (reg8 & I2C_8574_PCI66)
			clk->occr = 0xff000000;	/* 66 MHz PCI */
		else
			clk->occr = 0xff600001;	/* 33 MHz PCI */
	} else {
		clk->occr = 0xff600001;	/* 33 MHz PCI */
	}
#else
	clk->occr = 0xff000000;	/* 66 MHz PCI */
#endif

	udelay(2000);

	/*
	 * Release PCI RST Output signal
	 */
	pci_ctrl[0].gcr = 0;
	udelay(2000);
	pci_ctrl[0].gcr = 1;

#ifdef CONFIG_MPC83XX_PCI2
	pci_ctrl[1].gcr = 0;
	udelay(2000);
	pci_ctrl[1].gcr = 1;
#endif

	/* We need to wait at least a 1sec based on PCI specs */
	{
		int i;

		for (i = 0; i < 1000; i++)
			udelay(1000);
	}

	/*
	 * Configure PCI Local Access Windows
	 */
	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;

	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;

	/*
	 * Configure PCI Outbound Translation Windows
	 */

	/* PCI1 mem space - prefetch */
	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;

	/* PCI1 IO space */
	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;

	/* PCI1 mmio - non-prefetch mem space */
	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;

	/*
	 * Configure PCI Inbound Translation Windows
	 */

	/* we need RAM mapped to PCI space for the devices to
	 * access main memory */
	pci_ctrl[0].pitar1 = 0x0;
	pci_ctrl[0].pibar1 = 0x0;
	pci_ctrl[0].piebar1 = 0x0;
	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
	    PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* PCI memory prefetch space */
	pci_set_region(hose->regions + 0,
		       CFG_PCI1_MEM_BASE,
		       CFG_PCI1_MEM_PHYS,
		       CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CFG_PCI1_MMIO_BASE,
		       CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 2,
		       CFG_PCI1_IO_BASE,
		       CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);

	/* System memory space */
	pci_set_region(hose->regions + 3,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);

	hose->region_count = 4;

	pci_setup_indirect(hose,
			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));

	pci_register_hose(hose);

	/*
	 * Write to Command register
	 */
	reg16 = 0xff;
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);

#ifdef CONFIG_MPC83XX_PCI2
	hose = &pci_hose[1];

	/*
	 * Configure PCI Outbound Translation Windows
	 */

	/* PCI2 mem space - prefetch */
	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;

	/* PCI2 IO space */
	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;

	/* PCI2 mmio - non-prefetch mem space */
	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;

	/*
	 * Configure PCI Inbound Translation Windows
	 */

	/* we need RAM mapped to PCI space for the devices to
	 * access main memory */
	pci_ctrl[1].pitar1 = 0x0;
	pci_ctrl[1].pibar1 = 0x0;
	pci_ctrl[1].piebar1 = 0x0;
	pci_ctrl[1].piwar1 =
	    PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
	    (__ilog2(gd->ram_size) - 1);

	hose->first_busno = pci_hose[0].last_busno + 1;
	hose->last_busno = 0xff;

	/* PCI memory prefetch space */
	pci_set_region(hose->regions + 0,
		       CFG_PCI2_MEM_BASE,
		       CFG_PCI2_MEM_PHYS,
		       CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CFG_PCI2_MMIO_BASE,
		       CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 2,
		       CFG_PCI2_IO_BASE,
		       CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);

	/* System memory space */
	pci_set_region(hose->regions + 3,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);

	hose->region_count = 4;

	pci_setup_indirect(hose,
			   (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));

	pci_register_hose(hose);

	/*
	 * Write to Command register
	 */
	reg16 = 0xff;
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);
#endif
}

#endif				/* CONFIG_PCI */
#ifdef CONFIG_OF_FLAT_TREE
void
ft_pci_setup(void *blob, bd_t *bd)
{
       	u32 *p;
       	int len;

       	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
       	if (p != NULL) {
		p[0] = pci_hose[0].first_busno;
		p[1] = pci_hose[0].last_busno;
       	}

#ifdef CONFIG_MPC83XX_PCI2
	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
	if (p != NULL) {
		p[0] = pci_hose[1].first_busno;
		p[1] = pci_hose[1].last_busno;
	}
#endif
}
#endif /* CONFIG_OF_FLAT_TREE */
Commit	Line	Data
2ad6b513 TT	1	/*
	2	* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24
	25	#ifdef CONFIG_PCI
	26
	27	#include <asm/mmu.h>
	28	#include <asm/global_data.h>
	29	#include <pci.h>
	30	#include <asm/mpc8349_pci.h>
	31	#include <i2c.h>
be5e6181 TT	32	#if defined(CONFIG_OF_FLAT_TREE)
	33	#include <ft_build.h>
	34	#endif
2ad6b513 TT	35
	36	DECLARE_GLOBAL_DATA_PTR;
	37
	38	/* System RAM mapped to PCI space */
	39	#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
	40	#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
	41
	42	#ifndef CONFIG_PCI_PNP
	43	static struct pci_config_table pci_mpc8349itx_config_table[] = {
	44	{
	45	PCI_ANY_ID,
	46	PCI_ANY_ID,
	47	PCI_ANY_ID,
	48	PCI_ANY_ID,
	49	PCI_IDSEL_NUMBER,
	50	PCI_ANY_ID,
	51	pci_cfgfunc_config_device,
	52	{
	53	PCI_ENET0_IOADDR,
	54	PCI_ENET0_MEMADDR,
	55	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER}
	56	},
	57	{}
	58	};
	59	#endif
	60
	61	static struct pci_controller pci_hose[] = {
	62	{
	63	#ifndef CONFIG_PCI_PNP
	64	config_table:pci_mpc8349itx_config_table,
	65	#endif
	66	},
	67	{
	68	#ifndef CONFIG_PCI_PNP
	69	config_table:pci_mpc8349itx_config_table,
	70	#endif
	71	}
	72	};
	73
	74	/**************************************************************************
	75	* pci_init_board()
	76	*
	77	* NOTICE: PCI2 is not currently supported
	78	*
	79	*/
	80	void pci_init_board(void)
	81	{
	82	volatile immap_t *immr;
	83	volatile clk83xx_t *clk;
	84	volatile law83xx_t *pci_law;
	85	volatile pot83xx_t *pci_pot;
	86	volatile pcictrl83xx_t *pci_ctrl;
	87	volatile pciconf83xx_t *pci_conf;
	88	u8 reg8;
	89	u16 reg16;
	90	u32 reg32;
	91	u32 dev;
	92	struct pci_controller *hose;
	93
d239d74b	94	immr = (immap_t *) CFG_IMMR;
2ad6b513 TT	95	clk = (clk83xx_t *) & immr->clk;
	96	pci_law = immr->sysconf.pcilaw;
	97	pci_pot = immr->ios.pot;
	98	pci_ctrl = immr->pci_ctrl;
	99	pci_conf = immr->pci_conf;
	100
	101	hose = &pci_hose[0];
	102
	103	/*
	104	* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
	105	*/
	106
	107	reg32 = clk->occr;
	108	udelay(2000);
	109
	110	#ifdef CONFIG_HARD_I2C
be5e6181	111	i2c_set_bus_num(1);
2ad6b513 TT	112	/* Read the PCI_M66EN jumper setting */
	113	if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) \|\|
	114	(i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
	115	if (reg8 & I2C_8574_PCI66)
	116	clk->occr = 0xff000000; /* 66 MHz PCI */
	117	else
	118	clk->occr = 0xff600001; /* 33 MHz PCI */
	119	} else {
	120	clk->occr = 0xff600001; /* 33 MHz PCI */
	121	}
	122	#else
	123	clk->occr = 0xff000000; /* 66 MHz PCI */
	124	#endif
	125
	126	udelay(2000);
	127
	128	/*
	129	* Release PCI RST Output signal
	130	*/
	131	pci_ctrl[0].gcr = 0;
	132	udelay(2000);
	133	pci_ctrl[0].gcr = 1;
	134
	135	#ifdef CONFIG_MPC83XX_PCI2
	136	pci_ctrl[1].gcr = 0;
	137	udelay(2000);
	138	pci_ctrl[1].gcr = 1;
	139	#endif
	140
	141	/* We need to wait at least a 1sec based on PCI specs */
	142	{
	143	int i;
	144
	145	for (i = 0; i < 1000; i++)
	146	udelay(1000);
	147	}
	148
	149	/*
	150	* Configure PCI Local Access Windows
	151	*/
	152	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
	153	pci_law[0].ar = LAWAR_EN \| LAWAR_SIZE_1G;
	154
	155	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
98883332	156	pci_law[1].ar = LAWAR_EN \| LAWAR_SIZE_32M;
2ad6b513 TT	157
	158	/*
	159	* Configure PCI Outbound Translation Windows
	160	*/
	161
	162	/* PCI1 mem space - prefetch */
	163	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
	164	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
98883332	165	pci_pot[0].pocmr = POCMR_EN \| POCMR_PREFETCH_EN \| POCMR_CM_256M;
2ad6b513 TT	166
	167	/* PCI1 IO space */
	168	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
	169	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
98883332	170	pci_pot[1].pocmr = POCMR_EN \| POCMR_IO \| POCMR_CM_16M;
2ad6b513 TT	171
	172	/* PCI1 mmio - non-prefetch mem space */
	173	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
	174	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
98883332	175	pci_pot[2].pocmr = POCMR_EN \| POCMR_CM_256M;
2ad6b513 TT	176
	177	/*
	178	* Configure PCI Inbound Translation Windows
	179	*/
	180
	181	/* we need RAM mapped to PCI space for the devices to
	182	* access main memory */
	183	pci_ctrl[0].pitar1 = 0x0;
	184	pci_ctrl[0].pibar1 = 0x0;
	185	pci_ctrl[0].piebar1 = 0x0;
	186	pci_ctrl[0].piwar1 = PIWAR_EN \| PIWAR_PF \| PIWAR_RTT_SNOOP \|
	187	PIWAR_WTT_SNOOP \| (__ilog2(gd->ram_size) - 1);
	188
	189	hose->first_busno = 0;
	190	hose->last_busno = 0xff;
	191
	192	/* PCI memory prefetch space */
	193	pci_set_region(hose->regions + 0,
	194	CFG_PCI1_MEM_BASE,
	195	CFG_PCI1_MEM_PHYS,
	196	CFG_PCI1_MEM_SIZE, PCI_REGION_MEM \| PCI_REGION_PREFETCH);
	197
	198	/* PCI memory space */
	199	pci_set_region(hose->regions + 1,
	200	CFG_PCI1_MMIO_BASE,
	201	CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
	202
	203	/* PCI IO space */
	204	pci_set_region(hose->regions + 2,
	205	CFG_PCI1_IO_BASE,
	206	CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
	207
	208	/* System memory space */
	209	pci_set_region(hose->regions + 3,
	210	CONFIG_PCI_SYS_MEM_BUS,
	211	CONFIG_PCI_SYS_MEM_PHYS,
	212	gd->ram_size, PCI_REGION_MEM \| PCI_REGION_MEMORY);
	213
	214	hose->region_count = 4;
	215
	216	pci_setup_indirect(hose,
d239d74b	217	(CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
2ad6b513 TT	218
	219	pci_register_hose(hose);
	220
	221	/*
	222	* Write to Command register
	223	*/
	224	reg16 = 0xff;
	225	dev = PCI_BDF(hose->first_busno, 0, 0);
	226	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	227	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	228	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
	229
	230	/*
	231	* Clear non-reserved bits in status register.
	232	*/
	233	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	234	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	235	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	236
	237	#ifdef CONFIG_PCI_SCAN_SHOW
	238	printf("PCI: Bus Dev VenId DevId Class Int\n");
	239	#endif
	240	/*
	241	* Hose scan.
	242	*/
	243	hose->last_busno = pci_hose_scan(hose);
	244
	245	#ifdef CONFIG_MPC83XX_PCI2
	246	hose = &pci_hose[1];
	247
	248	/*
	249	* Configure PCI Outbound Translation Windows
	250	*/
	251
	252	/* PCI2 mem space - prefetch */
	253	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
	254	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
98883332	255	pci_pot[3].pocmr = POCMR_EN \| POCMR_PCI2 \| POCMR_PREFETCH_EN \| POCMR_CM_256M;
2ad6b513 TT	256
	257	/* PCI2 IO space */
	258	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
	259	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
98883332	260	pci_pot[4].pocmr = POCMR_EN \| POCMR_PCI2 \| POCMR_IO \| POCMR_CM_16M;
2ad6b513 TT	261
	262	/* PCI2 mmio - non-prefetch mem space */
	263	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
	264	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
98883332	265	pci_pot[5].pocmr = POCMR_EN \| POCMR_PCI2 \| POCMR_CM_256M;
2ad6b513 TT	266
	267	/*
	268	* Configure PCI Inbound Translation Windows
	269	*/
	270
	271	/* we need RAM mapped to PCI space for the devices to
	272	* access main memory */
	273	pci_ctrl[1].pitar1 = 0x0;
	274	pci_ctrl[1].pibar1 = 0x0;
	275	pci_ctrl[1].piebar1 = 0x0;
	276	pci_ctrl[1].piwar1 =
	277	PIWAR_EN \| PIWAR_PF \| PIWAR_RTT_SNOOP \| PIWAR_WTT_SNOOP \|
	278	(__ilog2(gd->ram_size) - 1);
	279
	280	hose->first_busno = pci_hose[0].last_busno + 1;
	281	hose->last_busno = 0xff;
	282
	283	/* PCI memory prefetch space */
	284	pci_set_region(hose->regions + 0,
	285	CFG_PCI2_MEM_BASE,
	286	CFG_PCI2_MEM_PHYS,
	287	CFG_PCI2_MEM_SIZE, PCI_REGION_MEM \| PCI_REGION_PREFETCH);
	288
	289	/* PCI memory space */
	290	pci_set_region(hose->regions + 1,
	291	CFG_PCI2_MMIO_BASE,
	292	CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
	293
	294	/* PCI IO space */
	295	pci_set_region(hose->regions + 2,
	296	CFG_PCI2_IO_BASE,
	297	CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
	298
	299	/* System memory space */
	300	pci_set_region(hose->regions + 3,
	301	CONFIG_PCI_SYS_MEM_BUS,
	302	CONFIG_PCI_SYS_MEM_PHYS,
	303	gd->ram_size, PCI_REGION_MEM \| PCI_REGION_MEMORY);
	304
	305	hose->region_count = 4;
	306
	307	pci_setup_indirect(hose,
d239d74b	308	(CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));
2ad6b513 TT	309
	310	pci_register_hose(hose);
	311
	312	/*
	313	* Write to Command register
	314	*/
	315	reg16 = 0xff;
	316	dev = PCI_BDF(hose->first_busno, 0, 0);
	317	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
	318	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	319	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
	320
	321	/*
	322	* Clear non-reserved bits in status register.
	323	*/
	324	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	325	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	326	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
	327
	328	/*
	329	* Hose scan.
	330	*/
	331	hose->last_busno = pci_hose_scan(hose);
	332	#endif
	333	}
	334
	335	#endif /* CONFIG_PCI */
bf0b542d KP	336	#ifdef CONFIG_OF_FLAT_TREE
	337	void
	338	ft_pci_setup(void blob, bd_t bd)
	339	{
	340	u32 *p;
	341	int len;
	342
	343	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
	344	if (p != NULL) {
	345	p[0] = pci_hose[0].first_busno;
	346	p[1] = pci_hose[0].last_busno;
	347	}
	348
	349	#ifdef CONFIG_MPC83XX_PCI2
	350	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
	351	if (p != NULL) {
	352	p[0] = pci_hose[1].first_busno;
	353	p[1] = pci_hose[1].last_busno;
	354	}
	355	#endif
	356	}
	357	#endif /* CONFIG_OF_FLAT_TREE */