[people/ms/u-boot.git] / board / mpc8568mds / mpc8568mds.c

/*
 * Copyright 2007 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
#include <i2c.h>
#include <ioports.h>

#include "bcsr.h"

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* GETH1 */
	{4, 10, 1, 0, 2}, /* TxD0 */
	{4,  9, 1, 0, 2}, /* TxD1 */
	{4,  8, 1, 0, 2}, /* TxD2 */
	{4,  7, 1, 0, 2}, /* TxD3 */
	{4, 23, 1, 0, 2}, /* TxD4 */
	{4, 22, 1, 0, 2}, /* TxD5 */
	{4, 21, 1, 0, 2}, /* TxD6 */
	{4, 20, 1, 0, 2}, /* TxD7 */
	{4, 15, 2, 0, 2}, /* RxD0 */
	{4, 14, 2, 0, 2}, /* RxD1 */
	{4, 13, 2, 0, 2}, /* RxD2 */
	{4, 12, 2, 0, 2}, /* RxD3 */
	{4, 29, 2, 0, 2}, /* RxD4 */
	{4, 28, 2, 0, 2}, /* RxD5 */
	{4, 27, 2, 0, 2}, /* RxD6 */
	{4, 26, 2, 0, 2}, /* RxD7 */
	{4, 11, 1, 0, 2}, /* TX_EN */
	{4, 24, 1, 0, 2}, /* TX_ER */
	{4, 16, 2, 0, 2}, /* RX_DV */
	{4, 30, 2, 0, 2}, /* RX_ER */
	{4, 17, 2, 0, 2}, /* RX_CLK */
	{4, 19, 1, 0, 2}, /* GTX_CLK */
	{1, 31, 2, 0, 3}, /* GTX125 */

	/* GETH2 */
	{5, 10, 1, 0, 2}, /* TxD0 */
	{5,  9, 1, 0, 2}, /* TxD1 */
	{5,  8, 1, 0, 2}, /* TxD2 */
	{5,  7, 1, 0, 2}, /* TxD3 */
	{5, 23, 1, 0, 2}, /* TxD4 */
	{5, 22, 1, 0, 2}, /* TxD5 */
	{5, 21, 1, 0, 2}, /* TxD6 */
	{5, 20, 1, 0, 2}, /* TxD7 */
	{5, 15, 2, 0, 2}, /* RxD0 */
	{5, 14, 2, 0, 2}, /* RxD1 */
	{5, 13, 2, 0, 2}, /* RxD2 */
	{5, 12, 2, 0, 2}, /* RxD3 */
	{5, 29, 2, 0, 2}, /* RxD4 */
	{5, 28, 2, 0, 2}, /* RxD5 */
	{5, 27, 2, 0, 3}, /* RxD6 */
	{5, 26, 2, 0, 2}, /* RxD7 */
	{5, 11, 1, 0, 2}, /* TX_EN */
	{5, 24, 1, 0, 2}, /* TX_ER */
	{5, 16, 2, 0, 2}, /* RX_DV */
	{5, 30, 2, 0, 2}, /* RX_ER */
	{5, 17, 2, 0, 2}, /* RX_CLK */
	{5, 19, 1, 0, 2}, /* GTX_CLK */
	{1, 31, 2, 0, 3}, /* GTX125 */
	{4,  6, 3, 0, 2}, /* MDIO */
	{4,  5, 1, 0, 2}, /* MDC */
	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};


#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

extern long int spd_sdram(void);

void local_bus_init(void);
void sdram_init(void);

int board_early_init_f (void)
{
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	enable_8568mds_duart();
	enable_8568mds_flash_write();
#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
	enable_8568mds_qe_mdio();
#endif

#ifdef CFG_I2C2_OFFSET
	/* Enable I2C2_SCL and I2C2_SDA */
	volatile struct par_io *port_c;
	port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
	port_c->cpdir2 |= 0x0f000000;
	port_c->cppar2 &= ~0x0f000000;
	port_c->cppar2 |= 0x0a000000;
#endif

	return 0;
}

int checkboard (void)
{
	printf ("Board: 8568 MDS\n");

	return 0;
}

long int
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
		/*
		 * Work around to stabilize DDR DLL MSYNC_IN.
		 * Errata DDR9 seems to have been fixed.
		 * This is now the workaround for Errata DDR11:
		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
		 */

		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);

		gur->ddrdllcr = 0x81000000;
		asm("sync;isync;msync");
		udelay(200);
	}
#endif
	dram_size = spd_sdram();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif
	/*
	 * SDRAM Initialization
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = &immap->im_lbc;

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & 0x0f) * 2;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	gur->lbiuiplldcr1 = 0x00078080;
	if (clkdiv == 16) {
		gur->lbiuiplldcr0 = 0x7c0f1bf0;
	} else if (clkdiv == 8) {
		gur->lbiuiplldcr0 = 0x6c0f1bf0;
	} else if (clkdiv == 4) {
		gur->lbiuiplldcr0 = 0x5c0f1bf0;
	}

	lbc->lcrr |= 0x00030000;

	asm("sync;isync;msync");
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void
sdram_init(void)
{
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)

	uint idx;
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
	uint lsdmr_common;

	puts("    SDRAM: ");

	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	lbc->or2 = CFG_OR2_PRELIM;
	asm("msync");

	lbc->br2 = CFG_BR2_PRELIM;
	asm("msync");

	lbc->lbcr = CFG_LBC_LBCR;
	asm("msync");


	lbc->lsrt = CFG_LBC_LSRT;
	lbc->mrtpr = CFG_LBC_MRTPR;
	asm("msync");

	/*
	 * MPC8568 uses "new" 15-16 style addressing.
	 */
	lsdmr_common = CFG_LBC_LSDMR_COMMON;
	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;

	/*
	 * Issue PRECHARGE ALL command.
	 */
	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue NORMAL OP command.
	 */
	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CFG_MEMTEST_START;
	uint *pend = (uint *) CFG_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CFG_MEMTEST_START,
	       CFG_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#if defined(CONFIG_PCI)
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc8568mds_config_table[] = {
	{
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 pci_cfgfunc_config_device,
	 {PCI_ENET0_IOADDR,
	  PCI_ENET0_MEMADDR,
	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
	 },
	{}
};
#endif

static struct pci_controller hose[] = {
	{
#ifndef CONFIG_PCI_PNP
	config_table: pci_mpc8568mds_config_table,
#endif
	}
};

#endif	/* CONFIG_PCI */

/*
 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
 */
void
pib_init(void)
{
	u8 val8, orig_i2c_bus;
	/*
	 * Assign PIB PMC2/3 to PCI bus
	 */

	/*switch temporarily to I2C bus #2 */
	orig_i2c_bus = i2c_get_bus_num();
	i2c_set_bus_num(1);

	val8 = 0x00;
	i2c_write(0x23, 0x6, 1, &val8, 1);
	i2c_write(0x23, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x23, 0x2, 1, &val8, 1);
	i2c_write(0x23, 0x3, 1, &val8, 1);

	val8 = 0x00;
	i2c_write(0x26, 0x6, 1, &val8, 1);
	val8 = 0x34;
	i2c_write(0x26, 0x7, 1, &val8, 1);
	val8 = 0xf9;
	i2c_write(0x26, 0x2, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x26, 0x3, 1, &val8, 1);

	val8 = 0x00;
	i2c_write(0x27, 0x6, 1, &val8, 1);
	i2c_write(0x27, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x27, 0x2, 1, &val8, 1);
	val8 = 0xef;
	i2c_write(0x27, 0x3, 1, &val8, 1);

	asm("eieio");
}

void
pci_init_board(void)
{
#ifdef CONFIG_PCI
	pib_init();
	pci_mpc85xx_init(hose);
#endif
}
Commit	Line	Data
67431059 AF	1	/*
	2	* Copyright 2007 Freescale Semiconductor.
	3	*
	4	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <pci.h>
	27	#include <asm/processor.h>
	28	#include <asm/immap_85xx.h>
	29	#include <spd.h>
c59e4091	30	#include <i2c.h>
da9d4610	31	#include <ioports.h>
67431059 AF	32
	33	#include "bcsr.h"
	34
da9d4610 AF	35	const qe_iop_conf_t qe_iop_conf_tab[] = {
	36	/* GETH1 */
	37	{4, 10, 1, 0, 2}, /* TxD0 */
	38	{4, 9, 1, 0, 2}, /* TxD1 */
	39	{4, 8, 1, 0, 2}, /* TxD2 */
	40	{4, 7, 1, 0, 2}, /* TxD3 */
	41	{4, 23, 1, 0, 2}, /* TxD4 */
	42	{4, 22, 1, 0, 2}, /* TxD5 */
	43	{4, 21, 1, 0, 2}, /* TxD6 */
	44	{4, 20, 1, 0, 2}, /* TxD7 */
	45	{4, 15, 2, 0, 2}, /* RxD0 */
	46	{4, 14, 2, 0, 2}, /* RxD1 */
	47	{4, 13, 2, 0, 2}, /* RxD2 */
	48	{4, 12, 2, 0, 2}, /* RxD3 */
	49	{4, 29, 2, 0, 2}, /* RxD4 */
	50	{4, 28, 2, 0, 2}, /* RxD5 */
	51	{4, 27, 2, 0, 2}, /* RxD6 */
	52	{4, 26, 2, 0, 2}, /* RxD7 */
	53	{4, 11, 1, 0, 2}, /* TX_EN */
	54	{4, 24, 1, 0, 2}, /* TX_ER */
	55	{4, 16, 2, 0, 2}, /* RX_DV */
	56	{4, 30, 2, 0, 2}, /* RX_ER */
	57	{4, 17, 2, 0, 2}, /* RX_CLK */
	58	{4, 19, 1, 0, 2}, /* GTX_CLK */
	59	{1, 31, 2, 0, 3}, /* GTX125 */
	60
	61	/* GETH2 */
	62	{5, 10, 1, 0, 2}, /* TxD0 */
	63	{5, 9, 1, 0, 2}, /* TxD1 */
	64	{5, 8, 1, 0, 2}, /* TxD2 */
	65	{5, 7, 1, 0, 2}, /* TxD3 */
	66	{5, 23, 1, 0, 2}, /* TxD4 */
	67	{5, 22, 1, 0, 2}, /* TxD5 */
	68	{5, 21, 1, 0, 2}, /* TxD6 */
	69	{5, 20, 1, 0, 2}, /* TxD7 */
	70	{5, 15, 2, 0, 2}, /* RxD0 */
	71	{5, 14, 2, 0, 2}, /* RxD1 */
	72	{5, 13, 2, 0, 2}, /* RxD2 */
	73	{5, 12, 2, 0, 2}, /* RxD3 */
	74	{5, 29, 2, 0, 2}, /* RxD4 */
	75	{5, 28, 2, 0, 2}, /* RxD5 */
	76	{5, 27, 2, 0, 3}, /* RxD6 */
	77	{5, 26, 2, 0, 2}, /* RxD7 */
	78	{5, 11, 1, 0, 2}, /* TX_EN */
	79	{5, 24, 1, 0, 2}, /* TX_ER */
	80	{5, 16, 2, 0, 2}, /* RX_DV */
	81	{5, 30, 2, 0, 2}, /* RX_ER */
	82	{5, 17, 2, 0, 2}, /* RX_CLK */
	83	{5, 19, 1, 0, 2}, /* GTX_CLK */
	84	{1, 31, 2, 0, 3}, /* GTX125 */
	85	{4, 6, 3, 0, 2}, /* MDIO */
	86	{4, 5, 1, 0, 2}, /* MDC */
	87	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	88	};
	89
67431059 AF	90
	91	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	92	extern void ddr_enable_ecc(unsigned int dram_size);
	93	#endif
	94
	95	extern long int spd_sdram(void);
	96
	97	void local_bus_init(void);
	98	void sdram_init(void);
	99
	100	int board_early_init_f (void)
	101	{
	102	/*
	103	* Initialize local bus.
	104	*/
	105	local_bus_init ();
	106
	107	enable_8568mds_duart();
	108	enable_8568mds_flash_write();
da9d4610 AF	109	#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
	110	enable_8568mds_qe_mdio();
	111	#endif
67431059	112
c59e4091 HW	113	#ifdef CFG_I2C2_OFFSET
	114	/* Enable I2C2_SCL and I2C2_SDA */
	115	volatile struct par_io *port_c;
	116	port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
	117	port_c->cpdir2 \|= 0x0f000000;
	118	port_c->cppar2 &= ~0x0f000000;
	119	port_c->cppar2 \|= 0x0a000000;
	120	#endif
	121
67431059 AF	122	return 0;
	123	}
	124
	125	int checkboard (void)
	126	{
	127	printf ("Board: 8568 MDS\n");
	128
	129	return 0;
	130	}
	131
	132	long int
	133	initdram(int board_type)
	134	{
	135	long dram_size = 0;
67431059 AF	136
	137	puts("Initializing\n");
	138
	139	#if defined(CONFIG_DDR_DLL)
	140	{
	141	/*
	142	* Work around to stabilize DDR DLL MSYNC_IN.
	143	* Errata DDR9 seems to have been fixed.
	144	* This is now the workaround for Errata DDR11:
	145	* Override DLL = 1, Course Adj = 1, Tap Select = 0
	146	*/
	147
f59b55a5	148	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
67431059 AF	149
	150	gur->ddrdllcr = 0x81000000;
	151	asm("sync;isync;msync");
	152	udelay(200);
	153	}
	154	#endif
	155	dram_size = spd_sdram();
	156
	157	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	158	/*
	159	* Initialize and enable DDR ECC.
	160	*/
	161	ddr_enable_ecc(dram_size);
	162	#endif
	163	/*
	164	* SDRAM Initialization
	165	*/
	166	sdram_init();
	167
	168	puts(" DDR: ");
	169	return dram_size;
	170	}
	171
	172	/*
	173	* Initialize Local Bus
	174	*/
	175	void
	176	local_bus_init(void)
	177	{
	178	volatile immap_t immap = (immap_t )CFG_IMMR;
f59b55a5	179	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
67431059 AF	180	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
	181
	182	uint clkdiv;
	183	uint lbc_hz;
	184	sys_info_t sysinfo;
	185
	186	get_sys_info(&sysinfo);
	187	clkdiv = (lbc->lcrr & 0x0f) * 2;
	188	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	189
	190	gur->lbiuiplldcr1 = 0x00078080;
	191	if (clkdiv == 16) {
	192	gur->lbiuiplldcr0 = 0x7c0f1bf0;
	193	} else if (clkdiv == 8) {
	194	gur->lbiuiplldcr0 = 0x6c0f1bf0;
	195	} else if (clkdiv == 4) {
	196	gur->lbiuiplldcr0 = 0x5c0f1bf0;
	197	}
	198
	199	lbc->lcrr \|= 0x00030000;
	200
	201	asm("sync;isync;msync");
	202	}
	203
	204	/*
	205	* Initialize SDRAM memory on the Local Bus.
	206	*/
	207	void
	208	sdram_init(void)
	209	{
	210	#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
	211
	212	uint idx;
	213	volatile immap_t immap = (immap_t )CFG_IMMR;
	214	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
	215	uint sdram_addr = (uint )CFG_LBC_SDRAM_BASE;
	216	uint lsdmr_common;
	217
	218	puts(" SDRAM: ");
	219
	220	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
	221
	222	/*
	223	* Setup SDRAM Base and Option Registers
	224	*/
	225	lbc->or2 = CFG_OR2_PRELIM;
	226	asm("msync");
	227
	228	lbc->br2 = CFG_BR2_PRELIM;
	229	asm("msync");
	230
	231	lbc->lbcr = CFG_LBC_LBCR;
	232	asm("msync");
	233
	234
	235	lbc->lsrt = CFG_LBC_LSRT;
	236	lbc->mrtpr = CFG_LBC_MRTPR;
	237	asm("msync");
	238
	239	/*
	240	* MPC8568 uses "new" 15-16 style addressing.
	241	*/
	242	lsdmr_common = CFG_LBC_LSDMR_COMMON;
	243	lsdmr_common \|= CFG_LBC_LSDMR_BSMA1516;
244
245	/*
246	* Issue PRECHARGE ALL command.
247	*/
248	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_PCHALL;
249	asm("sync;msync");
250	*sdram_addr = 0xff;
251	ppcDcbf((unsigned long) sdram_addr);
252	udelay(100);
253
254	/*
255	* Issue 8 AUTO REFRESH commands.
256	*/
257	for (idx = 0; idx < 8; idx++) {
258	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_ARFRSH;
259	asm("sync;msync");
260	*sdram_addr = 0xff;
261	ppcDcbf((unsigned long) sdram_addr);
262	udelay(100);
263	}
264
265	/*
266	* Issue 8 MODE-set command.
267	*/
268	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_MRW;
269	asm("sync;msync");
270	*sdram_addr = 0xff;
271	ppcDcbf((unsigned long) sdram_addr);
272	udelay(100);
273
274	/*
275	* Issue NORMAL OP command.
276	*/
277	lbc->lsdmr = lsdmr_common \| CFG_LBC_LSDMR_OP_NORMAL;
278	asm("sync;msync");
279	*sdram_addr = 0xff;
280	ppcDcbf((unsigned long) sdram_addr);
281	udelay(200); /* Overkill. Must wait > 200 bus cycles */
282
283	#endif /* enable SDRAM init */
284	}
285
286	#if defined(CFG_DRAM_TEST)
287	int
288	testdram(void)
289	{
290	uint pstart = (uint ) CFG_MEMTEST_START;
291	uint pend = (uint ) CFG_MEMTEST_END;
292	uint *p;
293
294	printf("Testing DRAM from 0x%08x to 0x%08x\n",
295	CFG_MEMTEST_START,
296	CFG_MEMTEST_END);
297
298	printf("DRAM test phase 1:\n");
299	for (p = pstart; p < pend; p++)
300	*p = 0xaaaaaaaa;
301
302	for (p = pstart; p < pend; p++) {
303	if (*p != 0xaaaaaaaa) {
304	printf ("DRAM test fails at: %08x\n", (uint) p);
305	return 1;
306	}
307	}
308
309	printf("DRAM test phase 2:\n");
310	for (p = pstart; p < pend; p++)
311	*p = 0x55555555;
312
313	for (p = pstart; p < pend; p++) {
314	if (*p != 0x55555555) {
315	printf ("DRAM test fails at: %08x\n", (uint) p);
316	return 1;
317	}
318	}
319
320	printf("DRAM test passed.\n");
321	return 0;
322	}
323	#endif
324
325	#if defined(CONFIG_PCI)
326	#ifndef CONFIG_PCI_PNP
327	static struct pci_config_table pci_mpc8568mds_config_table[] = {
328	{
329	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
330	pci_cfgfunc_config_device,
331	{PCI_ENET0_IOADDR,
332	PCI_ENET0_MEMADDR,
333	PCI_COMMON_MEMORY \| PCI_COMMAND_MASTER}
334	},
335	{}
336	};
337	#endif
338
339	static struct pci_controller hose[] = {
c59e4091	340	{
67431059	341	#ifndef CONFIG_PCI_PNP
c59e4091	342	config_table: pci_mpc8568mds_config_table,
67431059	343	#endif
c59e4091	344	}
67431059 AF	345	};
	346
	347	#endif /* CONFIG_PCI */
	348
c59e4091 HW	349	/*
	350	* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
	351	*/
	352	void
	353	pib_init(void)
	354	{
	355	u8 val8, orig_i2c_bus;
	356	/*
	357	* Assign PIB PMC2/3 to PCI bus
	358	*/
	359
	360	/switch temporarily to I2C bus #2 /
	361	orig_i2c_bus = i2c_get_bus_num();
	362	i2c_set_bus_num(1);
	363
	364	val8 = 0x00;
	365	i2c_write(0x23, 0x6, 1, &val8, 1);
	366	i2c_write(0x23, 0x7, 1, &val8, 1);
	367	val8 = 0xff;
	368	i2c_write(0x23, 0x2, 1, &val8, 1);
	369	i2c_write(0x23, 0x3, 1, &val8, 1);
	370
	371	val8 = 0x00;
	372	i2c_write(0x26, 0x6, 1, &val8, 1);
	373	val8 = 0x34;
	374	i2c_write(0x26, 0x7, 1, &val8, 1);
	375	val8 = 0xf9;
	376	i2c_write(0x26, 0x2, 1, &val8, 1);
	377	val8 = 0xff;
	378	i2c_write(0x26, 0x3, 1, &val8, 1);
	379
	380	val8 = 0x00;
	381	i2c_write(0x27, 0x6, 1, &val8, 1);
	382	i2c_write(0x27, 0x7, 1, &val8, 1);
	383	val8 = 0xff;
	384	i2c_write(0x27, 0x2, 1, &val8, 1);
	385	val8 = 0xef;
	386	i2c_write(0x27, 0x3, 1, &val8, 1);
	387
	388	asm("eieio");
	389	}
	390
67431059 AF	391	void
	392	pci_init_board(void)
	393	{
	394	#ifdef CONFIG_PCI
c59e4091	395	pib_init();
da9d4610	396	pci_mpc85xx_init(hose);
67431059 AF	397	#endif
67431059 AF	398	}