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affae2bf WD |
1 | /* |
2 | * (C) Copyright 2000, 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * Modified 4/5/2001 | |
26 | * Wait for completion of each sector erase command issued | |
27 | * 4/5/2001 | |
28 | * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com | |
29 | */ | |
30 | ||
31 | /* | |
32 | * Modified 3/7/2001 | |
33149b88 | 33 | * - adapted for pip405, Denis Peter, MPL AG Switzerland |
affae2bf WD |
34 | * TODO: |
35 | * clean-up | |
36 | */ | |
37 | ||
38 | #include <common.h> | |
39 | #include <ppc4xx.h> | |
40 | #include <asm/processor.h> | |
affae2bf | 41 | #include "common_util.h" |
7205e407 WD |
42 | #if defined(CONFIG_MIP405) |
43 | #include "../mip405/mip405.h" | |
44 | #endif | |
45 | #if defined(CONFIG_PIP405) | |
46 | #include "../pip405/pip405.h" | |
47 | #endif | |
48 | #include <405gp_pci.h> | |
affae2bf WD |
49 | |
50 | flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
51 | /*----------------------------------------------------------------------- | |
52 | * Functions | |
53 | */ | |
54 | static ulong flash_get_size (vu_long *addr, flash_info_t *info); | |
55 | static int write_word (flash_info_t *info, ulong dest, ulong data); | |
affae2bf WD |
56 | |
57 | void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt); | |
58 | ||
59 | ||
affae2bf WD |
60 | #ifdef CONFIG_PIP405 |
61 | #define ADDR0 0x5555 | |
62 | #define ADDR1 0x2aaa | |
63 | #define FLASH_WORD_SIZE unsigned short | |
64 | #endif | |
65 | ||
66 | #ifdef CONFIG_MIP405 | |
67 | #define ADDR0 0x5555 | |
68 | #define ADDR1 0x2aaa | |
69 | #define FLASH_WORD_SIZE unsigned short | |
70 | #endif | |
71 | ||
72 | #define FALSE 0 | |
73 | #define TRUE 1 | |
74 | ||
75 | /*----------------------------------------------------------------------- | |
7205e407 WD |
76 | * Some CS switching routines: |
77 | * | |
78 | * On PIP/MIP405 we have 3 (4) possible boot mode | |
79 | * | |
80 | * - Boot from Flash (Flash CS = CS0, MPS CS = CS1) | |
81 | * - Boot from MPS (Flash CS = CS1, MPS CS = CS0) | |
82 | * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1) | |
83 | * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0) | |
84 | * The flash init is the first board specific routine which is called | |
85 | * after code relocation (running from SDRAM) | |
86 | * The first thing we do is to map the Flash CS to the Flash area and | |
87 | * the MPS CS to the MPS area. Since the flash size is unknown at this | |
88 | * point, we use the max flash size and the lowest flash address as base. | |
89 | * | |
90 | * After flash detection we adjust the size of the CS area accordingly. | |
91 | * The board_init_r will fill in wrong values in the board init structure, | |
92 | * but this will be fixed in the misc_init_r routine: | |
93 | * bd->bi_flashstart=0-flash_info[0].size | |
94 | * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN | |
95 | * bd->bi_flashoffset=0 | |
96 | * | |
affae2bf | 97 | */ |
7205e407 WD |
98 | int get_boot_mode(void) |
99 | { | |
100 | unsigned long pbcr; | |
101 | int res = 0; | |
102 | pbcr = mfdcr (strap); | |
103 | if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) | |
104 | /* boot via MPS or MPS mapping */ | |
105 | res = BOOT_MPS; | |
106 | if(pbcr & PSR_ROM_LOC) | |
107 | /* boot via PCI.. */ | |
108 | res |= BOOT_PCI; | |
109 | return res; | |
110 | } | |
111 | ||
112 | /* Map the flash high (in boot area) | |
113 | This code can only be executed from SDRAM (after relocation). | |
114 | */ | |
115 | void setup_cs_reloc(void) | |
116 | { | |
117 | int mode; | |
118 | /* Since we are relocated, we can set-up the CS finaly | |
119 | * but first of all, switch off PCI mapping (in case it was a PCI boot) */ | |
120 | out32r(PMM0MA,0L); | |
121 | icache_enable (); /* we are relocated */ | |
122 | /* get boot mode */ | |
123 | mode=get_boot_mode(); | |
124 | /* we map the flash high in every case */ | |
125 | /* first findout on which cs the flash is */ | |
126 | if(mode & BOOT_MPS) { | |
127 | /* map flash high on CS1 and MPS on CS0 */ | |
128 | mtdcr (ebccfga, pb0ap); | |
129 | mtdcr (ebccfgd, MPS_AP); | |
130 | mtdcr (ebccfga, pb0cr); | |
131 | mtdcr (ebccfgd, MPS_CR); | |
132 | /* we use the default values (max values) for the flash | |
133 | * because its real size is not yet known */ | |
134 | mtdcr (ebccfga, pb1ap); | |
135 | mtdcr (ebccfgd, FLASH_AP); | |
136 | mtdcr (ebccfga, pb1cr); | |
137 | mtdcr (ebccfgd, FLASH_CR_B); | |
138 | } | |
139 | else { | |
140 | /* map flash high on CS0 and MPS on CS1 */ | |
141 | mtdcr (ebccfga, pb1ap); | |
142 | mtdcr (ebccfgd, MPS_AP); | |
143 | mtdcr (ebccfga, pb1cr); | |
144 | mtdcr (ebccfgd, MPS_CR); | |
145 | /* we use the default values (max values) for the flash | |
146 | * because its real size is not yet known */ | |
147 | mtdcr (ebccfga, pb0ap); | |
148 | mtdcr (ebccfgd, FLASH_AP); | |
149 | mtdcr (ebccfga, pb0cr); | |
150 | mtdcr (ebccfgd, FLASH_CR_B); | |
151 | } | |
152 | } | |
153 | ||
affae2bf WD |
154 | |
155 | ||
156 | unsigned long flash_init (void) | |
157 | { | |
4a551709 | 158 | unsigned long size_b0, size_b1,flashcr, size_reg; |
7205e407 WD |
159 | int mode, i; |
160 | extern char version_string; | |
161 | char *p=&version_string; | |
affae2bf | 162 | |
33149b88 WD |
163 | /* Since we are relocated, we can set-up the CS finally */ |
164 | setup_cs_reloc(); | |
165 | /* get and display boot mode */ | |
7205e407 WD |
166 | mode=get_boot_mode(); |
167 | if(mode & BOOT_PCI) | |
168 | printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ? | |
33149b88 | 169 | "MPS" : "Flash"); |
affae2bf | 170 | else |
7205e407 | 171 | printf("(%s Boot) ",(mode & BOOT_MPS) ? |
33149b88 | 172 | "MPS" : "Flash"); |
affae2bf WD |
173 | /* Init: no FLASHes known */ |
174 | for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { | |
175 | flash_info[i].flash_id = FLASH_UNKNOWN; | |
176 | } | |
177 | ||
178 | /* Static FLASH Bank configuration here - FIXME XXX */ | |
179 | ||
7205e407 | 180 | size_b0 = flash_get_size((vu_long *)CFG_MONITOR_BASE, &flash_info[0]); |
affae2bf WD |
181 | |
182 | if (flash_info[0].flash_id == FLASH_UNKNOWN) { | |
183 | printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", | |
184 | size_b0, size_b0<<20); | |
185 | } | |
33149b88 WD |
186 | /* protect the bootloader */ |
187 | /* Monitor protection ON by default */ | |
affae2bf | 188 | #if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
33149b88 WD |
189 | flash_protect(FLAG_PROTECT_SET, |
190 | CFG_MONITOR_BASE, | |
3b57fe0a | 191 | CFG_MONITOR_BASE+monitor_flash_len-1, |
33149b88 | 192 | &flash_info[0]); |
affae2bf | 193 | #endif |
27b207fd WD |
194 | /* protect reset vector */ |
195 | flash_info[0].protect[flash_info[0].sector_count-1] = 1; | |
33149b88 WD |
196 | size_b1 = 0 ; |
197 | flash_info[0].size = size_b0; | |
7205e407 | 198 | /* set up flash cs according to the size */ |
4a551709 WD |
199 | size_reg=(flash_info[0].size >>20); |
200 | switch (size_reg) { | |
201 | case 0: | |
202 | case 1: i=0; break; /* <= 1MB */ | |
203 | case 2: i=1; break; /* = 2MB */ | |
204 | case 4: i=2; break; /* = 4MB */ | |
205 | case 8: i=3; break; /* = 8MB */ | |
206 | case 16: i=4; break; /* = 16MB */ | |
207 | case 32: i=5; break; /* = 32MB */ | |
208 | case 64: i=6; break; /* = 64MB */ | |
209 | case 128: i=7; break; /*= 128MB */ | |
210 | default: | |
211 | printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg); | |
212 | while(1); | |
213 | } | |
7205e407 WD |
214 | if(mode & BOOT_MPS) { |
215 | /* flash is on CS1 */ | |
216 | mtdcr(ebccfga, pb1cr); | |
217 | flashcr = mfdcr (ebccfgd); | |
218 | /* we map the flash high in every case */ | |
219 | flashcr&=0x0001FFFF; /* mask out address bits */ | |
220 | flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ | |
4a551709 | 221 | flashcr|= (i << 17); /* size addr */ |
7205e407 WD |
222 | mtdcr(ebccfga, pb1cr); |
223 | mtdcr(ebccfgd, flashcr); | |
224 | } | |
225 | else { | |
226 | /* flash is on CS0 */ | |
227 | mtdcr(ebccfga, pb0cr); | |
228 | flashcr = mfdcr (ebccfgd); | |
229 | /* we map the flash high in every case */ | |
230 | flashcr&=0x0001FFFF; /* mask out address bits */ | |
231 | flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ | |
4a551709 | 232 | flashcr|= (i << 17); /* size addr */ |
7205e407 WD |
233 | mtdcr(ebccfga, pb0cr); |
234 | mtdcr(ebccfgd, flashcr); | |
235 | } | |
affae2bf | 236 | #if 0 |
7205e407 | 237 | /* enable this if you want to test if |
33149b88 WD |
238 | the relocation has be done ok. |
239 | This will disable both Chipselects */ | |
240 | mtdcr (ebccfga, pb0cr); | |
241 | mtdcr (ebccfgd, 0L); | |
242 | mtdcr (ebccfga, pb1cr); | |
243 | mtdcr (ebccfgd, 0L); | |
244 | printf("CS0 & CS1 switched off for test\n"); | |
245 | #endif | |
7205e407 WD |
246 | /* patch version_string */ |
247 | for(i=0;i<0x100;i++) { | |
248 | if(*p=='\n') { | |
249 | *p=0; | |
250 | break; | |
251 | } | |
252 | p++; | |
253 | } | |
33149b88 | 254 | return (size_b0); |
affae2bf WD |
255 | } |
256 | ||
33149b88 | 257 | |
affae2bf WD |
258 | /*----------------------------------------------------------------------- |
259 | */ | |
260 | void flash_print_info (flash_info_t *info) | |
261 | { | |
262 | int i; | |
33149b88 WD |
263 | int k; |
264 | int size; | |
265 | int erased; | |
266 | volatile unsigned long *flash; | |
affae2bf WD |
267 | |
268 | if (info->flash_id == FLASH_UNKNOWN) { | |
269 | printf ("missing or unknown FLASH type\n"); | |
270 | return; | |
271 | } | |
272 | ||
273 | switch (info->flash_id & FLASH_VENDMASK) { | |
274 | case FLASH_MAN_AMD: printf ("AMD "); break; | |
275 | case FLASH_MAN_FUJ: printf ("FUJITSU "); break; | |
276 | case FLASH_MAN_SST: printf ("SST "); break; | |
277 | case FLASH_MAN_INTEL: printf ("Intel "); break; | |
278 | default: printf ("Unknown Vendor "); break; | |
279 | } | |
280 | ||
281 | switch (info->flash_id & FLASH_TYPEMASK) { | |
282 | case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); | |
283 | break; | |
284 | case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); | |
285 | break; | |
286 | case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); | |
287 | break; | |
288 | case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); | |
289 | break; | |
290 | case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); | |
291 | break; | |
292 | case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); | |
293 | break; | |
294 | case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); | |
295 | break; | |
296 | case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); | |
297 | break; | |
298 | case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); | |
299 | break; | |
300 | case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); | |
301 | break; | |
302 | case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); | |
303 | break; | |
304 | case FLASH_INTEL320T: printf ("TE28F320C3 (32 Mbit, top sector size)\n"); | |
305 | break; | |
7205e407 WD |
306 | case FLASH_AM640U: printf ("AM29LV640U (64 Mbit, uniform sector size)\n"); |
307 | break; | |
affae2bf WD |
308 | default: printf ("Unknown Chip Type\n"); |
309 | break; | |
310 | } | |
311 | ||
312 | printf (" Size: %ld KB in %d Sectors\n", | |
313 | info->size >> 10, info->sector_count); | |
314 | ||
315 | printf (" Sector Start Addresses:"); | |
316 | for (i=0; i<info->sector_count; ++i) { | |
33149b88 WD |
317 | /* |
318 | * Check if whole sector is erased | |
319 | */ | |
affae2bf | 320 | if (i != (info->sector_count-1)) |
33149b88 | 321 | size = info->start[i+1] - info->start[i]; |
affae2bf | 322 | else |
33149b88 WD |
323 | size = info->start[0] + info->size - info->start[i]; |
324 | erased = 1; | |
325 | flash = (volatile unsigned long *)info->start[i]; | |
326 | size = size >> 2; /* divide by 4 for longword access */ | |
327 | for (k=0; k<size; k++) { | |
328 | if (*flash++ != 0xffffffff) { | |
329 | erased = 0; | |
affae2bf WD |
330 | break; |
331 | } | |
33149b88 | 332 | } |
affae2bf WD |
333 | if ((i % 5) == 0) |
334 | printf ("\n "); | |
affae2bf WD |
335 | printf (" %08lX%s%s", |
336 | info->start[i], | |
337 | erased ? " E" : " ", | |
33149b88 | 338 | info->protect[i] ? "RO " : " "); |
affae2bf WD |
339 | } |
340 | printf ("\n"); | |
affae2bf WD |
341 | } |
342 | ||
343 | /*----------------------------------------------------------------------- | |
344 | */ | |
345 | ||
346 | ||
347 | /*----------------------------------------------------------------------- | |
7205e407 WD |
348 | |
349 | */ | |
affae2bf WD |
350 | |
351 | /* | |
352 | * The following code cannot be run from FLASH! | |
353 | */ | |
354 | static ulong flash_get_size (vu_long *addr, flash_info_t *info) | |
355 | { | |
356 | short i; | |
357 | FLASH_WORD_SIZE value; | |
7205e407 | 358 | ulong base; |
affae2bf WD |
359 | volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; |
360 | ||
361 | /* Write auto select command: read Manufacturer ID */ | |
362 | addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; | |
363 | addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; | |
364 | addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; | |
365 | ||
366 | value = addr2[0]; | |
367 | /* printf("flash_get_size value: %x\n",value); */ | |
368 | switch (value) { | |
369 | case (FLASH_WORD_SIZE)AMD_MANUFACT: | |
370 | info->flash_id = FLASH_MAN_AMD; | |
371 | break; | |
372 | case (FLASH_WORD_SIZE)FUJ_MANUFACT: | |
373 | info->flash_id = FLASH_MAN_FUJ; | |
374 | break; | |
375 | case (FLASH_WORD_SIZE)INTEL_MANUFACT: | |
376 | info->flash_id = FLASH_MAN_INTEL; | |
377 | break; | |
378 | case (FLASH_WORD_SIZE)SST_MANUFACT: | |
379 | info->flash_id = FLASH_MAN_SST; | |
380 | break; | |
381 | default: | |
382 | info->flash_id = FLASH_UNKNOWN; | |
383 | info->sector_count = 0; | |
384 | info->size = 0; | |
385 | return (0); /* no or unknown flash */ | |
386 | } | |
387 | value = addr2[1]; /* device ID */ | |
7205e407 | 388 | /* printf("Device value %x\n",value); */ |
affae2bf WD |
389 | switch (value) { |
390 | case (FLASH_WORD_SIZE)AMD_ID_F040B: | |
8bde7f77 | 391 | info->flash_id += FLASH_AM040; |
affae2bf WD |
392 | info->sector_count = 8; |
393 | info->size = 0x0080000; /* => 512 ko */ | |
394 | break; | |
395 | case (FLASH_WORD_SIZE)AMD_ID_LV400T: | |
396 | info->flash_id += FLASH_AM400T; | |
397 | info->sector_count = 11; | |
398 | info->size = 0x00080000; | |
399 | break; /* => 0.5 MB */ | |
400 | ||
401 | case (FLASH_WORD_SIZE)AMD_ID_LV400B: | |
402 | info->flash_id += FLASH_AM400B; | |
403 | info->sector_count = 11; | |
404 | info->size = 0x00080000; | |
405 | break; /* => 0.5 MB */ | |
406 | ||
407 | case (FLASH_WORD_SIZE)AMD_ID_LV800T: | |
408 | info->flash_id += FLASH_AM800T; | |
409 | info->sector_count = 19; | |
410 | info->size = 0x00100000; | |
411 | break; /* => 1 MB */ | |
412 | ||
413 | case (FLASH_WORD_SIZE)AMD_ID_LV800B: | |
414 | info->flash_id += FLASH_AM800B; | |
415 | info->sector_count = 19; | |
416 | info->size = 0x00100000; | |
417 | break; /* => 1 MB */ | |
418 | ||
419 | case (FLASH_WORD_SIZE)AMD_ID_LV160T: | |
420 | info->flash_id += FLASH_AM160T; | |
421 | info->sector_count = 35; | |
422 | info->size = 0x00200000; | |
423 | break; /* => 2 MB */ | |
424 | ||
425 | case (FLASH_WORD_SIZE)AMD_ID_LV160B: | |
426 | info->flash_id += FLASH_AM160B; | |
427 | info->sector_count = 35; | |
428 | info->size = 0x00200000; | |
429 | break; /* => 2 MB */ | |
affae2bf WD |
430 | case (FLASH_WORD_SIZE)AMD_ID_LV320T: |
431 | info->flash_id += FLASH_AM320T; | |
432 | info->sector_count = 67; | |
433 | info->size = 0x00400000; | |
434 | break; /* => 4 MB */ | |
7205e407 WD |
435 | case (FLASH_WORD_SIZE)AMD_ID_LV640U: |
436 | info->flash_id += FLASH_AM640U; | |
437 | info->sector_count = 128; | |
438 | info->size = 0x00800000; | |
439 | break; /* => 8 MB */ | |
440 | #if 0 /* enable when device IDs are available */ | |
affae2bf WD |
441 | |
442 | case (FLASH_WORD_SIZE)AMD_ID_LV320B: | |
443 | info->flash_id += FLASH_AM320B; | |
444 | info->sector_count = 67; | |
445 | info->size = 0x00400000; | |
446 | break; /* => 4 MB */ | |
447 | #endif | |
448 | case (FLASH_WORD_SIZE)SST_ID_xF800A: | |
449 | info->flash_id += FLASH_SST800A; | |
450 | info->sector_count = 16; | |
451 | info->size = 0x00100000; | |
452 | break; /* => 1 MB */ | |
453 | case (FLASH_WORD_SIZE)INTEL_ID_28F320C3T: | |
454 | info->flash_id += FLASH_INTEL320T; | |
455 | info->sector_count = 71; | |
456 | info->size = 0x00400000; | |
457 | break; /* => 4 MB */ | |
458 | ||
459 | ||
460 | case (FLASH_WORD_SIZE)SST_ID_xF160A: | |
461 | info->flash_id += FLASH_SST160A; | |
462 | info->sector_count = 32; | |
463 | info->size = 0x00200000; | |
464 | break; /* => 2 MB */ | |
465 | ||
466 | default: | |
467 | info->flash_id = FLASH_UNKNOWN; | |
468 | return (0); /* => no or unknown flash */ | |
469 | ||
470 | } | |
7205e407 WD |
471 | /* base address calculation */ |
472 | base=0-info->size; | |
affae2bf | 473 | /* set up sector start address table */ |
33149b88 | 474 | if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || |
7205e407 WD |
475 | (info->flash_id == FLASH_AM040) || |
476 | (info->flash_id == FLASH_AM640U)){ | |
affae2bf WD |
477 | for (i = 0; i < info->sector_count; i++) |
478 | info->start[i] = base + (i * 0x00010000); | |
33149b88 WD |
479 | } |
480 | else { | |
affae2bf | 481 | if (info->flash_id & FLASH_BTYPE) { |
33149b88 WD |
482 | /* set sector offsets for bottom boot block type */ |
483 | info->start[0] = base + 0x00000000; | |
484 | info->start[1] = base + 0x00004000; | |
485 | info->start[2] = base + 0x00006000; | |
486 | info->start[3] = base + 0x00008000; | |
487 | for (i = 4; i < info->sector_count; i++) | |
488 | info->start[i] = base + (i * 0x00010000) - 0x00030000; | |
489 | } | |
490 | else { | |
affae2bf WD |
491 | /* set sector offsets for top boot block type */ |
492 | i = info->sector_count - 1; | |
493 | if(info->sector_count==71) { | |
494 | ||
495 | info->start[i--] = base + info->size - 0x00002000; | |
496 | info->start[i--] = base + info->size - 0x00004000; | |
497 | info->start[i--] = base + info->size - 0x00006000; | |
498 | info->start[i--] = base + info->size - 0x00008000; | |
499 | info->start[i--] = base + info->size - 0x0000A000; | |
500 | info->start[i--] = base + info->size - 0x0000C000; | |
501 | info->start[i--] = base + info->size - 0x0000E000; | |
502 | for (; i >= 0; i--) | |
503 | info->start[i] = base + i * 0x000010000; | |
504 | } | |
505 | else { | |
506 | info->start[i--] = base + info->size - 0x00004000; | |
507 | info->start[i--] = base + info->size - 0x00006000; | |
508 | info->start[i--] = base + info->size - 0x00008000; | |
509 | for (; i >= 0; i--) | |
510 | info->start[i] = base + i * 0x00010000; | |
511 | } | |
512 | } | |
513 | } | |
514 | ||
515 | /* check for protected sectors */ | |
516 | for (i = 0; i < info->sector_count; i++) { | |
517 | /* read sector protection at sector address, (A7 .. A0) = 0x02 */ | |
518 | /* D0 = 1 if protected */ | |
519 | addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); | |
33149b88 WD |
520 | if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) |
521 | info->protect[i] = 0; | |
522 | else | |
523 | info->protect[i] = addr2[2] & 1; | |
affae2bf WD |
524 | } |
525 | ||
526 | /* | |
527 | * Prevent writes to uninitialized FLASH. | |
528 | */ | |
529 | if (info->flash_id != FLASH_UNKNOWN) { | |
affae2bf WD |
530 | addr2 = (FLASH_WORD_SIZE *)info->start[0]; |
531 | *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ | |
affae2bf WD |
532 | } |
533 | return (info->size); | |
534 | } | |
535 | ||
33149b88 | 536 | |
affae2bf WD |
537 | int wait_for_DQ7(flash_info_t *info, int sect) |
538 | { | |
539 | ulong start, now, last; | |
540 | volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); | |
541 | ||
542 | start = get_timer (0); | |
33149b88 WD |
543 | last = start; |
544 | while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { | |
545 | if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { | |
546 | printf ("Timeout\n"); | |
547 | return -1; | |
548 | } | |
549 | /* show that we're waiting */ | |
550 | if ((now - last) > 1000) { /* every second */ | |
551 | putc ('.'); | |
552 | last = now; | |
553 | } | |
554 | } | |
affae2bf WD |
555 | return 0; |
556 | } | |
557 | ||
558 | int intel_wait_for_DQ7(flash_info_t *info, int sect) | |
559 | { | |
560 | ulong start, now, last; | |
561 | volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); | |
562 | ||
33149b88 WD |
563 | start = get_timer (0); |
564 | last = start; | |
565 | while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { | |
566 | if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { | |
567 | printf ("Timeout\n"); | |
568 | return -1; | |
569 | } | |
570 | /* show that we're waiting */ | |
571 | if ((now - last) > 1000) { /* every second */ | |
572 | putc ('.'); | |
573 | last = now; | |
574 | } | |
575 | } | |
576 | addr[0]=(FLASH_WORD_SIZE)0x00500050; | |
affae2bf WD |
577 | return 0; |
578 | } | |
579 | ||
580 | /*----------------------------------------------------------------------- | |
581 | */ | |
582 | ||
583 | int flash_erase (flash_info_t *info, int s_first, int s_last) | |
584 | { | |
585 | volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); | |
586 | volatile FLASH_WORD_SIZE *addr2; | |
587 | int flag, prot, sect, l_sect; | |
588 | int i; | |
589 | ||
590 | ||
591 | if ((s_first < 0) || (s_first > s_last)) { | |
592 | if (info->flash_id == FLASH_UNKNOWN) { | |
593 | printf ("- missing\n"); | |
594 | } else { | |
595 | printf ("- no sectors to erase\n"); | |
596 | } | |
597 | return 1; | |
598 | } | |
599 | ||
600 | if (info->flash_id == FLASH_UNKNOWN) { | |
601 | printf ("Can't erase unknown flash type - aborted\n"); | |
602 | return 1; | |
603 | } | |
604 | ||
605 | prot = 0; | |
606 | for (sect=s_first; sect<=s_last; ++sect) { | |
607 | if (info->protect[sect]) { | |
608 | prot++; | |
609 | } | |
610 | } | |
611 | ||
612 | if (prot) { | |
613 | printf ("- Warning: %d protected sectors will not be erased!\n", | |
614 | prot); | |
615 | } else { | |
616 | printf ("\n"); | |
617 | } | |
618 | ||
619 | l_sect = -1; | |
620 | ||
621 | /* Disable interrupts which might cause a timeout here */ | |
622 | flag = disable_interrupts(); | |
623 | ||
624 | /* Start erase on unprotected sectors */ | |
625 | for (sect = s_first; sect<=s_last; sect++) { | |
626 | if (info->protect[sect] == 0) { /* not protected */ | |
627 | addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); | |
628 | /* printf("Erasing sector %p\n", addr2); */ /* CLH */ | |
33149b88 | 629 | if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { |
affae2bf WD |
630 | addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
631 | addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; | |
632 | addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; | |
633 | addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; | |
634 | addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; | |
635 | addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ | |
636 | for (i=0; i<50; i++) | |
637 | udelay(1000); /* wait 1 ms */ | |
33149b88 WD |
638 | wait_for_DQ7(info, sect); |
639 | } | |
640 | else { | |
8bde7f77 | 641 | if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ |
affae2bf WD |
642 | addr2[0] = (FLASH_WORD_SIZE)0x00600060; /* unlock sector */ |
643 | addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */ | |
33149b88 | 644 | intel_wait_for_DQ7(info, sect); |
affae2bf WD |
645 | addr2[0] = (FLASH_WORD_SIZE)0x00200020; /* sector erase */ |
646 | addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */ | |
33149b88 | 647 | intel_wait_for_DQ7(info, sect); |
affae2bf WD |
648 | } |
649 | else { | |
650 | addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; | |
651 | addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; | |
652 | addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; | |
653 | addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; | |
654 | addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; | |
655 | addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ | |
33149b88 WD |
656 | wait_for_DQ7(info, sect); |
657 | } | |
658 | } | |
659 | l_sect = sect; | |
660 | /* | |
661 | * Wait for each sector to complete, it's more | |
662 | * reliable. According to AMD Spec, you must | |
663 | * issue all erase commands within a specified | |
664 | * timeout. This has been seen to fail, especially | |
665 | * if printf()s are included (for debug)!! | |
666 | */ | |
667 | /* wait_for_DQ7(info, sect); */ | |
affae2bf WD |
668 | } |
669 | } | |
670 | ||
671 | /* re-enable interrupts if necessary */ | |
672 | if (flag) | |
673 | enable_interrupts(); | |
674 | ||
675 | /* wait at least 80us - let's wait 1 ms */ | |
676 | udelay (1000); | |
677 | ||
678 | #if 0 | |
679 | /* | |
680 | * We wait for the last triggered sector | |
681 | */ | |
682 | if (l_sect < 0) | |
683 | goto DONE; | |
684 | wait_for_DQ7(info, l_sect); | |
685 | ||
686 | DONE: | |
687 | #endif | |
688 | /* reset to read mode */ | |
689 | addr = (FLASH_WORD_SIZE *)info->start[0]; | |
690 | addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ | |
691 | ||
692 | printf (" done\n"); | |
693 | return 0; | |
694 | } | |
695 | ||
33149b88 | 696 | |
affae2bf WD |
697 | void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt) |
698 | { | |
699 | int i; | |
700 | volatile FLASH_WORD_SIZE *addr2; | |
701 | long c; | |
702 | c= (long)cnt; | |
703 | for(i=info->sector_count-1;i>0;i--) | |
704 | { | |
705 | if(addr>=info->start[i]) | |
706 | break; | |
707 | } | |
708 | do { | |
709 | addr2 = (FLASH_WORD_SIZE *)(info->start[i]); | |
710 | addr2[0] = (FLASH_WORD_SIZE)0x00600060; /* unlock sector setup */ | |
711 | addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* unlock sector */ | |
712 | intel_wait_for_DQ7(info, i); | |
713 | i++; | |
714 | c-=(info->start[i]-info->start[i-1]); | |
715 | }while(c>0); | |
affae2bf WD |
716 | } |
717 | ||
718 | ||
719 | /*----------------------------------------------------------------------- | |
720 | * Copy memory to flash, returns: | |
721 | * 0 - OK | |
722 | * 1 - write timeout | |
723 | * 2 - Flash not erased | |
724 | */ | |
725 | ||
726 | int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) | |
727 | { | |
728 | ulong cp, wp, data; | |
729 | int i, l, rc; | |
730 | ||
731 | if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ | |
732 | unlock_intel_sectors(info,addr,cnt); | |
733 | } | |
734 | wp = (addr & ~3); /* get lower word aligned address */ | |
735 | /* | |
736 | * handle unaligned start bytes | |
737 | */ | |
738 | if ((l = addr - wp) != 0) { | |
739 | data = 0; | |
740 | for (i=0, cp=wp; i<l; ++i, ++cp) { | |
741 | data = (data << 8) | (*(uchar *)cp); | |
742 | } | |
743 | for (; i<4 && cnt>0; ++i) { | |
744 | data = (data << 8) | *src++; | |
745 | --cnt; | |
746 | ++cp; | |
747 | } | |
748 | for (; cnt==0 && i<4; ++i, ++cp) { | |
749 | data = (data << 8) | (*(uchar *)cp); | |
750 | } | |
751 | ||
752 | if ((rc = write_word(info, wp, data)) != 0) { | |
753 | return (rc); | |
754 | } | |
755 | wp += 4; | |
756 | } | |
757 | ||
758 | /* | |
759 | * handle word aligned part | |
760 | */ | |
761 | while (cnt >= 4) { | |
762 | data = 0; | |
763 | for (i=0; i<4; ++i) { | |
764 | data = (data << 8) | *src++; | |
765 | } | |
766 | if ((rc = write_word(info, wp, data)) != 0) { | |
767 | return (rc); | |
768 | } | |
769 | wp += 4; | |
770 | if((wp % 0x10000)==0) | |
771 | printf("."); /* show Progress */ | |
772 | cnt -= 4; | |
773 | } | |
774 | ||
775 | if (cnt == 0) { | |
776 | return (0); | |
777 | } | |
778 | ||
779 | /* | |
780 | * handle unaligned tail bytes | |
781 | */ | |
782 | data = 0; | |
783 | for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { | |
784 | data = (data << 8) | *src++; | |
785 | --cnt; | |
786 | } | |
787 | for (; i<4; ++i, ++cp) { | |
788 | data = (data << 8) | (*(uchar *)cp); | |
789 | } | |
790 | rc=write_word(info, wp, data); | |
791 | return rc; | |
792 | } | |
793 | ||
794 | /*----------------------------------------------------------------------- | |
795 | * Write a word to Flash, returns: | |
796 | * 0 - OK | |
797 | * 1 - write timeout | |
798 | * 2 - Flash not erased | |
799 | */ | |
800 | static FLASH_WORD_SIZE *read_val = (FLASH_WORD_SIZE *)0x200000; | |
801 | ||
802 | static int write_word (flash_info_t *info, ulong dest, ulong data) | |
803 | { | |
804 | volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); | |
805 | volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; | |
8bde7f77 | 806 | volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; |
affae2bf WD |
807 | ulong start; |
808 | int flag; | |
809 | int i; | |
810 | ||
811 | /* Check if Flash is (sufficiently) erased */ | |
812 | if ((*((volatile FLASH_WORD_SIZE *)dest) & | |
813 | (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { | |
814 | return (2); | |
815 | } | |
816 | /* Disable interrupts which might cause a timeout here */ | |
817 | flag = disable_interrupts(); | |
818 | for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) | |
819 | { | |
820 | if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ | |
821 | /* intel style writting */ | |
822 | dest2[i] = (FLASH_WORD_SIZE)0x00500050; | |
823 | dest2[i] = (FLASH_WORD_SIZE)0x00400040; | |
824 | *read_val++ = data2[i]; | |
825 | dest2[i] = data2[i]; | |
826 | if (flag) | |
827 | enable_interrupts(); | |
828 | /* data polling for D7 */ | |
829 | start = get_timer (0); | |
830 | udelay(10); | |
831 | while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) | |
832 | { | |
833 | if (get_timer(start) > CFG_FLASH_WRITE_TOUT) | |
834 | return (1); | |
835 | } | |
836 | dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */ | |
837 | udelay(10); | |
838 | dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */ | |
839 | if(dest2[i]!=data2[i]) | |
840 | printf("Error at %p 0x%04X != 0x%04X\n",&dest2[i],dest2[i],data2[i]); | |
841 | } | |
842 | else { | |
843 | addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; | |
844 | addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; | |
845 | addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; | |
846 | dest2[i] = data2[i]; | |
847 | /* re-enable interrupts if necessary */ | |
848 | if (flag) | |
849 | enable_interrupts(); | |
850 | /* data polling for D7 */ | |
851 | start = get_timer (0); | |
852 | while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != | |
853 | (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { | |
854 | if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { | |
8bde7f77 | 855 | return (1); |
affae2bf WD |
856 | } |
857 | } | |
858 | } | |
859 | } | |
860 | return (0); | |
861 | } | |
862 | ||
863 | /*----------------------------------------------------------------------- | |
864 | */ |