projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 46263f2d WD |
1 | /* |
| 2 | * SPDX-License-Identifier: GPL-2.0 ibm-pibs | |
| 3 | */ | |
| c609719b WD |
4 | /* |
| 5 | * Adapted for PIP405 03.07.01 | |
| 6 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch | |
| 7 | * | |
| 8 | * TODO: Clean-up | |
| 9 | */ | |
| 10 | ||
| 11 | #include <common.h> | |
| 12 | #include <pci.h> | |
| 13 | #include "isa.h" | |
| 14 | ||
| 15 | #ifdef CONFIG_405GP | |
| 16 | #ifdef CONFIG_PCI | |
| 17 | ||
| d87080b7 | 18 | DECLARE_GLOBAL_DATA_PTR; |
| c609719b WD |
19 | |
| 20 | #include "piix4_pci.h" | |
| 21 | #include "pci_parts.h" | |
| 22 | ||
| 23 | void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, | |
| 24 | struct pci_config_table *entry) | |
| 25 | { | |
| 26 | struct pci_pip405_config_entry *table; | |
| 27 | int i; | |
| 28 | ||
| 29 | table = (struct pci_pip405_config_entry*) entry->priv[0]; | |
| 30 | ||
| 31 | for (i=0; table[i].width; i++) | |
| 32 | { | |
| 33 | #ifdef DEBUG | |
| 34 | printf("Reg 0x%02X Value 0x%08lX Width %02d written\n", | |
| 35 | table[i].index, table[i].val, table[i].width); | |
| 36 | #endif | |
| 37 | ||
| 38 | switch(table[i].width) | |
| 39 | { | |
| 40 | case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break; | |
| 41 | case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break; | |
| 42 | case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break; | |
| 43 | } | |
| 44 | } | |
| 45 | } | |
| 46 | ||
| 47 | ||
| 48 | static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) | |
| 49 | { | |
| 50 | unsigned char int_line = 0xff; | |
| 3e38691e | 51 | unsigned char pin; |
| c609719b WD |
52 | /* |
| 53 | * Write pci interrupt line register | |
| 54 | */ | |
| 55 | if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */ | |
| 56 | return; | |
| 3e38691e WD |
57 | pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); |
| 58 | if ((pin == 0) || (pin > 4)) | |
| 59 | return; | |
| 60 | ||
| 61 | int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; | |
| 62 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); | |
| c609719b | 63 | #ifdef DEBUG |
| 3e38691e WD |
64 | printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", |
| 65 | PCI_DEV(dev),dev,int_line,int_line); | |
| c609719b | 66 | #endif |
| c609719b WD |
67 | } |
| 68 | ||
| 69 | extern void pci_405gp_init(struct pci_controller *hose); | |
| 70 | ||
| 71 | ||
| 72 | static struct pci_controller hose = { | |
| 73 | config_table: pci_pip405_config_table, | |
| 74 | fixup_irq: pci_pip405_fixup_irq, | |
| 75 | }; | |
| 76 | ||
| 3e38691e | 77 | |
| ad10dd9a | 78 | void pci_init_board(void) |
| c609719b WD |
79 | { |
| 80 | /*we want the ptrs to RAM not flash (ie don't use init list)*/ | |
| 81 | hose.fixup_irq = pci_pip405_fixup_irq; | |
| 82 | hose.config_table = pci_pip405_config_table; | |
| 3e38691e WD |
83 | #ifdef DEBUG |
| 84 | printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); | |
| 85 | #endif | |
| c609719b WD |
86 | pci_405gp_init(&hose); |
| 87 | } | |
| 88 | ||
| 89 | #endif /* CONFIG_PCI */ | |
| 90 | #endif /* CONFIG_405GP */ |