[people/ms/u-boot.git] / board / mpl / common / pci.c

/*
 * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
 */
/*
 * Adapted for PIP405 03.07.01
 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
 *
 * TODO: Clean-up
 */

#include <common.h>
#include <pci.h>
#include "isa.h"

#ifdef CONFIG_405GP
#ifdef CONFIG_PCI

DECLARE_GLOBAL_DATA_PTR;

#include "piix4_pci.h"
#include "pci_parts.h"

void pci_405gp_init(struct pci_controller *hose);

void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
		struct pci_config_table *entry)
{
	struct pci_pip405_config_entry *table;
	int i;

	table = (struct pci_pip405_config_entry *)entry->priv[0];

	for (i = 0; table[i].width; i++) {
#ifdef DEBUG
		printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
		       table[i].index, table[i].val, table[i].width);
#endif

		switch (table[i].width) {
		case 1:
		    pci_hose_write_config_byte(hose, dev,
					       table[i].index, table[i].val);
		    break;
		case 2:
		    pci_hose_write_config_word(hose, dev,
					       table[i].index, table[i].val);
		    break;
		case 4:
		    pci_hose_write_config_dword(hose, dev,
						table[i].index, table[i].val);
		    break;
		}
	}
}


static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
	unsigned char int_line = 0xff;
	unsigned char pin;
	/*
	 * Write pci interrupt line register
	 */
	if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */
		return;
	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
	if ((pin == 0) || (pin > 4))
		return;

	int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
#ifdef DEBUG
	printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
	       PCI_DEV(dev), dev, int_line, int_line);
#endif
}


static struct pci_controller hose = {
config_table: pci_pip405_config_table,
fixup_irq : pci_pip405_fixup_irq,
};


void pci_init_board(void)
{
	/*we want the ptrs to RAM not flash (ie don't use init list)*/
	hose.fixup_irq    = pci_pip405_fixup_irq;
	hose.config_table = pci_pip405_config_table;
#ifdef DEBUG
	printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",
	       pci_pip405_fixup_irq, pci_pip405_config_table, hose);
#endif
	pci_405gp_init(&hose);
}

#endif /* CONFIG_PCI */
#endif /* CONFIG_405GP */
Commit	Line	Data
46263f2d	1	/*
1b387ef5	2	* SPDX-License-Identifier: GPL-2.0 IBM-pibs
46263f2d	3	*/
c609719b WD	4	/*
	5	* Adapted for PIP405 03.07.01
	6	* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
	7	*
	8	* TODO: Clean-up
	9	*/
	10
	11	#include <common.h>
	12	#include <pci.h>
	13	#include "isa.h"
	14
	15	#ifdef CONFIG_405GP
	16	#ifdef CONFIG_PCI
	17
d87080b7	18	DECLARE_GLOBAL_DATA_PTR;
c609719b WD	19
	20	#include "piix4_pci.h"
	21	#include "pci_parts.h"
	22
57da153e CD	23	void pci_405gp_init(struct pci_controller *hose);
57da153e CD	24
c609719b	25	void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
57da153e	26	struct pci_config_table *entry)
c609719b WD	27	{
	28	struct pci_pip405_config_entry *table;
	29	int i;
	30
57da153e	31	table = (struct pci_pip405_config_entry *)entry->priv[0];
c609719b	32
57da153e	33	for (i = 0; table[i].width; i++) {
c609719b WD	34	#ifdef DEBUG
	35	printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
	36	table[i].index, table[i].val, table[i].width);
	37	#endif
	38
57da153e CD	39	switch (table[i].width) {
	40	case 1:
	41	pci_hose_write_config_byte(hose, dev,
	42	table[i].index, table[i].val);
	43	break;
	44	case 2:
	45	pci_hose_write_config_word(hose, dev,
	46	table[i].index, table[i].val);
	47	break;
	48	case 4:
	49	pci_hose_write_config_dword(hose, dev,
	50	table[i].index, table[i].val);
	51	break;
c609719b WD	52	}
	53	}
	54	}
	55
	56
	57	static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
	58	{
	59	unsigned char int_line = 0xff;
3e38691e	60	unsigned char pin;
c609719b WD	61	/*
	62	* Write pci interrupt line register
	63	*/
57da153e	64	if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */
c609719b	65	return;
3e38691e WD	66	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
3e38691e WD	67	if ((pin == 0) \|\| (pin > 4))
57da153e	68	return;
3e38691e WD	69
	70	int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
	71	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
c609719b	72	#ifdef DEBUG
3e38691e	73	printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
57da153e	74	PCI_DEV(dev), dev, int_line, int_line);
c609719b	75	#endif
c609719b WD	76	}
c609719b WD	77
c609719b WD	78
c609719b WD	79	static struct pci_controller hose = {
57da153e CD	80	config_table: pci_pip405_config_table,
57da153e CD	81	fixup_irq : pci_pip405_fixup_irq,
c609719b WD	82	};
c609719b WD	83
3e38691e	84
ad10dd9a	85	void pci_init_board(void)
c609719b WD	86	{
	87	/we want the ptrs to RAM not flash (ie don't use init list)/
	88	hose.fixup_irq = pci_pip405_fixup_irq;
	89	hose.config_table = pci_pip405_config_table;
3e38691e	90	#ifdef DEBUG
57da153e CD	91	printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",
57da153e CD	92	pci_pip405_fixup_irq, pci_pip405_config_table, hose);
3e38691e	93	#endif
c609719b WD	94	pci_405gp_init(&hose);
	95	}
	96
	97	#endif /* CONFIG_PCI */
	98	#endif /* CONFIG_405GP */