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858b1a64 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * | |
24 | * TODO: clean-up | |
25 | */ | |
26 | ||
27 | /* | |
28 | * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM? | |
29 | * | |
30 | * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being | |
31 | * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum | |
32 | * parameters from the datasheet are: | |
33 | * Tclk = 7.5ns (CL = 2) | |
34 | * Trp = 15ns | |
35 | * Trc = 60ns | |
36 | * Trcd = 15ns | |
37 | * Trfc = 66ns | |
38 | * | |
39 | * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock | |
40 | * period is 10ns and the parameters needed for the Timing Register are: | |
41 | * CASL = CL = 2 clock cycles | |
42 | * PTA = Trp = 15ns / 10ns = 2 clock cycles | |
43 | * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles | |
44 | * LDF = 2 clock cycles (but can be extended to meet board-level timing) | |
45 | * RFTA = Trfc = 66ns / 10ns= 7 clock cycles | |
46 | * RCD = Trcd = 15ns / 10ns= 2 clock cycles | |
47 | * | |
48 | * The actual bit settings in the register would be: | |
49 | * | |
50 | * CASL = 0b01 | |
51 | * PTA = 0b01 | |
52 | * CTP = 0b10 | |
53 | * LDF = 0b01 | |
54 | * RFTA = 0b011 | |
55 | * RCD = 0b01 | |
56 | * | |
57 | * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc | |
58 | * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay | |
59 | * defined as Trc rather than Trfc. | |
60 | * When using DIMM modules, most but not all of the required timing parameters can be read | |
61 | * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc | |
62 | * are not available from the EEPROM | |
63 | */ | |
64 | ||
65 | #include <common.h> | |
66 | #include "mip405.h" | |
67 | #include <asm/processor.h> | |
afabb498 | 68 | #include <asm/ppc4xx.h> |
b36df561 | 69 | #include <asm/ppc4xx-i2c.h> |
858b1a64 WD |
70 | #include <miiphy.h> |
71 | #include "../common/common_util.h" | |
28c34504 | 72 | #include <stdio_dev.h> |
858b1a64 | 73 | #include <i2c.h> |
27b207fd | 74 | #include <rtc.h> |
d87080b7 WD |
75 | |
76 | DECLARE_GLOBAL_DATA_PTR; | |
77 | ||
858b1a64 | 78 | #undef SDRAM_DEBUG |
f3e0de60 | 79 | #define ENABLE_ECC /* for ecc boards */ |
858b1a64 WD |
80 | |
81 | /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ | |
82 | #ifndef __ldiv_t_defined | |
83 | typedef struct { | |
84 | long int quot; /* Quotient */ | |
85 | long int rem; /* Remainder */ | |
86 | } ldiv_t; | |
87 | extern ldiv_t ldiv (long int __numer, long int __denom); | |
88 | # define __ldiv_t_defined 1 | |
89 | #endif | |
90 | ||
91 | ||
53677ef1 WD |
92 | #define PLD_PART_REG PER_PLD_ADDR + 0 |
93 | #define PLD_VERS_REG PER_PLD_ADDR + 1 | |
94 | #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 | |
95 | #define PLD_IRQ_REG PER_PLD_ADDR + 3 | |
96 | #define PLD_COM_MODE_REG PER_PLD_ADDR + 4 | |
97 | #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 | |
858b1a64 WD |
98 | |
99 | #define MEGA_BYTE (1024*1024) | |
100 | ||
101 | typedef struct { | |
102 | unsigned char boardtype; /* Board revision and Population Options */ | |
103 | unsigned char cal; /* cas Latency (will be programmend as cal-1) */ | |
104 | unsigned char trp; /* datain27 in clocks */ | |
105 | unsigned char trcd; /* datain29 in clocks */ | |
106 | unsigned char tras; /* datain30 in clocks */ | |
107 | unsigned char tctp; /* tras - trcd in clocks */ | |
108 | unsigned char am; /* Address Mod (will be programmed as am-1) */ | |
109 | unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */ | |
110 | unsigned char ecc; /* if true, ecc is enabled */ | |
111 | } sdram_t; | |
f3e0de60 WD |
112 | #if defined(CONFIG_MIP405T) |
113 | const sdram_t sdram_table[] = { | |
27b207fd | 114 | { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */ |
f3e0de60 WD |
115 | 3, /* Case Latenty = 3 */ |
116 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
117 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ | |
118 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
119 | 4, /* tcpt 44 - 20ns = 24ns */ | |
27b207fd WD |
120 | 2, /* Address Mode = 2 (12x9x4) */ |
121 | 3, /* size value (32MByte) */ | |
f3e0de60 WD |
122 | 0}, /* ECC disabled */ |
123 | { 0xff, /* terminator */ | |
124 | 0xff, | |
125 | 0xff, | |
126 | 0xff, | |
127 | 0xff, | |
128 | 0xff, | |
129 | 0xff, | |
130 | 0xff } | |
131 | }; | |
132 | #else | |
858b1a64 WD |
133 | const sdram_t sdram_table[] = { |
134 | { 0x0f, /* Rev A, 128MByte -1 Board */ | |
135 | 3, /* Case Latenty = 3 */ | |
136 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
33149b88 WD |
137 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
138 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
858b1a64 | 139 | 4, /* tcpt 44 - 20ns = 24ns */ |
33149b88 | 140 | 3, /* Address Mode = 3 */ |
858b1a64 WD |
141 | 5, /* size value */ |
142 | 1}, /* ECC enabled */ | |
143 | { 0x07, /* Rev A, 64MByte -2 Board */ | |
144 | 3, /* Case Latenty = 3 */ | |
145 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
33149b88 WD |
146 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
147 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
858b1a64 | 148 | 4, /* tcpt 44 - 20ns = 24ns */ |
33149b88 | 149 | 2, /* Address Mode = 2 */ |
858b1a64 WD |
150 | 4, /* size value */ |
151 | 1}, /* ECC enabled */ | |
3e38691e WD |
152 | { 0x03, /* Rev A, 128MByte -4 Board */ |
153 | 3, /* Case Latenty = 3 */ | |
154 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
33149b88 WD |
155 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
156 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
3e38691e | 157 | 4, /* tcpt 44 - 20ns = 24ns */ |
33149b88 WD |
158 | 3, /* Address Mode = 3 */ |
159 | 5, /* size value */ | |
160 | 1}, /* ECC enabled */ | |
161 | { 0x1f, /* Rev B, 128MByte -3 Board */ | |
162 | 3, /* Case Latenty = 3 */ | |
163 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
164 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ | |
165 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
166 | 4, /* tcpt 44 - 20ns = 24ns */ | |
167 | 3, /* Address Mode = 3 */ | |
3e38691e WD |
168 | 5, /* size value */ |
169 | 1}, /* ECC enabled */ | |
4a551709 WD |
170 | { 0x2f, /* Rev C, 128MByte -3 Board */ |
171 | 3, /* Case Latenty = 3 */ | |
172 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
173 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ | |
174 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
175 | 4, /* tcpt 44 - 20ns = 24ns */ | |
176 | 3, /* Address Mode = 3 */ | |
177 | 5, /* size value */ | |
178 | 1}, /* ECC enabled */ | |
858b1a64 WD |
179 | { 0xff, /* terminator */ |
180 | 0xff, | |
181 | 0xff, | |
182 | 0xff, | |
183 | 0xff, | |
184 | 0xff, | |
185 | 0xff, | |
186 | 0xff } | |
187 | }; | |
f3e0de60 | 188 | #endif /*CONFIG_MIP405T */ |
858b1a64 WD |
189 | void SDRAM_err (const char *s) |
190 | { | |
191 | #ifndef SDRAM_DEBUG | |
858b1a64 WD |
192 | (void) get_clocks (); |
193 | gd->baudrate = 9600; | |
194 | serial_init (); | |
195 | #endif | |
196 | serial_puts ("\n"); | |
197 | serial_puts (s); | |
198 | serial_puts ("\n enable SDRAM_DEBUG for more info\n"); | |
199 | for (;;); | |
200 | } | |
201 | ||
202 | ||
203 | unsigned char get_board_revcfg (void) | |
204 | { | |
205 | out8 (PER_BOARD_ADDR, 0); | |
206 | return (in8 (PER_BOARD_ADDR)); | |
207 | } | |
208 | ||
209 | ||
210 | #ifdef SDRAM_DEBUG | |
211 | ||
212 | void write_hex (unsigned char i) | |
213 | { | |
214 | char cc; | |
215 | ||
216 | cc = i >> 4; | |
217 | cc &= 0xf; | |
218 | if (cc > 9) | |
219 | serial_putc (cc + 55); | |
220 | else | |
221 | serial_putc (cc + 48); | |
222 | cc = i & 0xf; | |
223 | if (cc > 9) | |
224 | serial_putc (cc + 55); | |
225 | else | |
226 | serial_putc (cc + 48); | |
227 | } | |
228 | ||
229 | void write_4hex (unsigned long val) | |
230 | { | |
231 | write_hex ((unsigned char) (val >> 24)); | |
232 | write_hex ((unsigned char) (val >> 16)); | |
233 | write_hex ((unsigned char) (val >> 8)); | |
234 | write_hex ((unsigned char) val); | |
235 | } | |
236 | ||
237 | #endif | |
238 | ||
239 | ||
240 | int init_sdram (void) | |
241 | { | |
858b1a64 WD |
242 | unsigned long tmp, baseaddr; |
243 | unsigned short i; | |
244 | unsigned char trp_clocks, | |
245 | trcd_clocks, | |
246 | tras_clocks, | |
4233fafe | 247 | trc_clocks; |
858b1a64 WD |
248 | unsigned char cal_val; |
249 | unsigned char bc; | |
f3e0de60 | 250 | unsigned long sdram_tim, sdram_bank; |
858b1a64 | 251 | |
6d0f6bcf | 252 | /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/ |
858b1a64 WD |
253 | (void) get_clocks (); |
254 | gd->baudrate = 9600; | |
255 | serial_init (); | |
f3e0de60 | 256 | /* set up the pld */ |
d1c3b275 SR |
257 | mtdcr (EBC0_CFGADDR, PB7AP); |
258 | mtdcr (EBC0_CFGDATA, PLD_AP); | |
259 | mtdcr (EBC0_CFGADDR, PB7CR); | |
260 | mtdcr (EBC0_CFGDATA, PLD_CR); | |
f3e0de60 WD |
261 | /* THIS IS OBSOLETE */ |
262 | /* set up the board rev reg*/ | |
d1c3b275 SR |
263 | mtdcr (EBC0_CFGADDR, PB5AP); |
264 | mtdcr (EBC0_CFGDATA, BOARD_AP); | |
265 | mtdcr (EBC0_CFGADDR, PB5CR); | |
266 | mtdcr (EBC0_CFGDATA, BOARD_CR); | |
f3e0de60 WD |
267 | #ifdef SDRAM_DEBUG |
268 | /* get all informations from PLD */ | |
269 | serial_puts ("\nPLD Part 0x"); | |
270 | bc = in8 (PLD_PART_REG); | |
271 | write_hex (bc); | |
272 | serial_puts ("\nPLD Vers 0x"); | |
273 | bc = in8 (PLD_VERS_REG); | |
274 | write_hex (bc); | |
275 | serial_puts ("\nBoard Rev 0x"); | |
276 | bc = in8 (PLD_BOARD_CFG_REG); | |
277 | write_hex (bc); | |
278 | serial_puts ("\n"); | |
279 | #endif | |
280 | /* check board */ | |
281 | bc = in8 (PLD_PART_REG); | |
282 | #if defined(CONFIG_MIP405T) | |
283 | if((bc & 0x80)==0) | |
284 | SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n"); | |
285 | #else | |
286 | if((bc & 0x80)==0x80) | |
287 | SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); | |
288 | #endif | |
f3e0de60 | 289 | /* set-up the chipselect machine */ |
d1c3b275 SR |
290 | mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */ |
291 | tmp = mfdcr (EBC0_CFGDATA); | |
f3e0de60 | 292 | if ((tmp & 0x00002000) == 0) { |
858b1a64 | 293 | /* MPS Boot, set up the flash */ |
d1c3b275 SR |
294 | mtdcr (EBC0_CFGADDR, PB1AP); |
295 | mtdcr (EBC0_CFGDATA, FLASH_AP); | |
296 | mtdcr (EBC0_CFGADDR, PB1CR); | |
297 | mtdcr (EBC0_CFGDATA, FLASH_CR); | |
858b1a64 WD |
298 | } else { |
299 | /* Flash boot, set up the MPS */ | |
d1c3b275 SR |
300 | mtdcr (EBC0_CFGADDR, PB1AP); |
301 | mtdcr (EBC0_CFGDATA, MPS_AP); | |
302 | mtdcr (EBC0_CFGADDR, PB1CR); | |
303 | mtdcr (EBC0_CFGDATA, MPS_CR); | |
858b1a64 WD |
304 | } |
305 | /* set up UART0 (CS2) and UART1 (CS3) */ | |
d1c3b275 SR |
306 | mtdcr (EBC0_CFGADDR, PB2AP); |
307 | mtdcr (EBC0_CFGDATA, UART0_AP); | |
308 | mtdcr (EBC0_CFGADDR, PB2CR); | |
309 | mtdcr (EBC0_CFGDATA, UART0_CR); | |
310 | mtdcr (EBC0_CFGADDR, PB3AP); | |
311 | mtdcr (EBC0_CFGDATA, UART1_AP); | |
312 | mtdcr (EBC0_CFGADDR, PB3CR); | |
313 | mtdcr (EBC0_CFGDATA, UART1_CR); | |
f3e0de60 | 314 | bc = in8 (PLD_BOARD_CFG_REG); |
858b1a64 WD |
315 | #ifdef SDRAM_DEBUG |
316 | serial_puts ("\nstart SDRAM Setup\n"); | |
317 | serial_puts ("\nBoard Rev: "); | |
318 | write_hex (bc); | |
319 | serial_puts ("\n"); | |
320 | #endif | |
321 | i = 0; | |
6d0f6bcf | 322 | baseaddr = CONFIG_SYS_SDRAM_BASE; |
858b1a64 WD |
323 | while (sdram_table[i].sz != 0xff) { |
324 | if (sdram_table[i].boardtype == bc) | |
325 | break; | |
326 | i++; | |
327 | } | |
328 | if (sdram_table[i].boardtype != bc) | |
329 | SDRAM_err ("No SDRAM table found for this board!!!\n"); | |
330 | #ifdef SDRAM_DEBUG | |
331 | serial_puts (" found table "); | |
332 | write_hex (i); | |
333 | serial_puts (" \n"); | |
334 | #endif | |
27b207fd WD |
335 | /* since the ECC initialisation needs some time, |
336 | * we show that we're alive | |
337 | */ | |
338 | if (sdram_table[i].ecc) | |
339 | serial_puts ("\nInitializing SDRAM, Please stand by"); | |
858b1a64 WD |
340 | cal_val = sdram_table[i].cal - 1; /* Cas Latency */ |
341 | trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */ | |
342 | trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ | |
343 | tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ | |
344 | /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ | |
858b1a64 WD |
345 | /* trc_clocks is sum of trp_clocks + tras_clocks */ |
346 | trc_clocks = trp_clocks + tras_clocks; | |
347 | /* get SDRAM timing register */ | |
95b602ba | 348 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
d1c3b275 | 349 | sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; |
858b1a64 WD |
350 | /* insert CASL value */ |
351 | sdram_tim |= ((unsigned long) (cal_val)) << 23; | |
352 | /* insert PTA value */ | |
353 | sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18; | |
354 | /* insert CTP value */ | |
355 | sdram_tim |= | |
356 | ((unsigned long) (trc_clocks - trp_clocks - | |
357 | trcd_clocks)) << 16; | |
358 | /* insert LDF (always 01) */ | |
359 | sdram_tim |= ((unsigned long) 0x01) << 14; | |
360 | /* insert RFTA value */ | |
361 | sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2; | |
362 | /* insert RCD value */ | |
363 | sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0; | |
364 | ||
365 | tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */ | |
366 | /* insert SZ value; */ | |
367 | tmp |= ((unsigned long) sdram_table[i].sz << 17); | |
368 | /* get SDRAM bank 0 register */ | |
95b602ba | 369 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 370 | sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
858b1a64 WD |
371 | sdram_bank |= (baseaddr | tmp | 0x01); |
372 | ||
373 | #ifdef SDRAM_DEBUG | |
374 | serial_puts ("sdtr: "); | |
375 | write_4hex (sdram_tim); | |
376 | serial_puts ("\n"); | |
377 | #endif | |
378 | ||
379 | /* write SDRAM timing register */ | |
95b602ba | 380 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
d1c3b275 | 381 | mtdcr (SDRAM0_CFGDATA, sdram_tim); |
858b1a64 WD |
382 | |
383 | #ifdef SDRAM_DEBUG | |
384 | serial_puts ("mb0cf: "); | |
385 | write_4hex (sdram_bank); | |
386 | serial_puts ("\n"); | |
387 | #endif | |
388 | ||
389 | /* write SDRAM bank 0 register */ | |
95b602ba | 390 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 391 | mtdcr (SDRAM0_CFGDATA, sdram_bank); |
858b1a64 WD |
392 | |
393 | if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ | |
394 | /* get SDRAM refresh interval register */ | |
95b602ba | 395 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
d1c3b275 | 396 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; |
858b1a64 WD |
397 | tmp |= 0x07F00000; |
398 | } else { | |
399 | /* get SDRAM refresh interval register */ | |
95b602ba | 400 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
d1c3b275 | 401 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; |
858b1a64 WD |
402 | tmp |= 0x05F00000; |
403 | } | |
404 | /* write SDRAM refresh interval register */ | |
95b602ba | 405 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
d1c3b275 | 406 | mtdcr (SDRAM0_CFGDATA, tmp); |
858b1a64 | 407 | /* enable ECC if used */ |
f3e0de60 | 408 | #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) |
858b1a64 WD |
409 | if (sdram_table[i].ecc) { |
410 | /* disable checking for all banks */ | |
f3e0de60 | 411 | unsigned long *p; |
858b1a64 WD |
412 | #ifdef SDRAM_DEBUG |
413 | serial_puts ("disable ECC.. "); | |
414 | #endif | |
95b602ba | 415 | mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); |
d1c3b275 | 416 | tmp = mfdcr (SDRAM0_CFGDATA); |
858b1a64 | 417 | tmp &= 0xff0fffff; /* disable all banks */ |
95b602ba | 418 | mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); |
858b1a64 WD |
419 | /* set up SDRAM Controller with ECC enabled */ |
420 | #ifdef SDRAM_DEBUG | |
421 | serial_puts ("setup SDRAM Controller.. "); | |
422 | #endif | |
d1c3b275 | 423 | mtdcr (SDRAM0_CFGDATA, tmp); |
95b602ba | 424 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 425 | tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; |
95b602ba | 426 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 427 | mtdcr (SDRAM0_CFGDATA, tmp); |
858b1a64 WD |
428 | udelay (600); |
429 | #ifdef SDRAM_DEBUG | |
430 | serial_puts ("fill the memory..\n"); | |
431 | #endif | |
432 | serial_puts ("."); | |
433 | /* now, fill all the memory */ | |
434 | tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz); | |
435 | p = (unsigned long) 0; | |
436 | while ((unsigned long) p < tmp) { | |
437 | *p++ = 0L; | |
438 | if (!((unsigned long) p % 0x00800000)) /* every 8MByte */ | |
439 | serial_puts ("."); | |
858b1a64 WD |
440 | } |
441 | /* enable bank 0 */ | |
442 | serial_puts ("."); | |
443 | #ifdef SDRAM_DEBUG | |
444 | serial_puts ("enable ECC\n"); | |
445 | #endif | |
446 | udelay (400); | |
95b602ba | 447 | mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); |
d1c3b275 | 448 | tmp = mfdcr (SDRAM0_CFGDATA); |
858b1a64 | 449 | tmp |= 0x00800000; /* enable bank 0 */ |
d1c3b275 | 450 | mtdcr (SDRAM0_CFGDATA, tmp); |
858b1a64 WD |
451 | udelay (400); |
452 | } else | |
453 | #endif | |
454 | { | |
455 | /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ | |
95b602ba | 456 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 457 | tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; |
95b602ba | 458 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 459 | mtdcr (SDRAM0_CFGDATA, tmp); |
858b1a64 WD |
460 | udelay (400); |
461 | } | |
462 | serial_puts ("\n"); | |
463 | return (0); | |
464 | } | |
465 | ||
c837dcb1 | 466 | int board_early_init_f (void) |
858b1a64 WD |
467 | { |
468 | init_sdram (); | |
469 | ||
470 | /*-------------------------------------------------------------------------+ | |
471 | | Interrupt controller setup for the PIP405 board. | |
472 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
473 | | IRQ 16 405GP internally generated; active low; level sensitive | |
474 | | IRQ 17-24 RESERVED | |
475 | | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive | |
476 | | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive | |
477 | | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive | |
478 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive | |
479 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
480 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive | |
481 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive | |
482 | | Note for MIP405 board: | |
483 | | An interrupt taken for the SouthBridge (IRQ 25) indicates that | |
484 | | the Interrupt Controller in the South Bridge has caused the | |
485 | | interrupt. The IC must be read to determine which device | |
486 | | caused the interrupt. | |
487 | | | |
488 | +-------------------------------------------------------------------------*/ | |
952e7760 SR |
489 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
490 | mtdcr (UIC0ER, 0x00000000); /* disable all ints */ | |
491 | mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ | |
492 | mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ | |
493 | mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ | |
494 | mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
495 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
858b1a64 WD |
496 | return 0; |
497 | } | |
498 | ||
39441b35 DM |
499 | int board_early_init_r(void) |
500 | { | |
501 | int mode; | |
502 | ||
503 | /* | |
504 | * since we are relocated, we can finally enable i-cache | |
505 | * and set up the flash CS correctly | |
506 | */ | |
507 | icache_enable(); | |
508 | setup_cs_reloc(); | |
509 | /* get and display boot mode */ | |
510 | mode = get_boot_mode(); | |
511 | if (mode & BOOT_PCI) | |
512 | printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? | |
513 | "MPS" : "Flash"); | |
514 | else | |
515 | printf("%s Boot\n", (mode & BOOT_MPS) ? | |
516 | "MPS" : "Flash"); | |
517 | ||
518 | return 0; | |
519 | } | |
858b1a64 WD |
520 | |
521 | /* | |
522 | * Get some PLD Registers | |
523 | */ | |
524 | ||
525 | unsigned short get_pld_parvers (void) | |
526 | { | |
527 | unsigned short result; | |
528 | unsigned char rc; | |
529 | ||
530 | rc = in8 (PLD_PART_REG); | |
531 | result = (unsigned short) rc << 8; | |
532 | rc = in8 (PLD_VERS_REG); | |
533 | result |= rc; | |
534 | return result; | |
535 | } | |
536 | ||
537 | ||
858b1a64 WD |
538 | void user_led0 (unsigned char on) |
539 | { | |
540 | if (on) | |
541 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4)); | |
542 | else | |
543 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb)); | |
544 | } | |
545 | ||
546 | ||
547 | void ide_set_reset (int idereset) | |
548 | { | |
549 | /* if reset = 1 IDE reset will be asserted */ | |
550 | if (idereset) | |
551 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1)); | |
552 | else { | |
553 | udelay (10000); | |
554 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe)); | |
555 | } | |
556 | } | |
557 | ||
558 | ||
559 | /* ------------------------------------------------------------------------- */ | |
560 | ||
f3e0de60 | 561 | void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var) |
858b1a64 | 562 | { |
f3e0de60 WD |
563 | #if !defined(CONFIG_MIP405T) |
564 | unsigned char bc,rc,tmp; | |
858b1a64 | 565 | int i; |
858b1a64 | 566 | |
f3e0de60 WD |
567 | bc = in8 (PLD_BOARD_CFG_REG); |
568 | tmp = ~bc; | |
569 | tmp &= 0xf; | |
858b1a64 WD |
570 | rc = 0; |
571 | for (i = 0; i < 4; i++) { | |
572 | rc <<= 1; | |
f3e0de60 WD |
573 | rc += (tmp & 0x1); |
574 | tmp >>= 1; | |
858b1a64 WD |
575 | } |
576 | rc++; | |
4a551709 WD |
577 | if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */ |
578 | || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */ | |
33149b88 WD |
579 | && (rc==0x1)) /* Population Option 1 is a -3 */ |
580 | rc=3; | |
f3e0de60 WD |
581 | *pcbrev=(bc >> 4) & 0xf; |
582 | *var=rc; | |
583 | #else | |
584 | unsigned char bc; | |
585 | bc = in8 (PLD_BOARD_CFG_REG); | |
586 | *pcbrev=(bc >> 4) & 0xf; | |
27b207fd | 587 | *var=16-(bc & 0xf); |
f3e0de60 WD |
588 | #endif |
589 | } | |
590 | ||
591 | /* | |
592 | * Check Board Identity: | |
593 | */ | |
594 | /* serial String: "MIP405_1000" OR "MIP405T_1000" */ | |
595 | #if !defined(CONFIG_MIP405T) | |
596 | #define BOARD_NAME "MIP405" | |
597 | #else | |
598 | #define BOARD_NAME "MIP405T" | |
599 | #endif | |
600 | ||
601 | int checkboard (void) | |
602 | { | |
77ddac94 | 603 | char s[50]; |
f3e0de60 WD |
604 | unsigned char bc, var; |
605 | int i; | |
606 | backup_t *b = (backup_t *) s; | |
607 | ||
608 | puts ("Board: "); | |
609 | get_pcbrev_var(&bc,&var); | |
cdb74977 | 610 | i = getenv_f("serial#", (char *)s, 32); |
77ddac94 | 611 | if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) { |
858b1a64 WD |
612 | get_backup_values (b); |
613 | if (strncmp (b->signature, "MPL\0", 4) != 0) { | |
f3e0de60 WD |
614 | puts ("### No HW ID - assuming " BOARD_NAME); |
615 | printf ("-%d Rev %c", var, 'A' + bc); | |
858b1a64 | 616 | } else { |
f3e0de60 WD |
617 | b->serial_name[sizeof(BOARD_NAME)-1] = 0; |
618 | printf ("%s-%d Rev %c SN: %s", b->serial_name, var, | |
619 | 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]); | |
858b1a64 WD |
620 | } |
621 | } else { | |
f3e0de60 WD |
622 | s[sizeof(BOARD_NAME)-1] = 0; |
623 | printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc, | |
624 | &s[sizeof(BOARD_NAME)]); | |
858b1a64 WD |
625 | } |
626 | bc = in8 (PLD_EXT_CONF_REG); | |
627 | printf (" Boot Config: 0x%x\n", bc); | |
628 | return (0); | |
629 | } | |
630 | ||
631 | ||
632 | /* ------------------------------------------------------------------------- */ | |
633 | /* ------------------------------------------------------------------------- */ | |
634 | /* | |
635 | initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of | |
636 | the necessary info for SDRAM controller configuration | |
637 | */ | |
638 | /* ------------------------------------------------------------------------- */ | |
639 | /* ------------------------------------------------------------------------- */ | |
640 | static int test_dram (unsigned long ramsize); | |
641 | ||
9973e3c6 | 642 | phys_size_t initdram (int board_type) |
858b1a64 WD |
643 | { |
644 | ||
645 | unsigned long bank_reg[4], tmp, bank_size; | |
4233fafe | 646 | int i; |
858b1a64 WD |
647 | unsigned long TotalSize; |
648 | ||
858b1a64 WD |
649 | /* since the DRAM controller is allready set up, calculate the size with the |
650 | bank registers */ | |
95b602ba | 651 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 652 | bank_reg[0] = mfdcr (SDRAM0_CFGDATA); |
95b602ba | 653 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
d1c3b275 | 654 | bank_reg[1] = mfdcr (SDRAM0_CFGDATA); |
95b602ba | 655 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
d1c3b275 | 656 | bank_reg[2] = mfdcr (SDRAM0_CFGDATA); |
95b602ba | 657 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
d1c3b275 | 658 | bank_reg[3] = mfdcr (SDRAM0_CFGDATA); |
858b1a64 WD |
659 | TotalSize = 0; |
660 | for (i = 0; i < 4; i++) { | |
661 | if ((bank_reg[i] & 0x1) == 0x1) { | |
662 | tmp = (bank_reg[i] >> 17) & 0x7; | |
663 | bank_size = 4 << tmp; | |
664 | TotalSize += bank_size; | |
4233fafe | 665 | } |
858b1a64 | 666 | } |
95b602ba | 667 | mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); |
d1c3b275 | 668 | tmp = mfdcr (SDRAM0_CFGDATA); |
858b1a64 WD |
669 | |
670 | if (!tmp) | |
671 | printf ("No "); | |
672 | printf ("ECC "); | |
673 | ||
674 | test_dram (TotalSize * MEGA_BYTE); | |
675 | return (TotalSize * MEGA_BYTE); | |
676 | } | |
677 | ||
678 | /* ------------------------------------------------------------------------- */ | |
679 | ||
858b1a64 WD |
680 | |
681 | static int test_dram (unsigned long ramsize) | |
682 | { | |
683 | #ifdef SDRAM_DEBUG | |
684 | mem_test (0L, ramsize, 1); | |
685 | #endif | |
686 | /* not yet implemented */ | |
687 | return (1); | |
688 | } | |
689 | ||
27b207fd WD |
690 | /* used to check if the time in RTC is valid */ |
691 | static unsigned long start; | |
692 | static struct rtc_time tm; | |
693 | ||
858b1a64 WD |
694 | int misc_init_r (void) |
695 | { | |
7205e407 WD |
696 | /* adjust flash start and size as well as the offset */ |
697 | gd->bd->bi_flashstart=0-flash_info[0].size; | |
6d0f6bcf | 698 | gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; |
7205e407 WD |
699 | gd->bd->bi_flashoffset=0; |
700 | ||
27b207fd WD |
701 | /* check, if RTC is running */ |
702 | rtc_get (&tm); | |
703 | start=get_timer(0); | |
f3e0de60 | 704 | /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ |
d1c3b275 | 705 | if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) |
58ea142f | 706 | mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); |
f3e0de60 | 707 | |
858b1a64 WD |
708 | return (0); |
709 | } | |
710 | ||
711 | ||
712 | void print_mip405_rev (void) | |
713 | { | |
f3e0de60 WD |
714 | unsigned char part, vers, pcbrev, var; |
715 | ||
716 | get_pcbrev_var(&pcbrev,&var); | |
858b1a64 WD |
717 | part = in8 (PLD_PART_REG); |
718 | vers = in8 (PLD_VERS_REG); | |
f3e0de60 WD |
719 | printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n", |
720 | var, pcbrev + 'A', part & 0x7F, vers); | |
858b1a64 WD |
721 | } |
722 | ||
63e73c9a | 723 | |
27b207fd | 724 | extern int mk_date (char *, struct rtc_time *); |
858b1a64 WD |
725 | |
726 | int last_stage_init (void) | |
727 | { | |
27b207fd WD |
728 | unsigned long stop; |
729 | struct rtc_time newtm; | |
77ddac94 | 730 | char *s; |
331ab60c | 731 | |
3e38691e | 732 | /* write correct LED configuration */ |
63ff004c | 733 | if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) { |
858b1a64 WD |
734 | printf ("Error writing to the PHY\n"); |
735 | } | |
3e38691e WD |
736 | /* since LED/CFG2 is not connected on the -2, |
737 | * write to correct capability information */ | |
63ff004c | 738 | if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) { |
3e38691e WD |
739 | printf ("Error writing to the PHY\n"); |
740 | } | |
858b1a64 | 741 | print_mip405_rev (); |
28c34504 | 742 | stdio_print_current_devices (); |
858b1a64 | 743 | check_env (); |
27b207fd WD |
744 | /* check if RTC time is valid */ |
745 | stop=get_timer(start); | |
746 | while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */ | |
747 | udelay(1000); | |
748 | stop=get_timer(start); | |
749 | } | |
750 | rtc_get (&newtm); | |
751 | if(tm.tm_sec==newtm.tm_sec) { | |
752 | s=getenv("defaultdate"); | |
753 | if(!s) | |
754 | mk_date ("010112001970", &newtm); | |
755 | else | |
756 | if(mk_date (s, &newtm)!=0) { | |
757 | printf("RTC: Bad date format in defaultdate\n"); | |
758 | return 0; | |
759 | } | |
760 | rtc_reset (); | |
761 | rtc_set(&newtm); | |
762 | } | |
858b1a64 WD |
763 | return 0; |
764 | } | |
765 | ||
766 | /*************************************************************************** | |
767 | * some helping routines | |
768 | */ | |
769 | ||
770 | int overwrite_console (void) | |
771 | { | |
472d5460 YS |
772 | /* return true if console should be overwritten */ |
773 | return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0); | |
858b1a64 WD |
774 | } |
775 | ||
776 | ||
777 | /************************************************************************ | |
778 | * Print MIP405 Info | |
779 | ************************************************************************/ | |
780 | void print_mip405_info (void) | |
781 | { | |
782 | unsigned char part, vers, cfg, irq_reg, com_mode, ext; | |
783 | ||
784 | part = in8 (PLD_PART_REG); | |
785 | vers = in8 (PLD_VERS_REG); | |
786 | cfg = in8 (PLD_BOARD_CFG_REG); | |
787 | irq_reg = in8 (PLD_IRQ_REG); | |
788 | com_mode = in8 (PLD_COM_MODE_REG); | |
789 | ext = in8 (PLD_EXT_CONF_REG); | |
790 | ||
f3e0de60 | 791 | printf ("PLD Part %d version %d\n", part & 0x7F, vers); |
858b1a64 WD |
792 | printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A'); |
793 | printf ("Population Options %d %d %d %d\n", (cfg) & 0x1, | |
794 | (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1); | |
795 | printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off"); | |
796 | printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3); | |
f3e0de60 | 797 | #if !defined(CONFIG_MIP405T) |
858b1a64 WD |
798 | printf ("User Config Switch %d %d %d %d %d %d %d %d\n", |
799 | (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, | |
800 | (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, | |
801 | (ext >> 6) & 0x1, (ext >> 7) & 0x1); | |
802 | printf ("SER1 uses handshakes %s\n", | |
803 | (ext & 0x80) ? "DTR/DSR" : "RTS/CTS"); | |
f3e0de60 | 804 | #else |
27b207fd | 805 | printf ("User Config Switch %d %d %d %d %d %d %d %d\n", |
f3e0de60 WD |
806 | (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, |
807 | (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, | |
27b207fd | 808 | (ext >> 6) & 0x1,(ext >> 7) & 0x1); |
f3e0de60 | 809 | #endif |
858b1a64 WD |
810 | printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted"); |
811 | printf ("IRQs:\n"); | |
812 | printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active"); | |
f3e0de60 | 813 | #if !defined(CONFIG_MIP405T) |
858b1a64 WD |
814 | printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active"); |
815 | printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active"); | |
f3e0de60 | 816 | #endif |
858b1a64 WD |
817 | printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active"); |
818 | printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active"); | |
819 | printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active"); | |
820 | } |