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Commit | Line | Data |
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3a473b2a WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Denis Peter, d.peter@mpl.ch | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
3a473b2a WD |
5 | */ |
6 | /* PLX9096 register definitions | |
7 | */ | |
8 | #ifndef __PLX9056_H_ | |
9 | #define __PLX9056_H_ 1 | |
10 | ||
11 | #include <pci.h> | |
12 | ||
13 | #ifdef PLX9056_LOC | |
14 | #define LOCAL_OFFSET 0x080 | |
15 | /* PCI Config regs */ | |
16 | #else | |
17 | #define LOCAL_OFFSET 0x000 | |
18 | #endif | |
19 | ||
20 | #define PCI9056_VENDOR_ID PCI_VENDOR_ID | |
21 | /*#define PCI9656_DEVICE_ID PCI_DEVICE_ID */ | |
22 | #define PCI9056_COMMAND PCI_COMMAND | |
23 | /*#define PCI9656_STATUS PCI_STATUS */ | |
24 | #define PCI9056_REVISION PCI_REVISION_ID | |
25 | ||
26 | #define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE | |
27 | #define PCI9056_RTR_BASE PCI_BASE_ADDRESS_0 | |
28 | #define PCI9056_RTR_IO_BASE PCI_BASE_ADDRESS_1 | |
29 | #define PCI9056_LOCAL_BASE0 PCI_BASE_ADDRESS_2 | |
30 | #define PCI9056_LOCAL_BASE1 PCI_BASE_ADDRESS_3 | |
31 | #define PCI9056_UNUSED_BASE1 PCI_BASE_ADDRESS_4 | |
32 | #define PCI9056_UNUSED_BASE2 PCI_BASE_ADDRESS_5 | |
33 | #define PCI9056_CIS_PTR PCI_CARDBUS_CIS | |
34 | #define PCI9056_SUB_ID PCI_SUBSYSTEM_VENDOR_ID | |
35 | #define PCI9056_EXP_ROM_BASE PCI_ROM_ADDRESS | |
36 | #define PCI9056_CAP_PTR PCI_CAPABILITY_LIST | |
37 | #define PCI9056_INT_LINE PCI_INTERRUPT_LINE | |
38 | ||
39 | #if defined(PLX9056_LOC) | |
40 | #define PCI9056_PM_CAP_ID 0x180 | |
41 | #define PCI9056_PM_CSR 0x184 | |
42 | #define PCI9056_HS_CAP_ID 0x188 | |
43 | #define PCI9056_VPD_CAP_ID 0x18C | |
44 | #define PCI9056_VPD_DATA 0x190 | |
45 | #endif | |
46 | ||
47 | ||
3a473b2a WD |
48 | #define PCI_DEVICE_ID_PLX9056 0x9056 |
49 | ||
50 | /* Local Configuration Registers Accessible via the PCI Base address + Variable */ | |
51 | #define PCI9056_SPACE0_RANGE (0x000 + LOCAL_OFFSET) | |
52 | #define PCI9056_SPACE0_REMAP (0x004 + LOCAL_OFFSET) | |
53 | #define PCI9056_LOCAL_DMA_ARBIT (0x008 + LOCAL_OFFSET) | |
54 | #define PCI9056_ENDIAN_DESC (0x00c + LOCAL_OFFSET) | |
55 | #define PCI9056_EXP_ROM_RANGE (0x010 + LOCAL_OFFSET) | |
56 | #define PCI9056_EXP_ROM_REMAP (0x014 + LOCAL_OFFSET) | |
57 | #define PCI9056_SPACE0_ROM_DESC (0x018 + LOCAL_OFFSET) | |
58 | #define PCI9056_DM_RANGE (0x01c + LOCAL_OFFSET) | |
59 | #define PCI9056_DM_MEM_BASE (0x020 + LOCAL_OFFSET) | |
60 | #define PCI9056_DM_IO_BASE (0x024 + LOCAL_OFFSET) | |
61 | #define PCI9056_DM_PCI_MEM_REMAP (0x028 + LOCAL_OFFSET) | |
62 | #define PCI9056_DM_PCI_IO_CONFIG (0x02c + LOCAL_OFFSET) | |
63 | #define PCI9056_SPACE1_RANGE (0x0f0 + LOCAL_OFFSET) | |
64 | #define PCI9056_SPACE1_REMAP (0x0f4 + LOCAL_OFFSET) | |
65 | #define PCI9056_SPACE1_DESC (0x0f8 + LOCAL_OFFSET) | |
66 | #define PCI9056_DM_DAC (0x0fc + LOCAL_OFFSET) | |
67 | ||
68 | #ifdef PLX9056_LOC | |
69 | #define PCI9056_ARBITER_CTRL 0x1A0 | |
70 | #define PCI9056_ABORT_ADDRESS 0x1A4 | |
71 | #endif | |
72 | ||
73 | /* Runtime registers PCI Address + LOCAL_OFFSET */ | |
74 | #ifdef PLX9056_LOC | |
75 | #define PCI9056_MAILBOX0 0x0C0 | |
76 | #define PCI9056_MAILBOX1 0x0C4 | |
77 | #else | |
78 | #define PCI9056_MAILBOX0 0x078 | |
79 | #define PCI9056_MAILBOX1 0x07c | |
80 | #endif | |
81 | ||
82 | #define PCI9056_MAILBOX2 (0x048 + LOCAL_OFFSET) | |
83 | #define PCI9056_MAILBOX3 (0x04c + LOCAL_OFFSET) | |
84 | #define PCI9056_MAILBOX4 (0x050 + LOCAL_OFFSET) | |
85 | #define PCI9056_MAILBOX5 (0x054 + LOCAL_OFFSET) | |
86 | #define PCI9056_MAILBOX6 (0x058 + LOCAL_OFFSET) | |
87 | #define PCI9056_MAILBOX7 (0x05c + LOCAL_OFFSET) | |
88 | #define PCI9056_PCI_TO_LOC_DBELL (0x060 + LOCAL_OFFSET) | |
89 | #define PCI9056_LOC_TO_PCI_DBELL (0x064 + LOCAL_OFFSET) | |
90 | #define PCI9056_INT_CTRL_STAT (0x068 + LOCAL_OFFSET) | |
91 | #define PCI9056_EEPROM_CTRL_STAT (0x06c + LOCAL_OFFSET) | |
92 | #define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET) | |
93 | #define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET) | |
94 | ||
3a473b2a | 95 | #endif /* #ifndef __PLX9056_H_ */ |