projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7d393aed WD |
1 | /* |
| 2 | * (C) Copyright 2001 | |
| 3 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | * | |
| 23 | * | |
| 24 | * TODO: clean-up | |
| 25 | */ | |
| 26 | ||
| 27 | #include <common.h> | |
| 28 | #include "pip405.h" | |
| 29 | #include <asm/processor.h> | |
| 30 | #include <i2c.h> | |
| 28c34504 | 31 | #include <stdio_dev.h> |
| 7d393aed WD |
32 | #include "../common/isa.h" |
| 33 | #include "../common/common_util.h" | |
| 34 | ||
| d87080b7 WD |
35 | DECLARE_GLOBAL_DATA_PTR; |
| 36 | ||
| 7d393aed WD |
37 | #undef SDRAM_DEBUG |
| 38 | ||
| 39 | #define FALSE 0 | |
| 40 | #define TRUE 1 | |
| 41 | ||
| 42 | /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ | |
| 43 | #ifndef __ldiv_t_defined | |
| 44 | typedef struct { | |
| 45 | long int quot; /* Quotient */ | |
| 46 | long int rem; /* Remainder */ | |
| 47 | } ldiv_t; | |
| 48 | extern ldiv_t ldiv (long int __numer, long int __denom); | |
| 49 | ||
| 50 | # define __ldiv_t_defined 1 | |
| 51 | #endif | |
| 52 | ||
| 53 | ||
| 54 | typedef enum { | |
| 55 | SDRAM_NO_ERR, | |
| 56 | SDRAM_SPD_COMM_ERR, | |
| 57 | SDRAM_SPD_CHKSUM_ERR, | |
| 58 | SDRAM_UNSUPPORTED_ERR, | |
| 59 | SDRAM_UNKNOWN_ERR | |
| 60 | } SDRAM_ERR; | |
| 61 | ||
| 62 | typedef struct { | |
| 63 | const unsigned char mode; | |
| 64 | const unsigned char row; | |
| 65 | const unsigned char col; | |
| 66 | const unsigned char bank; | |
| 67 | } SDRAM_SETUP; | |
| 68 | ||
| 69 | static const SDRAM_SETUP sdram_setup_table[] = { | |
| 70 | {1, 11, 9, 2}, | |
| 71 | {1, 11, 10, 2}, | |
| 72 | {2, 12, 9, 4}, | |
| 73 | {2, 12, 10, 4}, | |
| 74 | {3, 13, 9, 4}, | |
| 75 | {3, 13, 10, 4}, | |
| 76 | {3, 13, 11, 4}, | |
| 77 | {4, 12, 8, 2}, | |
| 78 | {4, 12, 8, 4}, | |
| 79 | {5, 11, 8, 2}, | |
| 80 | {5, 11, 8, 4}, | |
| 81 | {6, 13, 8, 2}, | |
| 82 | {6, 13, 8, 4}, | |
| 83 | {7, 13, 9, 2}, | |
| 84 | {7, 13, 10, 2}, | |
| 85 | {0, 0, 0, 0} | |
| 86 | }; | |
| 87 | ||
| 88 | static const unsigned char cal_indextable[] = { | |
| 89 | 9, 23, 25 | |
| 90 | }; | |
| 91 | ||
| 92 | ||
| 93 | /* | |
| 94 | * translate ns.ns/10 coding of SPD timing values | |
| 95 | * into 10 ps unit values | |
| 96 | */ | |
| 97 | ||
| 98 | unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version) | |
| 99 | { | |
| 100 | unsigned short ns, ns10; | |
| 101 | ||
| 102 | /* isolate upper nibble */ | |
| 103 | ns = (spd_byte >> 4) & 0x0F; | |
| 104 | /* isolate lower nibble */ | |
| 105 | ns10 = (spd_byte & 0x0F); | |
| 106 | ||
| 107 | return (ns * 100 + ns10 * 10); | |
| 108 | } | |
| 109 | ||
| 110 | /* | |
| 111 | * translate ns.ns/4 coding of SPD timing values | |
| 112 | * into 10 ps unit values | |
| 113 | */ | |
| 114 | ||
| 115 | unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version) | |
| 116 | { | |
| 117 | unsigned short ns, ns4; | |
| 118 | ||
| 119 | /* isolate upper 6 bits */ | |
| 120 | ns = (spd_byte >> 2) & 0x3F; | |
| 121 | /* isloate lower 2 bits */ | |
| 122 | ns4 = (spd_byte & 0x03); | |
| 123 | ||
| 124 | return (ns * 100 + ns4 * 25); | |
| 125 | } | |
| 126 | ||
| 127 | /* | |
| 128 | * translate ns coding of SPD timing values | |
| 129 | * into 10 ps unit values | |
| 130 | */ | |
| 131 | ||
| 132 | unsigned short NSto10PS (unsigned char spd_byte) | |
| 133 | { | |
| 134 | return (spd_byte * 100); | |
| 135 | } | |
| 136 | ||
| 137 | void SDRAM_err (const char *s) | |
| 138 | { | |
| 139 | #ifndef SDRAM_DEBUG | |
| 7d393aed WD |
140 | (void) get_clocks (); |
| 141 | gd->baudrate = 9600; | |
| 142 | serial_init (); | |
| 143 | #endif | |
| 144 | serial_puts ("\n"); | |
| 145 | serial_puts (s); | |
| 146 | serial_puts ("\n enable SDRAM_DEBUG for more info\n"); | |
| 147 | for (;;); | |
| 148 | } | |
| 149 | ||
| 150 | ||
| 151 | #ifdef SDRAM_DEBUG | |
| 152 | ||
| 153 | void write_hex (unsigned char i) | |
| 154 | { | |
| 155 | char cc; | |
| 156 | ||
| 157 | cc = i >> 4; | |
| 158 | cc &= 0xf; | |
| 159 | if (cc > 9) | |
| 160 | serial_putc (cc + 55); | |
| 161 | else | |
| 162 | serial_putc (cc + 48); | |
| 163 | cc = i & 0xf; | |
| 164 | if (cc > 9) | |
| 165 | serial_putc (cc + 55); | |
| 166 | else | |
| 167 | serial_putc (cc + 48); | |
| 168 | } | |
| 169 | ||
| 170 | void write_4hex (unsigned long val) | |
| 171 | { | |
| 172 | write_hex ((unsigned char) (val >> 24)); | |
| 173 | write_hex ((unsigned char) (val >> 16)); | |
| 174 | write_hex ((unsigned char) (val >> 8)); | |
| 175 | write_hex ((unsigned char) val); | |
| 176 | } | |
| 177 | ||
| 178 | #endif | |
| 179 | ||
| c837dcb1 | 180 | int board_early_init_f (void) |
| 7d393aed | 181 | { |
| 7d393aed | 182 | unsigned char datain[128]; |
| 77ddac94 | 183 | unsigned long sdram_size = 0; |
| 7d393aed WD |
184 | SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; |
| 185 | unsigned long memclk; | |
| 186 | unsigned long tmemclk = 0; | |
| 187 | unsigned long tmp, bank, baseaddr, bank_size; | |
| 188 | unsigned short i; | |
| 189 | unsigned char rows, cols, banks, sdram_banks, density; | |
| 190 | unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, | |
| 4e11c351 | 191 | trc_clocks; |
| 7d393aed WD |
192 | unsigned char cal_index, cal_val, spd_version, spd_chksum; |
| 193 | unsigned char buf[8]; | |
| 4e11c351 SR |
194 | #ifdef SDRAM_DEBUG |
| 195 | unsigned char tctp_clocks; | |
| 196 | #endif | |
| 197 | ||
| 7205e407 | 198 | /* set up the config port */ |
| d1c3b275 SR |
199 | mtdcr (EBC0_CFGADDR, PB7AP); |
| 200 | mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); | |
| 201 | mtdcr (EBC0_CFGADDR, PB7CR); | |
| 202 | mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR); | |
| 7d393aed WD |
203 | |
| 204 | memclk = get_bus_freq (tmemclk); | |
| 205 | tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ | |
| 206 | ||
| 207 | #ifdef SDRAM_DEBUG | |
| 208 | (void) get_clocks (); | |
| 209 | gd->baudrate = 9600; | |
| 210 | serial_init (); | |
| 211 | serial_puts ("\nstart SDRAM Setup\n"); | |
| 212 | #endif | |
| 213 | ||
| 214 | /* Read Serial Presence Detect Information */ | |
| 6d0f6bcf | 215 | i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 7d393aed WD |
216 | for (i = 0; i < 128; i++) |
| 217 | datain[i] = 127; | |
| 218 | i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); | |
| 219 | #ifdef SDRAM_DEBUG | |
| 220 | serial_puts ("\ni2c_read returns "); | |
| 221 | write_hex (i); | |
| 222 | serial_puts ("\n"); | |
| 223 | #endif | |
| 224 | ||
| 225 | #ifdef SDRAM_DEBUG | |
| 226 | for (i = 0; i < 128; i++) { | |
| 227 | write_hex (datain[i]); | |
| 228 | serial_puts (" "); | |
| 229 | if (((i + 1) % 16) == 0) | |
| 230 | serial_puts ("\n"); | |
| 231 | } | |
| 232 | serial_puts ("\n"); | |
| 233 | #endif | |
| 234 | spd_chksum = 0; | |
| 235 | for (i = 0; i < 63; i++) { | |
| 236 | spd_chksum += datain[i]; | |
| 237 | } /* endfor */ | |
| 238 | if (datain[63] != spd_chksum) { | |
| 239 | #ifdef SDRAM_DEBUG | |
| 240 | serial_puts ("SPD chksum: 0x"); | |
| 241 | write_hex (datain[63]); | |
| 242 | serial_puts (" != calc. chksum: 0x"); | |
| 243 | write_hex (spd_chksum); | |
| 244 | serial_puts ("\n"); | |
| 245 | #endif | |
| 246 | SDRAM_err ("SPD checksum Error"); | |
| 247 | } | |
| 248 | /* SPD seems to be ok, use it */ | |
| 249 | ||
| 250 | /* get SPD version */ | |
| 251 | spd_version = datain[62]; | |
| 252 | ||
| 253 | /* do some sanity checks on the kind of RAM */ | |
| 254 | if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */ | |
| 255 | (datain[2] != 0x04) || /* if not SDRAM */ | |
| 256 | (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ | |
| 257 | (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ | |
| 8ed44d91 | 258 | (datain[126] == 0x66)) /* or a 66MHz modules */ |
| 7d393aed WD |
259 | SDRAM_err ("unsupported SDRAM"); |
| 260 | #ifdef SDRAM_DEBUG | |
| 261 | serial_puts ("SDRAM sanity ok\n"); | |
| 262 | #endif | |
| 263 | ||
| 264 | /* get number of rows/cols/banks out of byte 3+4+5 */ | |
| 265 | rows = datain[3]; | |
| 266 | cols = datain[4]; | |
| 267 | banks = datain[5]; | |
| 268 | ||
| 269 | /* get number of SDRAM banks out of byte 17 and | |
| 270 | supported CAS latencies out of byte 18 */ | |
| 271 | sdram_banks = datain[17]; | |
| 272 | supported_cal = datain[18] & ~0x81; | |
| 273 | ||
| 274 | while (t->mode != 0) { | |
| 275 | if ((t->row == rows) && (t->col == cols) | |
| 276 | && (t->bank == sdram_banks)) | |
| 277 | break; | |
| 278 | t++; | |
| 279 | } /* endwhile */ | |
| 280 | ||
| 281 | #ifdef SDRAM_DEBUG | |
| 282 | serial_puts ("rows: "); | |
| 283 | write_hex (rows); | |
| 284 | serial_puts (" cols: "); | |
| 285 | write_hex (cols); | |
| 286 | serial_puts (" banks: "); | |
| 287 | write_hex (banks); | |
| 288 | serial_puts (" mode: "); | |
| 289 | write_hex (t->mode); | |
| 290 | serial_puts ("\n"); | |
| 291 | #endif | |
| 292 | if (t->mode == 0) | |
| 293 | SDRAM_err ("unsupported SDRAM"); | |
| 294 | /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */ | |
| 295 | #ifdef SDRAM_DEBUG | |
| 296 | serial_puts ("tRP: "); | |
| 297 | write_hex (datain[27]); | |
| 298 | serial_puts ("\ntRCD: "); | |
| 299 | write_hex (datain[29]); | |
| 300 | serial_puts ("\ntRAS: "); | |
| 301 | write_hex (datain[30]); | |
| 302 | serial_puts ("\n"); | |
| 303 | #endif | |
| 304 | ||
| 305 | trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk; | |
| 306 | trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk; | |
| 307 | tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk; | |
| 308 | density = datain[31]; | |
| 309 | ||
| 310 | /* trc_clocks is sum of trp_clocks + tras_clocks */ | |
| 311 | trc_clocks = trp_clocks + tras_clocks; | |
| 4e11c351 SR |
312 | |
| 313 | #ifdef SDRAM_DEBUG | |
| 7d393aed WD |
314 | /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ |
| 315 | tctp_clocks = | |
| 316 | ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + | |
| 317 | (tmemclk - 1)) / tmemclk; | |
| 318 | ||
| 7d393aed WD |
319 | serial_puts ("c_RP: "); |
| 320 | write_hex (trp_clocks); | |
| 321 | serial_puts ("\nc_RCD: "); | |
| 322 | write_hex (trcd_clocks); | |
| 323 | serial_puts ("\nc_RAS: "); | |
| 324 | write_hex (tras_clocks); | |
| 325 | serial_puts ("\nc_RC: (RP+RAS): "); | |
| 326 | write_hex (trc_clocks); | |
| 327 | serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): "); | |
| 328 | write_hex (tctp_clocks); | |
| 329 | serial_puts ("\nt_CTP: RAS - RCD: "); | |
| 330 | write_hex ((unsigned | |
| 331 | char) ((NSto10PS (datain[30]) - | |
| 332 | NSto10PS (datain[29])) >> 8)); | |
| 333 | write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29]))); | |
| 334 | serial_puts ("\ntmemclk: "); | |
| 335 | write_hex ((unsigned char) (tmemclk >> 8)); | |
| 336 | write_hex ((unsigned char) (tmemclk)); | |
| 337 | serial_puts ("\n"); | |
| 338 | #endif | |
| 339 | ||
| 340 | ||
| 341 | cal_val = 255; | |
| 342 | for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) { | |
| 343 | /* is this CAS latency supported ? */ | |
| 344 | if ((supported_cal >> i) & 0x01) { | |
| 345 | buf[0] = datain[cal_indextable[cal_index]]; | |
| 346 | if (cal_index < 2) { | |
| 347 | if (NS10to10PS (buf[0], spd_version) <= tmemclk) | |
| 348 | cal_val = i; | |
| 349 | } else { | |
| 350 | /* SPD bytes 25+26 have another format */ | |
| 351 | if (NS4to10PS (buf[0], spd_version) <= tmemclk) | |
| 352 | cal_val = i; | |
| 353 | } /* endif */ | |
| 354 | cal_index++; | |
| 355 | } /* endif */ | |
| 356 | } /* endfor */ | |
| 357 | #ifdef SDRAM_DEBUG | |
| 358 | serial_puts ("CAL: "); | |
| 359 | write_hex (cal_val + 1); | |
| 360 | serial_puts ("\n"); | |
| 361 | #endif | |
| 362 | ||
| 363 | if (cal_val == 255) | |
| 364 | SDRAM_err ("unsupported SDRAM"); | |
| 365 | ||
| 366 | /* get SDRAM timing register */ | |
| 95b602ba | 367 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
| d1c3b275 | 368 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; |
| 7d393aed WD |
369 | /* insert CASL value */ |
| 370 | /* tmp |= ((unsigned long)cal_val) << 23; */ | |
| 371 | tmp |= ((unsigned long) cal_val) << 23; | |
| 372 | /* insert PTA value */ | |
| 373 | tmp |= ((unsigned long) (trp_clocks - 1)) << 18; | |
| 374 | /* insert CTP value */ | |
| 375 | /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */ | |
| 376 | tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16; | |
| 377 | /* insert LDF (always 01) */ | |
| 378 | tmp |= ((unsigned long) 0x01) << 14; | |
| 379 | /* insert RFTA value */ | |
| 380 | tmp |= ((unsigned long) (trc_clocks - 4)) << 2; | |
| 381 | /* insert RCD value */ | |
| 382 | tmp |= ((unsigned long) (trcd_clocks - 1)) << 0; | |
| 383 | ||
| 384 | #ifdef SDRAM_DEBUG | |
| 385 | serial_puts ("sdtr: "); | |
| 386 | write_4hex (tmp); | |
| 387 | serial_puts ("\n"); | |
| 388 | #endif | |
| 389 | ||
| 390 | /* write SDRAM timing register */ | |
| 95b602ba | 391 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
| d1c3b275 | 392 | mtdcr (SDRAM0_CFGDATA, tmp); |
| 6d0f6bcf | 393 | baseaddr = CONFIG_SYS_SDRAM_BASE; |
| 7d393aed WD |
394 | bank_size = (((unsigned long) density) << 22) / 2; |
| 395 | /* insert AM value */ | |
| 396 | tmp = ((unsigned long) t->mode - 1) << 13; | |
| 397 | /* insert SZ value; */ | |
| 398 | switch (bank_size) { | |
| 399 | case 0x00400000: | |
| 400 | tmp |= ((unsigned long) 0x00) << 17; | |
| 401 | break; | |
| 402 | case 0x00800000: | |
| 403 | tmp |= ((unsigned long) 0x01) << 17; | |
| 404 | break; | |
| 405 | case 0x01000000: | |
| 406 | tmp |= ((unsigned long) 0x02) << 17; | |
| 407 | break; | |
| 408 | case 0x02000000: | |
| 409 | tmp |= ((unsigned long) 0x03) << 17; | |
| 410 | break; | |
| 411 | case 0x04000000: | |
| 412 | tmp |= ((unsigned long) 0x04) << 17; | |
| 413 | break; | |
| 414 | case 0x08000000: | |
| 415 | tmp |= ((unsigned long) 0x05) << 17; | |
| 416 | break; | |
| 417 | case 0x10000000: | |
| 418 | tmp |= ((unsigned long) 0x06) << 17; | |
| 419 | break; | |
| 420 | default: | |
| 421 | SDRAM_err ("unsupported SDRAM"); | |
| 422 | } /* endswitch */ | |
| 423 | /* get SDRAM bank 0 register */ | |
| 95b602ba | 424 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
| d1c3b275 | 425 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
| 7d393aed WD |
426 | bank |= (baseaddr | tmp | 0x01); |
| 427 | #ifdef SDRAM_DEBUG | |
| 428 | serial_puts ("bank0: baseaddr: "); | |
| 429 | write_4hex (baseaddr); | |
| 430 | serial_puts (" banksize: "); | |
| 431 | write_4hex (bank_size); | |
| 432 | serial_puts (" mb0cf: "); | |
| 433 | write_4hex (bank); | |
| 434 | serial_puts ("\n"); | |
| 435 | #endif | |
| 436 | baseaddr += bank_size; | |
| 437 | sdram_size += bank_size; | |
| 438 | ||
| 439 | /* write SDRAM bank 0 register */ | |
| 95b602ba | 440 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
| d1c3b275 | 441 | mtdcr (SDRAM0_CFGDATA, bank); |
| 7d393aed WD |
442 | |
| 443 | /* get SDRAM bank 1 register */ | |
| 95b602ba | 444 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
| d1c3b275 | 445 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
| 7d393aed WD |
446 | sdram_size = 0; |
| 447 | ||
| 448 | #ifdef SDRAM_DEBUG | |
| 449 | serial_puts ("bank1: baseaddr: "); | |
| 450 | write_4hex (baseaddr); | |
| 451 | serial_puts (" banksize: "); | |
| 452 | write_4hex (bank_size); | |
| 453 | #endif | |
| 454 | if (banks == 2) { | |
| 455 | bank |= (baseaddr | tmp | 0x01); | |
| 456 | baseaddr += bank_size; | |
| 457 | sdram_size += bank_size; | |
| 458 | } /* endif */ | |
| 459 | #ifdef SDRAM_DEBUG | |
| 460 | serial_puts (" mb1cf: "); | |
| 461 | write_4hex (bank); | |
| 462 | serial_puts ("\n"); | |
| 463 | #endif | |
| 464 | /* write SDRAM bank 1 register */ | |
| 95b602ba | 465 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
| d1c3b275 | 466 | mtdcr (SDRAM0_CFGDATA, bank); |
| 7d393aed WD |
467 | |
| 468 | /* get SDRAM bank 2 register */ | |
| 95b602ba | 469 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
| d1c3b275 | 470 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
| 7d393aed WD |
471 | |
| 472 | bank |= (baseaddr | tmp | 0x01); | |
| 473 | ||
| 474 | #ifdef SDRAM_DEBUG | |
| 475 | serial_puts ("bank2: baseaddr: "); | |
| 476 | write_4hex (baseaddr); | |
| 477 | serial_puts (" banksize: "); | |
| 478 | write_4hex (bank_size); | |
| 479 | serial_puts (" mb2cf: "); | |
| 480 | write_4hex (bank); | |
| 481 | serial_puts ("\n"); | |
| 482 | #endif | |
| 483 | ||
| 484 | baseaddr += bank_size; | |
| 485 | sdram_size += bank_size; | |
| 486 | ||
| 487 | /* write SDRAM bank 2 register */ | |
| 95b602ba | 488 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
| d1c3b275 | 489 | mtdcr (SDRAM0_CFGDATA, bank); |
| 7d393aed WD |
490 | |
| 491 | /* get SDRAM bank 3 register */ | |
| 95b602ba | 492 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
| d1c3b275 | 493 | bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; |
| 7d393aed WD |
494 | |
| 495 | #ifdef SDRAM_DEBUG | |
| 496 | serial_puts ("bank3: baseaddr: "); | |
| 497 | write_4hex (baseaddr); | |
| 498 | serial_puts (" banksize: "); | |
| 499 | write_4hex (bank_size); | |
| 500 | #endif | |
| 501 | ||
| 502 | if (banks == 2) { | |
| 503 | bank |= (baseaddr | tmp | 0x01); | |
| 504 | baseaddr += bank_size; | |
| 505 | sdram_size += bank_size; | |
| 506 | } | |
| 507 | /* endif */ | |
| 508 | #ifdef SDRAM_DEBUG | |
| 509 | serial_puts (" mb3cf: "); | |
| 510 | write_4hex (bank); | |
| 511 | serial_puts ("\n"); | |
| 512 | #endif | |
| 513 | ||
| 514 | /* write SDRAM bank 3 register */ | |
| 95b602ba | 515 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
| d1c3b275 | 516 | mtdcr (SDRAM0_CFGDATA, bank); |
| 7d393aed WD |
517 | |
| 518 | ||
| 519 | /* get SDRAM refresh interval register */ | |
| 95b602ba | 520 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
| d1c3b275 | 521 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; |
| 7d393aed WD |
522 | |
| 523 | if (tmemclk < NSto10PS (16)) | |
| 524 | tmp |= 0x05F00000; | |
| 525 | else | |
| 526 | tmp |= 0x03F80000; | |
| 527 | ||
| 528 | /* write SDRAM refresh interval register */ | |
| 95b602ba | 529 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
| d1c3b275 | 530 | mtdcr (SDRAM0_CFGDATA, tmp); |
| 7d393aed WD |
531 | |
| 532 | /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ | |
| 95b602ba | 533 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
| d1c3b275 | 534 | tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; |
| 95b602ba | 535 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
| d1c3b275 | 536 | mtdcr (SDRAM0_CFGDATA, tmp); |
| 7d393aed WD |
537 | |
| 538 | ||
| 7d393aed WD |
539 | /*-------------------------------------------------------------------------+ |
| 540 | | Interrupt controller setup for the PIP405 board. | |
| 541 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
| 542 | | IRQ 16 405GP internally generated; active low; level sensitive | |
| 543 | | IRQ 17-24 RESERVED | |
| 544 | | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive | |
| 545 | | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive | |
| 546 | | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive | |
| 547 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive | |
| 548 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
| 549 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive | |
| 550 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive | |
| 551 | | Note for PIP405 board: | |
| 552 | | An interrupt taken for the SouthBridge (IRQ 25) indicates that | |
| 553 | | the Interrupt Controller in the South Bridge has caused the | |
| 554 | | interrupt. The IC must be read to determine which device | |
| 555 | | caused the interrupt. | |
| 556 | | | |
| 557 | +-------------------------------------------------------------------------*/ | |
| 952e7760 SR |
558 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
| 559 | mtdcr (UIC0ER, 0x00000000); /* disable all ints */ | |
| 560 | mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ | |
| 561 | mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ | |
| 562 | mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ | |
| 563 | mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
| 564 | mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ | |
| 7d393aed WD |
565 | |
| 566 | return 0; | |
| 567 | } | |
| 568 | ||
| 21be309b DM |
569 | int board_early_init_r(void) |
| 570 | { | |
| 571 | int mode; | |
| 572 | ||
| 573 | /* | |
| 574 | * since we are relocated, we can finally enable i-cache | |
| 575 | * and set up the flash CS correctly | |
| 576 | */ | |
| 577 | icache_enable(); | |
| 578 | setup_cs_reloc(); | |
| 579 | /* get and display boot mode */ | |
| 580 | mode = get_boot_mode(); | |
| 581 | if (mode & BOOT_PCI) | |
| 582 | printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? | |
| 583 | "MPS" : "Flash"); | |
| 584 | else | |
| 585 | printf("%s Boot\n", (mode & BOOT_MPS) ? | |
| 586 | "MPS" : "Flash"); | |
| 7d393aed | 587 | |
| 21be309b DM |
588 | return 0; |
| 589 | } | |
| 7d393aed WD |
590 | /* ------------------------------------------------------------------------- */ |
| 591 | ||
| 592 | /* | |
| 593 | * Check Board Identity: | |
| 594 | */ | |
| 595 | ||
| 596 | int checkboard (void) | |
| 597 | { | |
| 77ddac94 | 598 | char s[50]; |
| 7d393aed WD |
599 | unsigned char bc; |
| 600 | int i; | |
| 601 | backup_t *b = (backup_t *) s; | |
| 602 | ||
| 603 | puts ("Board: "); | |
| 604 | ||
| cdb74977 | 605 | i = getenv_f("serial#", (char *)s, 32); |
| 77ddac94 | 606 | if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) { |
| 7d393aed WD |
607 | get_backup_values (b); |
| 608 | if (strncmp (b->signature, "MPL\0", 4) != 0) { | |
| 609 | puts ("### No HW ID - assuming PIP405"); | |
| 610 | } else { | |
| 611 | b->serial_name[6] = 0; | |
| 612 | printf ("%s SN: %s", b->serial_name, | |
| 613 | &b->serial_name[7]); | |
| 614 | } | |
| 615 | } else { | |
| 616 | s[6] = 0; | |
| 617 | printf ("%s SN: %s", s, &s[7]); | |
| 618 | } | |
| 619 | bc = in8 (CONFIG_PORT_ADDR); | |
| 620 | printf (" Boot Config: 0x%x\n", bc); | |
| 621 | return (0); | |
| 622 | } | |
| 623 | ||
| 624 | ||
| 625 | /* ------------------------------------------------------------------------- */ | |
| 626 | /* ------------------------------------------------------------------------- */ | |
| 627 | /* | |
| 628 | initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of | |
| 629 | the necessary info for SDRAM controller configuration | |
| 630 | */ | |
| 631 | /* ------------------------------------------------------------------------- */ | |
| 632 | /* ------------------------------------------------------------------------- */ | |
| 633 | static int test_dram (unsigned long ramsize); | |
| 634 | ||
| 9973e3c6 | 635 | phys_size_t initdram (int board_type) |
| 7d393aed | 636 | { |
| 7d393aed WD |
637 | unsigned long bank_reg[4], tmp, bank_size; |
| 638 | int i, ds; | |
| 639 | unsigned long TotalSize; | |
| 640 | ||
| 641 | ds = 0; | |
| 642 | /* since the DRAM controller is allready set up, | |
| 643 | * calculate the size with the bank registers | |
| 644 | */ | |
| 95b602ba | 645 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
| d1c3b275 | 646 | bank_reg[0] = mfdcr (SDRAM0_CFGDATA); |
| 95b602ba | 647 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
| d1c3b275 | 648 | bank_reg[1] = mfdcr (SDRAM0_CFGDATA); |
| 95b602ba | 649 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
| d1c3b275 | 650 | bank_reg[2] = mfdcr (SDRAM0_CFGDATA); |
| 95b602ba | 651 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
| d1c3b275 | 652 | bank_reg[3] = mfdcr (SDRAM0_CFGDATA); |
| 7d393aed WD |
653 | TotalSize = 0; |
| 654 | for (i = 0; i < 4; i++) { | |
| 655 | if ((bank_reg[i] & 0x1) == 0x1) { | |
| 656 | tmp = (bank_reg[i] >> 17) & 0x7; | |
| 657 | bank_size = 4 << tmp; | |
| 658 | TotalSize += bank_size; | |
| 659 | } else | |
| 660 | ds = 1; | |
| 661 | } | |
| 662 | if (ds == 1) | |
| 663 | printf ("single-sided DIMM "); | |
| 664 | else | |
| 665 | printf ("double-sided DIMM "); | |
| 666 | test_dram (TotalSize * 1024 * 1024); | |
| 667 | /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */ | |
| 668 | (void) get_clocks(); | |
| 669 | if (gd->cpu_clk > 220000000) | |
| 670 | TotalSize /= 2; | |
| 671 | return (TotalSize * 1024 * 1024); | |
| 672 | } | |
| 673 | ||
| 674 | /* ------------------------------------------------------------------------- */ | |
| 675 | ||
| 676 | ||
| 677 | static int test_dram (unsigned long ramsize) | |
| 678 | { | |
| 679 | /* not yet implemented */ | |
| 680 | return (1); | |
| 681 | } | |
| 682 | ||
| 7d393aed WD |
683 | int misc_init_r (void) |
| 684 | { | |
| 7205e407 WD |
685 | /* adjust flash start and size as well as the offset */ |
| 686 | gd->bd->bi_flashstart=0-flash_info[0].size; | |
| 6d0f6bcf | 687 | gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; |
| 7205e407 WD |
688 | gd->bd->bi_flashoffset=0; |
| 689 | ||
| 690 | /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ | |
| d1c3b275 | 691 | if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) |
| 58ea142f | 692 | mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); |
| 7205e407 | 693 | |
| 7d393aed WD |
694 | return (0); |
| 695 | } | |
| 696 | ||
| 697 | /*************************************************************************** | |
| 698 | * some helping routines | |
| 699 | */ | |
| 700 | ||
| 701 | int overwrite_console (void) | |
| 702 | { | |
| 703 | return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */ | |
| 704 | } | |
| 705 | ||
| 706 | ||
| 7d393aed WD |
707 | extern int isa_init (void); |
| 708 | ||
| 709 | ||
| 710 | void print_pip405_rev (void) | |
| 711 | { | |
| 712 | unsigned char part, vers, cfg; | |
| 713 | ||
| 714 | part = in8 (PLD_PART_REG); | |
| 715 | vers = in8 (PLD_VERS_REG); | |
| 716 | cfg = in8 (PLD_BOARD_CFG_REG); | |
| 717 | printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n", | |
| 718 | 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf, | |
| 719 | vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf); | |
| 720 | } | |
| 721 | ||
| 722 | extern void check_env(void); | |
| 723 | ||
| 724 | ||
| 725 | int last_stage_init (void) | |
| 726 | { | |
| 727 | print_pip405_rev (); | |
| 728 | isa_init (); | |
| 28c34504 | 729 | stdio_print_current_devices (); |
| 7d393aed WD |
730 | check_env(); |
| 731 | return 0; | |
| 732 | } | |
| 733 | ||
| 734 | /************************************************************************ | |
| 735 | * Print PIP405 Info | |
| 736 | ************************************************************************/ | |
| 737 | void print_pip405_info (void) | |
| 738 | { | |
| 739 | unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr, | |
| 740 | compwr, nicvga, scsirst; | |
| 741 | ||
| 742 | part = in8 (PLD_PART_REG); | |
| 743 | vers = in8 (PLD_VERS_REG); | |
| 744 | cfg = in8 (PLD_BOARD_CFG_REG); | |
| 745 | ledu = in8 (PLD_LED_USER_REG); | |
| 746 | sysman = in8 (PLD_SYS_MAN_REG); | |
| 747 | flashcom = in8 (PLD_FLASH_COM_REG); | |
| 748 | can = in8 (PLD_CAN_REG); | |
| 749 | serpwr = in8 (PLD_SER_PWR_REG); | |
| 750 | compwr = in8 (PLD_COM_PWR_REG); | |
| 751 | nicvga = in8 (PLD_NIC_VGA_REG); | |
| 752 | scsirst = in8 (PLD_SCSI_RST_REG); | |
| 753 | printf ("PLD Part %d version %d\n", | |
| 754 | part & 0xf, vers & 0xf); | |
| 755 | printf ("PLD Part %d version %d\n", | |
| 756 | (part >> 4) & 0xf, (vers >> 4) & 0xf); | |
| 757 | printf ("Board Revision %c\n", (cfg & 0xf) + 'A'); | |
| 758 | printf ("Population Options %d %d %d %d\n", | |
| 759 | (cfg >> 4) & 0x1, (cfg >> 5) & 0x1, | |
| 760 | (cfg >> 6) & 0x1, (cfg >> 7) & 0x1); | |
| 761 | printf ("User LED0 %s User LED1 %s\n", | |
| 762 | ((ledu & 0x1) == 0x1) ? "on" : "off", | |
| 763 | ((ledu & 0x2) == 0x2) ? "on" : "off"); | |
| 764 | printf ("Additionally Options %d %d\n", | |
| 765 | (ledu >> 2) & 0x1, (ledu >> 3) & 0x1); | |
| 766 | printf ("User Config Switch %d %d %d %d\n", | |
| 767 | (ledu >> 4) & 0x1, (ledu >> 5) & 0x1, | |
| 768 | (ledu >> 6) & 0x1, (ledu >> 7) & 0x1); | |
| 769 | switch (sysman & 0x3) { | |
| 770 | case 0: | |
| 771 | printf ("PCI Clocks are running\n"); | |
| 772 | break; | |
| 773 | case 1: | |
| 774 | printf ("PCI Clocks are stopped in POS State\n"); | |
| 775 | break; | |
| 776 | case 2: | |
| 777 | printf ("PCI Clocks are stopped when PCI_STP# is asserted\n"); | |
| 778 | break; | |
| 779 | case 3: | |
| 780 | printf ("PCI Clocks are stopped\n"); | |
| 781 | break; | |
| 782 | } | |
| 783 | switch ((sysman >> 2) & 0x3) { | |
| 784 | case 0: | |
| 785 | printf ("Main Clocks are running\n"); | |
| 786 | break; | |
| 787 | case 1: | |
| 788 | printf ("Main Clocks are stopped in POS State\n"); | |
| 789 | break; | |
| 790 | case 2: | |
| 791 | case 3: | |
| 792 | printf ("PCI Clocks are stopped\n"); | |
| 793 | break; | |
| 794 | } | |
| 795 | printf ("INIT asserts %sINT2# (SMI)\n", | |
| 796 | ((sysman & 0x10) == 0x10) ? "" : "not "); | |
| 797 | printf ("INIT asserts %sINT1# (NMI)\n", | |
| 798 | ((sysman & 0x20) == 0x20) ? "" : "not "); | |
| 799 | printf ("INIT occured %d\n", (sysman >> 6) & 0x1); | |
| 800 | printf ("SER1 is routed to %s\n", | |
| 801 | ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232"); | |
| 802 | printf ("COM2 is routed to %s\n", | |
| 803 | ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232"); | |
| 804 | printf ("RS485 is configured as %s duplex\n", | |
| 805 | ((flashcom & 0x4) == 0x4) ? "full" : "half"); | |
| 806 | printf ("RS485 is connected to %s\n", | |
| 807 | ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2"); | |
| 808 | printf ("SER1 uses handshakes %s\n", | |
| 809 | ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS"); | |
| 810 | printf ("Bootflash is %swriteprotected\n", | |
| 811 | ((flashcom & 0x20) == 0x20) ? "not " : ""); | |
| 812 | printf ("Bootflash VPP is %s\n", | |
| 813 | ((flashcom & 0x40) == 0x40) ? "on" : "off"); | |
| 814 | printf ("Bootsector is %swriteprotected\n", | |
| 815 | ((flashcom & 0x80) == 0x80) ? "not " : ""); | |
| 816 | switch ((can) & 0x3) { | |
| 817 | case 0: | |
| 818 | printf ("CAN Controller is on address 0x1000..0x10FF\n"); | |
| 819 | break; | |
| 820 | case 1: | |
| 821 | printf ("CAN Controller is on address 0x8000..0x80FF\n"); | |
| 822 | break; | |
| 823 | case 2: | |
| 824 | printf ("CAN Controller is on address 0xE000..0xE0FF\n"); | |
| 825 | break; | |
| 826 | case 3: | |
| 827 | printf ("CAN Controller is disabled\n"); | |
| 828 | break; | |
| 829 | } | |
| 830 | switch ((can >> 2) & 0x3) { | |
| 831 | case 0: | |
| 832 | printf ("CAN Controller Reset is ISA Reset\n"); | |
| 833 | break; | |
| 834 | case 1: | |
| 835 | printf ("CAN Controller Reset is ISA Reset and POS State\n"); | |
| 836 | break; | |
| 837 | case 2: | |
| 838 | case 3: | |
| 839 | printf ("CAN Controller is in reset\n"); | |
| 840 | break; | |
| 841 | } | |
| 842 | if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13)) | |
| 843 | printf ("CAN Interrupt is disabled\n"); | |
| 844 | else | |
| 845 | printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf); | |
| 846 | switch (serpwr & 0x3) { | |
| 847 | case 0: | |
| 848 | printf ("SER0 Drivers are enabled\n"); | |
| 849 | break; | |
| 850 | case 1: | |
| 851 | printf ("SER0 Drivers are disabled in the POS state\n"); | |
| 852 | break; | |
| 853 | case 2: | |
| 854 | case 3: | |
| 855 | printf ("SER0 Drivers are disabled\n"); | |
| 856 | break; | |
| 857 | } | |
| 858 | switch ((serpwr >> 2) & 0x3) { | |
| 859 | case 0: | |
| 860 | printf ("SER1 Drivers are enabled\n"); | |
| 861 | break; | |
| 862 | case 1: | |
| 863 | printf ("SER1 Drivers are disabled in the POS state\n"); | |
| 864 | break; | |
| 865 | case 2: | |
| 866 | case 3: | |
| 867 | printf ("SER1 Drivers are disabled\n"); | |
| 868 | break; | |
| 869 | } | |
| 870 | switch (compwr & 0x3) { | |
| 871 | case 0: | |
| 872 | printf ("COM1 Drivers are enabled\n"); | |
| 873 | break; | |
| 874 | case 1: | |
| 875 | printf ("COM1 Drivers are disabled in the POS state\n"); | |
| 876 | break; | |
| 877 | case 2: | |
| 878 | case 3: | |
| 879 | printf ("COM1 Drivers are disabled\n"); | |
| 880 | break; | |
| 881 | } | |
| 882 | switch ((compwr >> 2) & 0x3) { | |
| 883 | case 0: | |
| 884 | printf ("COM2 Drivers are enabled\n"); | |
| 885 | break; | |
| 886 | case 1: | |
| 887 | printf ("COM2 Drivers are disabled in the POS state\n"); | |
| 888 | break; | |
| 889 | case 2: | |
| 890 | case 3: | |
| 891 | printf ("COM2 Drivers are disabled\n"); | |
| 892 | break; | |
| 893 | } | |
| 894 | switch ((nicvga) & 0x3) { | |
| 895 | case 0: | |
| 896 | printf ("PHY is running\n"); | |
| 897 | break; | |
| 898 | case 1: | |
| 899 | printf ("PHY is in Power save mode in POS state\n"); | |
| 900 | break; | |
| 901 | case 2: | |
| 902 | case 3: | |
| 903 | printf ("PHY is in Power save mode\n"); | |
| 904 | break; | |
| 905 | } | |
| 906 | switch ((nicvga >> 2) & 0x3) { | |
| 907 | case 0: | |
| 908 | printf ("VGA is running\n"); | |
| 909 | break; | |
| 910 | case 1: | |
| 911 | printf ("VGA is in Power save mode in POS state\n"); | |
| 912 | break; | |
| 913 | case 2: | |
| 914 | case 3: | |
| 915 | printf ("VGA is in Power save mode\n"); | |
| 916 | break; | |
| 917 | } | |
| 918 | printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not "); | |
| 919 | printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not "); | |
| 920 | printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1, | |
| 921 | (nicvga >> 7) & 0x1); | |
| 922 | switch ((scsirst) & 0x3) { | |
| 923 | case 0: | |
| 924 | printf ("SCSI Controller is running\n"); | |
| 925 | break; | |
| 926 | case 1: | |
| 927 | printf ("SCSI Controller is in Power save mode in POS state\n"); | |
| 928 | break; | |
| 929 | case 2: | |
| 930 | case 3: | |
| 931 | printf ("SCSI Controller is in Power save mode\n"); | |
| 932 | break; | |
| 933 | } | |
| 934 | printf ("SCSI termination is %s\n", | |
| 935 | ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled"); | |
| 936 | printf ("SCSI Controller is %sreseted\n", | |
| 937 | ((scsirst & 0x10) == 0x10) ? "" : "not "); | |
| 938 | printf ("IDE disks are %sreseted\n", | |
| 939 | ((scsirst & 0x20) == 0x20) ? "" : "not "); | |
| 940 | printf ("ISA Bus is %sreseted\n", | |
| 941 | ((scsirst & 0x40) == 0x40) ? "" : "not "); | |
| 942 | printf ("Super IO is %sreseted\n", | |
| 943 | ((scsirst & 0x80) == 0x80) ? "" : "not "); | |
| 944 | } | |
| 945 | ||
| 946 | void user_led0 (unsigned char on) | |
| 947 | { | |
| 948 | if (on == TRUE) | |
| 949 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1)); | |
| 950 | else | |
| 951 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe)); | |
| 952 | } | |
| 953 | ||
| 954 | void user_led1 (unsigned char on) | |
| 955 | { | |
| 956 | if (on == TRUE) | |
| 957 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2)); | |
| 958 | else | |
| 959 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd)); | |
| 960 | } | |
| 961 | ||
| 962 | void ide_set_reset (int idereset) | |
| 963 | { | |
| 964 | /* if reset = 1 IDE reset will be asserted */ | |
| 965 | unsigned char resreg; | |
| 966 | ||
| 967 | resreg = in8 (PLD_SCSI_RST_REG); | |
| 968 | if (idereset == 1) | |
| 969 | resreg |= 0x20; | |
| 970 | else { | |
| 971 | udelay(10000); | |
| 972 | resreg &= 0xdf; | |
| 973 | } | |
| 974 | out8 (PLD_SCSI_RST_REG, resreg); | |
| 975 | } |